diff options
Diffstat (limited to 'arch/arm/mach-mx5/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index b462c22f53d8..87c0c58f27a7 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h | |||
| @@ -217,9 +217,12 @@ | |||
| 217 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) | 217 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) |
| 218 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) | 218 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) |
| 219 | #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) | 219 | #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) |
| 220 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) | ||
| 220 | #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) | 221 | #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) |
| 221 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) | 222 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) |
| 222 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) | 223 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) |
| 224 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) | ||
| 225 | #define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) | ||
| 223 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) | 226 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) |
| 224 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) | 227 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) |
| 225 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) | 228 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) |
| @@ -271,6 +274,10 @@ | |||
| 271 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) | 274 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) |
| 272 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) | 275 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) |
| 273 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) | 276 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) |
| 277 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) | ||
| 278 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) | ||
| 279 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) | ||
| 280 | #define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) | ||
| 274 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) | 281 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) |
| 275 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) | 282 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) |
| 276 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) | 283 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) |