diff options
Diffstat (limited to 'arch/arm/mach-mx5/cpu.c')
-rw-r--r-- | arch/arm/mach-mx5/cpu.c | 55 |
1 files changed, 24 insertions, 31 deletions
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index a00d2bc7246a..d40671da4372 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
@@ -20,37 +20,18 @@ | |||
20 | 20 | ||
21 | static int cpu_silicon_rev = -1; | 21 | static int cpu_silicon_rev = -1; |
22 | 22 | ||
23 | #define SI_REV 0x48 | 23 | #define IIM_SREV 0x24 |
24 | 24 | ||
25 | static void query_silicon_parameter(void) | 25 | static int get_mx51_srev(void) |
26 | { | 26 | { |
27 | void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); | 27 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
28 | u32 rev; | 28 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; |
29 | 29 | ||
30 | if (!rom) { | 30 | if (rev == 0x0) |
31 | cpu_silicon_rev = -EINVAL; | 31 | return IMX_CHIP_REVISION_2_0; |
32 | return; | 32 | else if (rev == 0x10) |
33 | } | 33 | return IMX_CHIP_REVISION_3_0; |
34 | 34 | return 0; | |
35 | rev = readl(rom + SI_REV); | ||
36 | switch (rev) { | ||
37 | case 0x1: | ||
38 | cpu_silicon_rev = MX51_CHIP_REV_1_0; | ||
39 | break; | ||
40 | case 0x2: | ||
41 | cpu_silicon_rev = MX51_CHIP_REV_1_1; | ||
42 | break; | ||
43 | case 0x10: | ||
44 | cpu_silicon_rev = MX51_CHIP_REV_2_0; | ||
45 | break; | ||
46 | case 0x20: | ||
47 | cpu_silicon_rev = MX51_CHIP_REV_3_0; | ||
48 | break; | ||
49 | default: | ||
50 | cpu_silicon_rev = 0; | ||
51 | } | ||
52 | |||
53 | iounmap(rom); | ||
54 | } | 35 | } |
55 | 36 | ||
56 | /* | 37 | /* |
@@ -64,7 +45,7 @@ int mx51_revision(void) | |||
64 | return -EINVAL; | 45 | return -EINVAL; |
65 | 46 | ||
66 | if (cpu_silicon_rev == -1) | 47 | if (cpu_silicon_rev == -1) |
67 | query_silicon_parameter(); | 48 | cpu_silicon_rev = get_mx51_srev(); |
68 | 49 | ||
69 | return cpu_silicon_rev; | 50 | return cpu_silicon_rev; |
70 | } | 51 | } |
@@ -82,7 +63,7 @@ static int __init mx51_neon_fixup(void) | |||
82 | if (!cpu_is_mx51()) | 63 | if (!cpu_is_mx51()) |
83 | return 0; | 64 | return 0; |
84 | 65 | ||
85 | if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { | 66 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { |
86 | elf_hwcap &= ~HWCAP_NEON; | 67 | elf_hwcap &= ~HWCAP_NEON; |
87 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | 68 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); |
88 | } | 69 | } |
@@ -92,6 +73,18 @@ static int __init mx51_neon_fixup(void) | |||
92 | late_initcall(mx51_neon_fixup); | 73 | late_initcall(mx51_neon_fixup); |
93 | #endif | 74 | #endif |
94 | 75 | ||
76 | static int get_mx53_srev(void) | ||
77 | { | ||
78 | void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); | ||
79 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | ||
80 | |||
81 | if (rev == 0x0) | ||
82 | return IMX_CHIP_REVISION_1_0; | ||
83 | else if (rev == 0x10) | ||
84 | return IMX_CHIP_REVISION_2_0; | ||
85 | return 0; | ||
86 | } | ||
87 | |||
95 | /* | 88 | /* |
96 | * Returns: | 89 | * Returns: |
97 | * the silicon revision of the cpu | 90 | * the silicon revision of the cpu |
@@ -103,7 +96,7 @@ int mx53_revision(void) | |||
103 | return -EINVAL; | 96 | return -EINVAL; |
104 | 97 | ||
105 | if (cpu_silicon_rev == -1) | 98 | if (cpu_silicon_rev == -1) |
106 | query_silicon_parameter(); | 99 | cpu_silicon_rev = get_mx53_srev(); |
107 | 100 | ||
108 | return cpu_silicon_rev; | 101 | return cpu_silicon_rev; |
109 | } | 102 | } |