1 files changed, 59 insertions, 0 deletions

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index df46b5e60857..472bdfab2e55 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -21,6 +21,7 @@
 static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG  0xB0
 
 static int get_mx51_srev(void)
 {
@@ -51,6 +52,26 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+void mx51_display_revision(void)
+{
+        int rev;
+        char *srev;
+        rev = mx51_revision();
+
+        switch (rev) {
+        case IMX_CHIP_REVISION_2_0:
+                srev = IMX_CHIP_REVISION_2_0_STRING;
+                break;
+        case IMX_CHIP_REVISION_3_0:
+                srev = IMX_CHIP_REVISION_3_0_STRING;
+                break;
+        default:
+                srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+        }
+        printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
 #ifdef CONFIG_NEON
 
 /*
@@ -107,6 +128,44 @@ int mx53_revision(void)
 }
 EXPORT_SYMBOL(mx53_revision);
 
+static int get_mx50_srev(void)
+{
+        void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+        u32 rev;
+
+        if (!anatop) {
+                cpu_silicon_rev = -EINVAL;
+                return 0;
+        }
+
+        rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+        rev &= 0xff;
+
+        iounmap(anatop);
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_1_0;
+        else if (rev == 0x1)
+                return IMX_CHIP_REVISION_1_1;
+        return 0;
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+        if (!cpu_is_mx50())
+                return -EINVAL;
+
+        if (cpu_silicon_rev == -1)
+                cpu_silicon_rev = get_mx50_srev();
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;