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Diffstat (limited to 'arch/arm/mach-mx5/clock-mx51.c')
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 1ee6ce4087b8..d9f612d3370e 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -37,6 +37,7 @@ static struct clk lp_apm_clk;
37static struct clk periph_apm_clk; 37static struct clk periph_apm_clk;
38static struct clk ahb_clk; 38static struct clk ahb_clk;
39static struct clk ipg_clk; 39static struct clk ipg_clk;
40static struct clk usboh3_clk;
40 41
41#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
42 43
@@ -570,6 +571,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
570 return 0; 571 return 0;
571} 572}
572 573
574static unsigned long clk_usboh3_get_rate(struct clk *clk)
575{
576 u32 reg, prediv, podf;
577 unsigned long parent_rate;
578
579 parent_rate = clk_get_rate(clk->parent);
580
581 reg = __raw_readl(MXC_CCM_CSCDR1);
582 prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
583 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
584 podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
585 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
586
587 return parent_rate / (prediv * podf);
588}
589
590static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
591{
592 u32 reg, mux;
593
594 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
595 &lp_apm_clk);
596 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
597 reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
598 __raw_writel(reg, MXC_CCM_CSCMR1);
599
600 return 0;
601}
602
573static unsigned long get_high_reference_clock_rate(struct clk *clk) 603static unsigned long get_high_reference_clock_rate(struct clk *clk)
574{ 604{
575 return external_high_reference; 605 return external_high_reference;
@@ -691,6 +721,12 @@ static struct clk uart_root_clk = {
691 .set_parent = _clk_uart_set_parent, 721 .set_parent = _clk_uart_set_parent,
692}; 722};
693 723
724static struct clk usboh3_clk = {
725 .parent = &pll2_sw_clk,
726 .get_rate = clk_usboh3_get_rate,
727 .set_parent = _clk_usboh3_set_parent,
728};
729
694static struct clk ahb_max_clk = { 730static struct clk ahb_max_clk = {
695 .parent = &ahb_clk, 731 .parent = &ahb_clk,
696 .enable_reg = MXC_CCM_CCGR0, 732 .enable_reg = MXC_CCM_CCGR0,
@@ -779,6 +815,12 @@ static struct clk_lookup lookups[] = {
779 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 815 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
780 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 816 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
781 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 817 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
818 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
819 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
820 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
821 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
822 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
823 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
782}; 824};
783 825
784static void clk_tree_init(void) 826static void clk_tree_init(void)
@@ -819,6 +861,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
819 clk_enable(&cpu_clk); 861 clk_enable(&cpu_clk);
820 clk_enable(&main_bus_clk); 862 clk_enable(&main_bus_clk);
821 863
864 /* set the usboh3_clk parent to pll2_sw_clk */
865 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
866
822 /* System timer */ 867 /* System timer */
823 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 868 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
824 MX51_MXC_INT_GPT); 869 MX51_MXC_INT_GPT);