diff options
Diffstat (limited to 'arch/arm/mach-mx5/clock-mx51-mx53.c')
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 1ef7e97e0015..b94879e8679f 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -1434,6 +1434,10 @@ DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, | |||
1434 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, | 1434 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, |
1435 | NULL, NULL, &pll3_sw_clk, NULL); | 1435 | NULL, NULL, &pll3_sw_clk, NULL); |
1436 | 1436 | ||
1437 | /* PATA */ | ||
1438 | DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET, | ||
1439 | NULL, NULL, &ipg_clk, &spba_clk); | ||
1440 | |||
1437 | #define _REGISTER_CLOCK(d, n, c) \ | 1441 | #define _REGISTER_CLOCK(d, n, c) \ |
1438 | { \ | 1442 | { \ |
1439 | .dev_id = d, \ | 1443 | .dev_id = d, \ |
@@ -1490,6 +1494,7 @@ static struct clk_lookup mx51_lookups[] = { | |||
1490 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) | 1494 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) |
1491 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) | 1495 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) |
1492 | _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) | 1496 | _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) |
1497 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) | ||
1493 | }; | 1498 | }; |
1494 | 1499 | ||
1495 | static struct clk_lookup mx53_lookups[] = { | 1500 | static struct clk_lookup mx53_lookups[] = { |
@@ -1523,6 +1528,7 @@ static struct clk_lookup mx53_lookups[] = { | |||
1523 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 1528 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
1524 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) | 1529 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) |
1525 | _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) | 1530 | _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) |
1531 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) | ||
1526 | _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk) | 1532 | _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk) |
1527 | _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk) | 1533 | _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk) |
1528 | _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk) | 1534 | _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk) |
@@ -1567,9 +1573,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
1567 | clk_enable(&main_bus_clk); | 1573 | clk_enable(&main_bus_clk); |
1568 | 1574 | ||
1569 | clk_enable(&iim_clk); | 1575 | clk_enable(&iim_clk); |
1570 | mx51_revision(); | 1576 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
1571 | clk_disable(&iim_clk); | 1577 | clk_disable(&iim_clk); |
1572 | mx51_display_revision(); | ||
1573 | 1578 | ||
1574 | /* move usb_phy_clk to 24MHz */ | 1579 | /* move usb_phy_clk to 24MHz */ |
1575 | clk_set_parent(&usb_phy1_clk, &osc_clk); | 1580 | clk_set_parent(&usb_phy1_clk, &osc_clk); |
@@ -1587,7 +1592,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
1587 | 1592 | ||
1588 | /* System timer */ | 1593 | /* System timer */ |
1589 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), | 1594 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
1590 | MX51_MXC_INT_GPT); | 1595 | MX51_INT_GPT); |
1591 | return 0; | 1596 | return 0; |
1592 | } | 1597 | } |
1593 | 1598 | ||
@@ -1611,9 +1616,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, | |||
1611 | clk_enable(&main_bus_clk); | 1616 | clk_enable(&main_bus_clk); |
1612 | 1617 | ||
1613 | clk_enable(&iim_clk); | 1618 | clk_enable(&iim_clk); |
1614 | mx53_revision(); | 1619 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
1615 | clk_disable(&iim_clk); | 1620 | clk_disable(&iim_clk); |
1616 | mx53_display_revision(); | ||
1617 | 1621 | ||
1618 | /* Set SDHC parents to be PLL2 */ | 1622 | /* Set SDHC parents to be PLL2 */ |
1619 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); | 1623 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); |