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1 files changed, 121 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
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1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24
25#include <mach/common.h>
26#include <mach/hardware.h>
27#include <mach/iomux-mx51.h>
28#include <mach/i2c.h>
29#include <mach/mxc_ehci.h>
30
31#include <asm/irq.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx51.h"
38#include "devices.h"
39
40#define MX51_USB_PLL_DIV_24_MHZ 0x01
41
42static struct pad_desc mx51efikamx_pads[] = {
43 /* UART1 */
44 MX51_PAD_UART1_RXD__UART1_RXD,
45 MX51_PAD_UART1_TXD__UART1_TXD,
46 MX51_PAD_UART1_RTS__UART1_RTS,
47 MX51_PAD_UART1_CTS__UART1_CTS,
48};
49
50/* Serial ports */
51#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
52static const struct imxuart_platform_data uart_pdata = {
53 .flags = IMXUART_HAVE_RTSCTS,
54};
55
56static inline void mxc_init_imx_uart(void)
57{
58 imx51_add_imx_uart(0, &uart_pdata);
59 imx51_add_imx_uart(1, &uart_pdata);
60 imx51_add_imx_uart(2, &uart_pdata);
61}
62#else /* !SERIAL_IMX */
63static inline void mxc_init_imx_uart(void)
64{
65}
66#endif /* SERIAL_IMX */
67
68/* This function is board specific as the bit mask for the plldiv will also
69 * be different for other Freescale SoCs, thus a common bitmask is not
70 * possible and cannot get place in /plat-mxc/ehci.c.
71 */
72static int initialize_otg_port(struct platform_device *pdev)
73{
74 u32 v;
75 void __iomem *usb_base;
76 void __iomem *usbother_base;
77 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
78 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
79
80 /* Set the PHY clock to 19.2MHz */
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
82 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
83 v |= MX51_USB_PLL_DIV_24_MHZ;
84 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
85 iounmap(usb_base);
86 return 0;
87}
88
89static struct mxc_usbh_platform_data dr_utmi_config = {
90 .init = initialize_otg_port,
91 .portsc = MXC_EHCI_UTMI_16BIT,
92 .flags = MXC_EHCI_INTERNAL_PHY,
93};
94
95static void __init mxc_board_init(void)
96{
97 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
98 ARRAY_SIZE(mx51efikamx_pads));
99 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
100 mxc_init_imx_uart();
101}
102
103static void __init mx51_efikamx_timer_init(void)
104{
105 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
106}
107
108static struct sys_timer mxc_timer = {
109 .init = mx51_efikamx_timer_init,
110};
111
112MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
113 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
114 .phys_io = MX51_AIPS1_BASE_ADDR,
115 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
116 .boot_params = MX51_PHYS_OFFSET + 0x100,
117 .map_io = mx51_map_io,
118 .init_irq = mx51_init_irq,
119 .init_machine = mxc_board_init,
120 .timer = &mxc_timer,
121MACHINE_END