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Diffstat (limited to 'arch/arm/mach-mx5/board-cpuimx51.c')
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c31
1 files changed, 14 insertions, 17 deletions
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 4efa02ee1639..e2afe0c2a12e 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -36,17 +36,12 @@
36#include <asm/mach/time.h> 36#include <asm/mach/time.h>
37 37
38#include "devices-imx51.h" 38#include "devices-imx51.h"
39#include "devices.h"
40 39
41#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) 40#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
42#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) 41#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
43#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) 42#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
44#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) 43#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
45#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) 44#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
46#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
47#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
48#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
49#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
50#define CPUIMX51_QUART_XTAL 14745600 45#define CPUIMX51_QUART_XTAL 14745600
51#define CPUIMX51_QUART_REGSHIFT 17 46#define CPUIMX51_QUART_REGSHIFT 17
52 47
@@ -61,7 +56,7 @@
61static struct plat_serial8250_port serial_platform_data[] = { 56static struct plat_serial8250_port serial_platform_data[] = {
62 { 57 {
63 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), 58 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
64 .irq = CPUIMX51_QUARTA_IRQ, 59 .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
65 .irqflags = IRQF_TRIGGER_HIGH, 60 .irqflags = IRQF_TRIGGER_HIGH,
66 .uartclk = CPUIMX51_QUART_XTAL, 61 .uartclk = CPUIMX51_QUART_XTAL,
67 .regshift = CPUIMX51_QUART_REGSHIFT, 62 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -69,7 +64,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
69 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 64 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
70 }, { 65 }, {
71 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), 66 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
72 .irq = CPUIMX51_QUARTB_IRQ, 67 .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
73 .irqflags = IRQF_TRIGGER_HIGH, 68 .irqflags = IRQF_TRIGGER_HIGH,
74 .uartclk = CPUIMX51_QUART_XTAL, 69 .uartclk = CPUIMX51_QUART_XTAL,
75 .regshift = CPUIMX51_QUART_REGSHIFT, 70 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -77,7 +72,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
77 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 72 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
78 }, { 73 }, {
79 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), 74 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
80 .irq = CPUIMX51_QUARTC_IRQ, 75 .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
81 .irqflags = IRQF_TRIGGER_HIGH, 76 .irqflags = IRQF_TRIGGER_HIGH,
82 .uartclk = CPUIMX51_QUART_XTAL, 77 .uartclk = CPUIMX51_QUART_XTAL,
83 .regshift = CPUIMX51_QUART_REGSHIFT, 78 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -85,7 +80,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
85 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 80 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
86 }, { 81 }, {
87 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), 82 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
88 .irq = CPUIMX51_QUARTD_IRQ, 83 .irq = irq_to_gpio(CPUIMX51_QUARTD_GPIO),
89 .irqflags = IRQF_TRIGGER_HIGH, 84 .irqflags = IRQF_TRIGGER_HIGH,
90 .uartclk = CPUIMX51_QUART_XTAL, 85 .uartclk = CPUIMX51_QUART_XTAL,
91 .regshift = CPUIMX51_QUART_REGSHIFT, 86 .regshift = CPUIMX51_QUART_REGSHIFT,
@@ -171,7 +166,7 @@ static int initialize_otg_port(struct platform_device *pdev)
171 void __iomem *usb_base; 166 void __iomem *usb_base;
172 void __iomem *usbother_base; 167 void __iomem *usbother_base;
173 168
174 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 169 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
175 if (!usb_base) 170 if (!usb_base)
176 return -ENOMEM; 171 return -ENOMEM;
177 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 172 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -194,7 +189,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
194 void __iomem *usb_base; 189 void __iomem *usb_base;
195 void __iomem *usbother_base; 190 void __iomem *usbother_base;
196 191
197 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 192 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
198 if (!usb_base) 193 if (!usb_base)
199 return -ENOMEM; 194 return -ENOMEM;
200 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 195 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -210,17 +205,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
210 MXC_EHCI_ITC_NO_THRESHOLD); 205 MXC_EHCI_ITC_NO_THRESHOLD);
211} 206}
212 207
213static struct mxc_usbh_platform_data dr_utmi_config = { 208static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
214 .init = initialize_otg_port, 209 .init = initialize_otg_port,
215 .portsc = MXC_EHCI_UTMI_16BIT, 210 .portsc = MXC_EHCI_UTMI_16BIT,
216}; 211};
217 212
218static struct fsl_usb2_platform_data usb_pdata = { 213static const struct fsl_usb2_platform_data usb_pdata __initconst = {
219 .operating_mode = FSL_USB2_DR_DEVICE, 214 .operating_mode = FSL_USB2_DR_DEVICE,
220 .phy_mode = FSL_USB2_PHY_UTMI_WIDE, 215 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
221}; 216};
222 217
223static struct mxc_usbh_platform_data usbh1_config = { 218static const struct mxc_usbh_platform_data usbh1_config __initconst = {
224 .init = initialize_usbh1_port, 219 .init = initialize_usbh1_port,
225 .portsc = MXC_EHCI_MODE_ULPI, 220 .portsc = MXC_EHCI_MODE_ULPI,
226}; 221};
@@ -245,6 +240,8 @@ __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
245 */ 240 */
246static void __init eukrea_cpuimx51_init(void) 241static void __init eukrea_cpuimx51_init(void)
247{ 242{
243 imx51_soc_init();
244
248 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, 245 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
249 ARRAY_SIZE(eukrea_cpuimx51_pads)); 246 ARRAY_SIZE(eukrea_cpuimx51_pads));
250 247
@@ -272,12 +269,12 @@ static void __init eukrea_cpuimx51_init(void)
272 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); 269 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
273 270
274 if (otg_mode_host) 271 if (otg_mode_host)
275 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); 272 imx51_add_mxc_ehci_otg(&dr_utmi_config);
276 else { 273 else {
277 initialize_otg_port(NULL); 274 initialize_otg_port(NULL);
278 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); 275 imx51_add_fsl_usb2_udc(&usb_pdata);
279 } 276 }
280 mxc_register_device(&mxc_usbh1_device, &usbh1_config); 277 imx51_add_mxc_ehci_hs(1, &usbh1_config);
281 278
282#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD 279#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
283 eukrea_mbimx51_baseboard_init(); 280 eukrea_mbimx51_baseboard_init();