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-rw-r--r--arch/arm/mach-mx3/Kconfig257
-rw-r--r--arch/arm/mach-mx3/Makefile26
-rw-r--r--arch/arm/mach-mx3/Makefile.boot3
-rw-r--r--arch/arm/mach-mx3/clock-imx31.c630
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c550
-rw-r--r--arch/arm/mach-mx3/cpu.c89
-rw-r--r--arch/arm/mach-mx3/crm_regs.h248
-rw-r--r--arch/arm/mach-mx3/devices-imx31.h68
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h76
-rw-r--r--arch/arm/mach-mx3/devices.c115
-rw-r--r--arch/arm/mach-mx3/devices.h4
-rw-r--r--arch/arm/mach-mx3/ehci-imx31.c83
-rw-r--r--arch/arm/mach-mx3/ehci-imx35.c80
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c318
-rw-r--r--arch/arm/mach-mx3/iomux-imx31.c181
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c578
-rw-r--r--arch/arm/mach-mx3/mach-bug.c66
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c203
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c279
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c771
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c543
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c303
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c288
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c576
-rw-r--r--arch/arm/mach-mx3/mach-mx35_3ds.c225
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c691
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c190
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c428
-rw-r--r--arch/arm/mach-mx3/mach-qong.c270
-rw-r--r--arch/arm/mach-mx3/mach-vpr200.c333
-rw-r--r--arch/arm/mach-mx3/mm.c141
-rw-r--r--arch/arm/mach-mx3/mx31lilly-db.c221
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c204
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c243
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c368
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c210
-rw-r--r--arch/arm/mach-mx3/pcm037.h11
37 files changed, 0 insertions, 9870 deletions
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
deleted file mode 100644
index 340809a7d233..000000000000
--- a/arch/arm/mach-mx3/Kconfig
+++ /dev/null
@@ -1,257 +0,0 @@
1if ARCH_MX3
2
3# ARCH_MX31 and ARCH_MX35 are left for compatibility
4# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
5# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
6# more sensible) names are used: SOC_IMX31 and SOC_IMX35
7config ARCH_MX31
8 bool
9
10config ARCH_MX35
11 bool
12
13config SOC_IMX31
14 bool
15 select IMX_HAVE_PLATFORM_MXC_RNGA
16 select ARCH_MXC_AUDMUX_V2
17 select ARCH_MX31
18 select MXC_AVIC
19
20config SOC_IMX35
21 bool
22 select ARCH_MXC_IOMUX_V3
23 select ARCH_MXC_AUDMUX_V2
24 select HAVE_EPIT
25 select ARCH_MX35
26 select MXC_AVIC
27
28comment "MX3 platforms:"
29
30config MACH_MX31ADS
31 bool "Support MX31ADS platforms"
32 select SOC_IMX31
33 select IMX_HAVE_PLATFORM_IMX_I2C
34 select IMX_HAVE_PLATFORM_IMX_SSI
35 select IMX_HAVE_PLATFORM_IMX_UART
36 default y
37 help
38 Include support for MX31ADS platform. This includes specific
39 configurations for the board and its peripherals.
40
41config MACH_MX31ADS_WM1133_EV1
42 bool "Support Wolfson Microelectronics 1133-EV1 module"
43 depends on MACH_MX31ADS
44 depends on MFD_WM8350_I2C
45 depends on REGULATOR_WM8350
46 select MFD_WM8350_CONFIG_MODE_0
47 select MFD_WM8352_CONFIG_MODE_0
48 help
49 Include support for the Wolfson Microelectronics 1133-EV1 PMU
50 and audio module for the MX31ADS platform.
51
52config MACH_PCM037
53 bool "Support Phytec pcm037 (i.MX31) platforms"
54 select SOC_IMX31
55 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
56 select IMX_HAVE_PLATFORM_IMX2_WDT
57 select IMX_HAVE_PLATFORM_IMX_I2C
58 select IMX_HAVE_PLATFORM_IMX_UART
59 select IMX_HAVE_PLATFORM_MXC_EHCI
60 select IMX_HAVE_PLATFORM_MXC_MMC
61 select IMX_HAVE_PLATFORM_MXC_NAND
62 select IMX_HAVE_PLATFORM_MXC_W1
63 select MXC_ULPI if USB_ULPI
64 help
65 Include support for Phytec pcm037 platform. This includes
66 specific configurations for the board and its peripherals.
67
68config MACH_PCM037_EET
69 bool "Support pcm037 EET board extensions"
70 depends on MACH_PCM037
71 select IMX_HAVE_PLATFORM_SPI_IMX
72 help
73 Add support for PCM037 EET baseboard extensions. If you are using the
74 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
75 command-line parameter.
76
77config MACH_MX31LITE
78 bool "Support MX31 LITEKIT (LogicPD)"
79 select SOC_IMX31
80 select MXC_ULPI if USB_ULPI
81 select IMX_HAVE_PLATFORM_IMX2_WDT
82 select IMX_HAVE_PLATFORM_IMX_UART
83 select IMX_HAVE_PLATFORM_MXC_EHCI
84 select IMX_HAVE_PLATFORM_MXC_MMC
85 select IMX_HAVE_PLATFORM_MXC_NAND
86 select IMX_HAVE_PLATFORM_SPI_IMX
87 help
88 Include support for MX31 LITEKIT platform. This includes specific
89 configurations for the board and its peripherals.
90
91config MACH_MX31_3DS
92 bool "Support MX31PDK (3DS)"
93 select SOC_IMX31
94 select MXC_DEBUG_BOARD
95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
96 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_I2C
98 select IMX_HAVE_PLATFORM_IMX_KEYPAD
99 select IMX_HAVE_PLATFORM_IMX_UART
100 select IMX_HAVE_PLATFORM_MXC_EHCI
101 select IMX_HAVE_PLATFORM_MXC_NAND
102 select IMX_HAVE_PLATFORM_SPI_IMX
103 select MXC_ULPI if USB_ULPI
104 help
105 Include support for MX31PDK (3DS) platform. This includes specific
106 configurations for the board and its peripherals.
107
108config MACH_MX31_3DS_MXC_NAND_USE_BBT
109 bool "Make the MXC NAND driver use the in flash Bad Block Table"
110 depends on MACH_MX31_3DS
111 depends on MTD_NAND_MXC
112 help
113 Enable this if you want that the MXC NAND driver uses the in flash
114 Bad Block Table to know what blocks are bad instead of scanning the
115 entire flash looking for bad block markers.
116
117config MACH_MX31MOBOARD
118 bool "Support mx31moboard platforms (EPFL Mobots group)"
119 select SOC_IMX31
120 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
121 select IMX_HAVE_PLATFORM_IMX_I2C
122 select IMX_HAVE_PLATFORM_IMX_UART
123 select IMX_HAVE_PLATFORM_MXC_EHCI
124 select IMX_HAVE_PLATFORM_MXC_MMC
125 select IMX_HAVE_PLATFORM_SPI_IMX
126 select MXC_ULPI if USB_ULPI
127 help
128 Include support for mx31moboard platform. This includes specific
129 configurations for the board and its peripherals.
130
131config MACH_MX31LILLY
132 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
133 select SOC_IMX31
134 select IMX_HAVE_PLATFORM_IMX_UART
135 select IMX_HAVE_PLATFORM_MXC_EHCI
136 select IMX_HAVE_PLATFORM_MXC_MMC
137 select IMX_HAVE_PLATFORM_SPI_IMX
138 select MXC_ULPI if USB_ULPI
139 help
140 Include support for mx31 based LILLY1131 modules. This includes
141 specific configurations for the board and its peripherals.
142
143config MACH_QONG
144 bool "Support Dave/DENX QongEVB-LITE platform"
145 select SOC_IMX31
146 select IMX_HAVE_PLATFORM_IMX_UART
147 help
148 Include support for Dave/DENX QongEVB-LITE platform. This includes
149 specific configurations for the board and its peripherals.
150
151config MACH_PCM043
152 bool "Support Phytec pcm043 (i.MX35) platforms"
153 select SOC_IMX35
154 select IMX_HAVE_PLATFORM_FLEXCAN
155 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
156 select IMX_HAVE_PLATFORM_IMX2_WDT
157 select IMX_HAVE_PLATFORM_IMX_I2C
158 select IMX_HAVE_PLATFORM_IMX_SSI
159 select IMX_HAVE_PLATFORM_IMX_UART
160 select IMX_HAVE_PLATFORM_MXC_EHCI
161 select IMX_HAVE_PLATFORM_MXC_NAND
162 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
163 select MXC_ULPI if USB_ULPI
164 help
165 Include support for Phytec pcm043 platform. This includes
166 specific configurations for the board and its peripherals.
167
168config MACH_ARMADILLO5X0
169 bool "Support Atmark Armadillo-500 Development Base Board"
170 select SOC_IMX31
171 select IMX_HAVE_PLATFORM_IMX_I2C
172 select IMX_HAVE_PLATFORM_IMX_UART
173 select IMX_HAVE_PLATFORM_MXC_EHCI
174 select IMX_HAVE_PLATFORM_MXC_MMC
175 select IMX_HAVE_PLATFORM_MXC_NAND
176 select MXC_ULPI if USB_ULPI
177 help
178 Include support for Atmark Armadillo-500 platform. This includes
179 specific configurations for the board and its peripherals.
180
181config MACH_MX35_3DS
182 bool "Support MX35PDK platform"
183 select SOC_IMX35
184 select MXC_DEBUG_BOARD
185 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
186 select IMX_HAVE_PLATFORM_IMX2_WDT
187 select IMX_HAVE_PLATFORM_IMX_I2C
188 select IMX_HAVE_PLATFORM_IMX_UART
189 select IMX_HAVE_PLATFORM_MXC_EHCI
190 select IMX_HAVE_PLATFORM_MXC_NAND
191 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
192 help
193 Include support for MX35PDK platform. This includes specific
194 configurations for the board and its peripherals.
195
196config MACH_KZM_ARM11_01
197 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
198 select SOC_IMX31
199 select IMX_HAVE_PLATFORM_IMX_UART
200 help
201 Include support for KZM-ARM11-01. This includes specific
202 configurations for the board and its peripherals.
203
204config MACH_BUG
205 bool "Support Buglabs BUGBase platform"
206 select SOC_IMX31
207 select IMX_HAVE_PLATFORM_IMX_UART
208 default y
209 help
210 Include support for BUGBase 1.3 platform. This includes specific
211 configurations for the board and its peripherals.
212
213config MACH_EUKREA_CPUIMX35
214 bool "Support Eukrea CPUIMX35 Platform"
215 select SOC_IMX35
216 select IMX_HAVE_PLATFORM_FLEXCAN
217 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
218 select IMX_HAVE_PLATFORM_IMX2_WDT
219 select IMX_HAVE_PLATFORM_IMX_I2C
220 select IMX_HAVE_PLATFORM_IMX_UART
221 select IMX_HAVE_PLATFORM_MXC_EHCI
222 select IMX_HAVE_PLATFORM_MXC_NAND
223 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
224 select MXC_ULPI if USB_ULPI
225 help
226 Include support for Eukrea CPUIMX35 platform. This includes
227 specific configurations for the board and its peripherals.
228
229choice
230 prompt "Baseboard"
231 depends on MACH_EUKREA_CPUIMX35
232 default MACH_EUKREA_MBIMXSD35_BASEBOARD
233
234config MACH_EUKREA_MBIMXSD35_BASEBOARD
235 bool "Eukrea MBIMXSD development board"
236 select IMX_HAVE_PLATFORM_IMX_SSI
237 help
238 This adds board specific devices that can be found on Eukrea's
239 MBIMXSD evaluation board.
240
241endchoice
242
243config MACH_VPR200
244 bool "Support VPR200 platform"
245 select SOC_IMX35
246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
247 select IMX_HAVE_PLATFORM_IMX2_WDT
248 select IMX_HAVE_PLATFORM_IMX_UART
249 select IMX_HAVE_PLATFORM_IMX_I2C
250 select IMX_HAVE_PLATFORM_MXC_EHCI
251 select IMX_HAVE_PLATFORM_MXC_NAND
252 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
253 help
254 Include support for VPR200 platform. This includes specific
255 configurations for the board and its peripherals.
256
257endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
deleted file mode 100644
index a54faf2cf5fa..000000000000
--- a/arch/arm/mach-mx3/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
13obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
14obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
15obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
16obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
17 mx31moboard-marxbot.o mx31moboard-smartbot.o
18obj-$(CONFIG_MACH_QONG) += mach-qong.o
19obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
23obj-$(CONFIG_MACH_BUG) += mach-bug.o
24obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
25obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
26obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
deleted file mode 100644
index e1dd366f836b..000000000000
--- a/arch/arm/mach-mx3/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
deleted file mode 100644
index d423cac8cab7..000000000000
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ /dev/null
@@ -1,630 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/clkdev.h>
27
28#include <asm/div64.h>
29
30#include <mach/clock.h>
31#include <mach/hardware.h>
32#include <mach/mx31.h>
33#include <mach/common.h>
34
35#include "crm_regs.h"
36
37#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
38
39static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
40{
41 u32 min_pre, temp_pre, old_err, err;
42
43 if (div >= 512) {
44 *pre = 8;
45 *post = 64;
46 } else if (div >= 64) {
47 min_pre = (div - 1) / 64 + 1;
48 old_err = 8;
49 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
50 err = div % temp_pre;
51 if (err == 0) {
52 *pre = temp_pre;
53 break;
54 }
55 err = temp_pre - err;
56 if (err < old_err) {
57 old_err = err;
58 *pre = temp_pre;
59 }
60 }
61 *post = (div + *pre - 1) / *pre;
62 } else if (div <= 8) {
63 *pre = div;
64 *post = 1;
65 } else {
66 *pre = 1;
67 *post = div;
68 }
69}
70
71static struct clk mcu_pll_clk;
72static struct clk serial_pll_clk;
73static struct clk ipg_clk;
74static struct clk ckih_clk;
75
76static int cgr_enable(struct clk *clk)
77{
78 u32 reg;
79
80 if (!clk->enable_reg)
81 return 0;
82
83 reg = __raw_readl(clk->enable_reg);
84 reg |= 3 << clk->enable_shift;
85 __raw_writel(reg, clk->enable_reg);
86
87 return 0;
88}
89
90static void cgr_disable(struct clk *clk)
91{
92 u32 reg;
93
94 if (!clk->enable_reg)
95 return;
96
97 reg = __raw_readl(clk->enable_reg);
98 reg &= ~(3 << clk->enable_shift);
99
100 /* special case for EMI clock */
101 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
102 reg |= (1 << clk->enable_shift);
103
104 __raw_writel(reg, clk->enable_reg);
105}
106
107static unsigned long pll_ref_get_rate(void)
108{
109 unsigned long ccmr;
110 unsigned int prcs;
111
112 ccmr = __raw_readl(MXC_CCM_CCMR);
113 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
114 if (prcs == 0x1)
115 return CKIL_CLK_FREQ * 1024;
116 else
117 return clk_get_rate(&ckih_clk);
118}
119
120static unsigned long usb_pll_get_rate(struct clk *clk)
121{
122 unsigned long reg;
123
124 reg = __raw_readl(MXC_CCM_UPCTL);
125
126 return mxc_decode_pll(reg, pll_ref_get_rate());
127}
128
129static unsigned long serial_pll_get_rate(struct clk *clk)
130{
131 unsigned long reg;
132
133 reg = __raw_readl(MXC_CCM_SRPCTL);
134
135 return mxc_decode_pll(reg, pll_ref_get_rate());
136}
137
138static unsigned long mcu_pll_get_rate(struct clk *clk)
139{
140 unsigned long reg, ccmr;
141
142 ccmr = __raw_readl(MXC_CCM_CCMR);
143
144 if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
145 return clk_get_rate(&ckih_clk);
146
147 reg = __raw_readl(MXC_CCM_MPCTL);
148
149 return mxc_decode_pll(reg, pll_ref_get_rate());
150}
151
152static int usb_pll_enable(struct clk *clk)
153{
154 u32 reg;
155
156 reg = __raw_readl(MXC_CCM_CCMR);
157 reg |= MXC_CCM_CCMR_UPE;
158 __raw_writel(reg, MXC_CCM_CCMR);
159
160 /* No lock bit on MX31, so using max time from spec */
161 udelay(80);
162
163 return 0;
164}
165
166static void usb_pll_disable(struct clk *clk)
167{
168 u32 reg;
169
170 reg = __raw_readl(MXC_CCM_CCMR);
171 reg &= ~MXC_CCM_CCMR_UPE;
172 __raw_writel(reg, MXC_CCM_CCMR);
173}
174
175static int serial_pll_enable(struct clk *clk)
176{
177 u32 reg;
178
179 reg = __raw_readl(MXC_CCM_CCMR);
180 reg |= MXC_CCM_CCMR_SPE;
181 __raw_writel(reg, MXC_CCM_CCMR);
182
183 /* No lock bit on MX31, so using max time from spec */
184 udelay(80);
185
186 return 0;
187}
188
189static void serial_pll_disable(struct clk *clk)
190{
191 u32 reg;
192
193 reg = __raw_readl(MXC_CCM_CCMR);
194 reg &= ~MXC_CCM_CCMR_SPE;
195 __raw_writel(reg, MXC_CCM_CCMR);
196}
197
198#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
199#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
200#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
201
202static unsigned long mcu_main_get_rate(struct clk *clk)
203{
204 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
205
206 if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
207 return clk_get_rate(&serial_pll_clk);
208 else
209 return clk_get_rate(&mcu_pll_clk);
210}
211
212static unsigned long ahb_get_rate(struct clk *clk)
213{
214 unsigned long max_pdf;
215
216 max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
217 MXC_CCM_PDR0_MAX_PODF_OFFSET);
218 return clk_get_rate(clk->parent) / (max_pdf + 1);
219}
220
221static unsigned long ipg_get_rate(struct clk *clk)
222{
223 unsigned long ipg_pdf;
224
225 ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
226 MXC_CCM_PDR0_IPG_PODF_OFFSET);
227 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
228}
229
230static unsigned long nfc_get_rate(struct clk *clk)
231{
232 unsigned long nfc_pdf;
233
234 nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
235 MXC_CCM_PDR0_NFC_PODF_OFFSET);
236 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
237}
238
239static unsigned long hsp_get_rate(struct clk *clk)
240{
241 unsigned long hsp_pdf;
242
243 hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
244 MXC_CCM_PDR0_HSP_PODF_OFFSET);
245 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
246}
247
248static unsigned long usb_get_rate(struct clk *clk)
249{
250 unsigned long usb_pdf, usb_prepdf;
251
252 usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
253 MXC_CCM_PDR1_USB_PODF_OFFSET);
254 usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
255 MXC_CCM_PDR1_USB_PRDF_OFFSET);
256 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
257}
258
259static unsigned long csi_get_rate(struct clk *clk)
260{
261 u32 reg, pre, post;
262
263 reg = __raw_readl(MXC_CCM_PDR0);
264 pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
265 MXC_CCM_PDR0_CSI_PRDF_OFFSET;
266 pre++;
267 post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
268 MXC_CCM_PDR0_CSI_PODF_OFFSET;
269 post++;
270 return clk_get_rate(clk->parent) / (pre * post);
271}
272
273static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
274{
275 u32 pre, post, parent = clk_get_rate(clk->parent);
276 u32 div = parent / rate;
277
278 if (parent % rate)
279 div++;
280
281 __calc_pre_post_dividers(div, &pre, &post);
282
283 return parent / (pre * post);
284}
285
286static int csi_set_rate(struct clk *clk, unsigned long rate)
287{
288 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
289
290 div = parent / rate;
291
292 if ((parent / div) != rate)
293 return -EINVAL;
294
295 __calc_pre_post_dividers(div, &pre, &post);
296
297 /* Set CSI clock divider */
298 reg = __raw_readl(MXC_CCM_PDR0) &
299 ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
300 reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
301 reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
302 __raw_writel(reg, MXC_CCM_PDR0);
303
304 return 0;
305}
306
307static unsigned long ssi1_get_rate(struct clk *clk)
308{
309 unsigned long ssi1_pdf, ssi1_prepdf;
310
311 ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
312 MXC_CCM_PDR1_SSI1_PODF_OFFSET);
313 ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
314 MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
315 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
316}
317
318static unsigned long ssi2_get_rate(struct clk *clk)
319{
320 unsigned long ssi2_pdf, ssi2_prepdf;
321
322 ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
323 MXC_CCM_PDR1_SSI2_PODF_OFFSET);
324 ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
325 MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
326 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
327}
328
329static unsigned long firi_get_rate(struct clk *clk)
330{
331 unsigned long firi_pdf, firi_prepdf;
332
333 firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
334 MXC_CCM_PDR1_FIRI_PODF_OFFSET);
335 firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
336 MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
337 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
338}
339
340static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
341{
342 u32 pre, post;
343 u32 parent = clk_get_rate(clk->parent);
344 u32 div = parent / rate;
345
346 if (parent % rate)
347 div++;
348
349 __calc_pre_post_dividers(div, &pre, &post);
350
351 return parent / (pre * post);
352
353}
354
355static int firi_set_rate(struct clk *clk, unsigned long rate)
356{
357 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
358
359 div = parent / rate;
360
361 if ((parent / div) != rate)
362 return -EINVAL;
363
364 __calc_pre_post_dividers(div, &pre, &post);
365
366 /* Set FIRI clock divider */
367 reg = __raw_readl(MXC_CCM_PDR1) &
368 ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
369 reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
370 reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
371 __raw_writel(reg, MXC_CCM_PDR1);
372
373 return 0;
374}
375
376static unsigned long mbx_get_rate(struct clk *clk)
377{
378 return clk_get_rate(clk->parent) / 2;
379}
380
381static unsigned long mstick1_get_rate(struct clk *clk)
382{
383 unsigned long msti_pdf;
384
385 msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
386 MXC_CCM_PDR2_MST1_PDF_OFFSET);
387 return clk_get_rate(clk->parent) / (msti_pdf + 1);
388}
389
390static unsigned long mstick2_get_rate(struct clk *clk)
391{
392 unsigned long msti_pdf;
393
394 msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
395 MXC_CCM_PDR2_MST2_PDF_OFFSET);
396 return clk_get_rate(clk->parent) / (msti_pdf + 1);
397}
398
399static unsigned long ckih_rate;
400
401static unsigned long clk_ckih_get_rate(struct clk *clk)
402{
403 return ckih_rate;
404}
405
406static unsigned long clk_ckil_get_rate(struct clk *clk)
407{
408 return CKIL_CLK_FREQ;
409}
410
411static struct clk ckih_clk = {
412 .get_rate = clk_ckih_get_rate,
413};
414
415static struct clk mcu_pll_clk = {
416 .parent = &ckih_clk,
417 .get_rate = mcu_pll_get_rate,
418};
419
420static struct clk mcu_main_clk = {
421 .parent = &mcu_pll_clk,
422 .get_rate = mcu_main_get_rate,
423};
424
425static struct clk serial_pll_clk = {
426 .parent = &ckih_clk,
427 .get_rate = serial_pll_get_rate,
428 .enable = serial_pll_enable,
429 .disable = serial_pll_disable,
430};
431
432static struct clk usb_pll_clk = {
433 .parent = &ckih_clk,
434 .get_rate = usb_pll_get_rate,
435 .enable = usb_pll_enable,
436 .disable = usb_pll_disable,
437};
438
439static struct clk ahb_clk = {
440 .parent = &mcu_main_clk,
441 .get_rate = ahb_get_rate,
442};
443
444#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
445 static struct clk name = { \
446 .id = i, \
447 .enable_reg = er, \
448 .enable_shift = es, \
449 .get_rate = gr, \
450 .enable = cgr_enable, \
451 .disable = cgr_disable, \
452 .secondary = s, \
453 .parent = p, \
454 }
455
456#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
457 static struct clk name = { \
458 .id = i, \
459 .enable_reg = er, \
460 .enable_shift = es, \
461 .get_rate = getsetround##_get_rate, \
462 .set_rate = getsetround##_set_rate, \
463 .round_rate = getsetround##_round_rate, \
464 .enable = cgr_enable, \
465 .disable = cgr_disable, \
466 .secondary = s, \
467 .parent = p, \
468 }
469
470DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
471DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
472
473DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
474DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
475DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
476DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
477DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
478DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
479DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
480DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
481DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
482DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
483DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
484DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
485DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
486DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
487DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
488DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
489
490DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
491DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
492DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
493DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
494DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
495DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
496DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
497DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
498DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
499DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
500DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
501DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
502DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
503DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
504
505DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
506DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
507DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
508DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
509DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
510DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
511DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
512
513DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
514DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
515DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
516DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
517DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
518
519#define _REGISTER_CLOCK(d, n, c) \
520 { \
521 .dev_id = d, \
522 .con_id = n, \
523 .clk = &c, \
524 },
525
526static struct clk_lookup lookups[] = {
527 _REGISTER_CLOCK(NULL, "emi", emi_clk)
528 _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
529 _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
530 _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
532 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
533 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
534 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
535 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
536 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
537 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
538 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
539 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
540 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
541 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
542 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
543 _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
544 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
545 _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
546 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
547 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
548 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
549 _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
550 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
551 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
552 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
553 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
554 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
555 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
556 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
557 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
558 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
559 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
560 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
561 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
562 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
563 _REGISTER_CLOCK(NULL, "firi", firi_clk)
564 _REGISTER_CLOCK(NULL, "ata", ata_clk)
565 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
566 _REGISTER_CLOCK(NULL, "rng", rng_clk)
567 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
568 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
569 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
570 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
571 _REGISTER_CLOCK(NULL, "scc", scc_clk)
572 _REGISTER_CLOCK(NULL, "iim", iim_clk)
573 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
574 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
575};
576
577int __init mx31_clocks_init(unsigned long fref)
578{
579 u32 reg;
580
581 ckih_rate = fref;
582
583 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
584
585 /* change the csi_clk parent if necessary */
586 reg = __raw_readl(MXC_CCM_CCMR);
587 if (!(reg & MXC_CCM_CCMR_CSCS))
588 if (clk_set_parent(&csi_clk, &usb_pll_clk))
589 pr_err("%s: error changing csi_clk parent\n", __func__);
590
591
592 /* Turn off all possible clocks */
593 __raw_writel((3 << 4), MXC_CCM_CGR0);
594 __raw_writel(0, MXC_CCM_CGR1);
595 __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
596 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
597 MX32, but still required to be set */
598 MXC_CCM_CGR2);
599
600 /*
601 * Before turning off usb_pll make sure ipg_per_clk is generated
602 * by ipg_clk and not usb_pll.
603 */
604 __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
605
606 usb_pll_disable(&usb_pll_clk);
607
608 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
609
610 clk_enable(&gpt_clk);
611 clk_enable(&emi_clk);
612 clk_enable(&iim_clk);
613
614 clk_enable(&serial_pll_clk);
615
616 mx31_read_cpu_rev();
617
618 if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
619 reg = __raw_readl(MXC_CCM_PMCR1);
620 /* No PLL restart on DVFS switch; enable auto EMI handshake */
621 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
622 __raw_writel(reg, MXC_CCM_PMCR1);
623 }
624
625 mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
626 MX31_INT_GPT);
627
628 return 0;
629}
630
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
deleted file mode 100644
index 448a038cd1ec..000000000000
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ /dev/null
@@ -1,550 +0,0 @@
1/*
2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/clkdev.h>
25
26#include <mach/clock.h>
27#include <mach/hardware.h>
28#include <mach/common.h>
29
30#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
31
32#define CCM_CCMR 0x00
33#define CCM_PDR0 0x04
34#define CCM_PDR1 0x08
35#define CCM_PDR2 0x0C
36#define CCM_PDR3 0x10
37#define CCM_PDR4 0x14
38#define CCM_RCSR 0x18
39#define CCM_MPCTL 0x1C
40#define CCM_PPCTL 0x20
41#define CCM_ACMR 0x24
42#define CCM_COSR 0x28
43#define CCM_CGR0 0x2C
44#define CCM_CGR1 0x30
45#define CCM_CGR2 0x34
46#define CCM_CGR3 0x38
47
48#ifdef HAVE_SET_RATE_SUPPORT
49static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
50{
51 u32 min_pre, temp_pre, old_err, err;
52
53 min_pre = (div - 1) / maxpost + 1;
54 old_err = 8;
55
56 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
57 if (div > (temp_pre * maxpost))
58 break;
59
60 if (div < (temp_pre * temp_pre))
61 continue;
62
63 err = div % temp_pre;
64
65 if (err == 0) {
66 *pre = temp_pre;
67 break;
68 }
69
70 err = temp_pre - err;
71
72 if (err < old_err) {
73 old_err = err;
74 *pre = temp_pre;
75 }
76 }
77
78 *post = (div + *pre - 1) / *pre;
79}
80
81/* get the best values for a 3-bit divider combined with a 6-bit divider */
82static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
83{
84 if (div >= 512) {
85 *pre = 8;
86 *post = 64;
87 } else if (div >= 64) {
88 calc_dividers(div, pre, post, 64);
89 } else if (div <= 8) {
90 *pre = div;
91 *post = 1;
92 } else {
93 *pre = 1;
94 *post = div;
95 }
96}
97
98/* get the best values for two cascaded 3-bit dividers */
99static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
100{
101 if (div >= 64) {
102 *pre = *post = 8;
103 } else if (div > 8) {
104 calc_dividers(div, pre, post, 8);
105 } else {
106 *pre = 1;
107 *post = div;
108 }
109}
110#endif
111
112static unsigned long get_rate_mpll(void)
113{
114 ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
115
116 return mxc_decode_pll(mpctl, 24000000);
117}
118
119static unsigned long get_rate_ppll(void)
120{
121 ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
122
123 return mxc_decode_pll(ppctl, 24000000);
124}
125
126struct arm_ahb_div {
127 unsigned char arm, ahb, sel;
128};
129
130static struct arm_ahb_div clk_consumer[] = {
131 { .arm = 1, .ahb = 4, .sel = 0},
132 { .arm = 1, .ahb = 3, .sel = 1},
133 { .arm = 2, .ahb = 2, .sel = 0},
134 { .arm = 0, .ahb = 0, .sel = 0},
135 { .arm = 0, .ahb = 0, .sel = 0},
136 { .arm = 0, .ahb = 0, .sel = 0},
137 { .arm = 4, .ahb = 1, .sel = 0},
138 { .arm = 1, .ahb = 5, .sel = 0},
139 { .arm = 1, .ahb = 8, .sel = 0},
140 { .arm = 1, .ahb = 6, .sel = 1},
141 { .arm = 2, .ahb = 4, .sel = 0},
142 { .arm = 0, .ahb = 0, .sel = 0},
143 { .arm = 0, .ahb = 0, .sel = 0},
144 { .arm = 0, .ahb = 0, .sel = 0},
145 { .arm = 4, .ahb = 2, .sel = 0},
146 { .arm = 0, .ahb = 0, .sel = 0},
147};
148
149static unsigned long get_rate_arm(void)
150{
151 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
152 struct arm_ahb_div *aad;
153 unsigned long fref = get_rate_mpll();
154
155 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
156 if (aad->sel)
157 fref = fref * 3 / 4;
158
159 return fref / aad->arm;
160}
161
162static unsigned long get_rate_ahb(struct clk *clk)
163{
164 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
165 struct arm_ahb_div *aad;
166 unsigned long fref = get_rate_arm();
167
168 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
169
170 return fref / aad->ahb;
171}
172
173static unsigned long get_rate_ipg(struct clk *clk)
174{
175 return get_rate_ahb(NULL) >> 1;
176}
177
178static unsigned long get_rate_uart(struct clk *clk)
179{
180 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
181 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
182 unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
183
184 if (pdr3 & (1 << 14))
185 return get_rate_arm() / div;
186 else
187 return get_rate_ppll() / div;
188}
189
190static unsigned long get_rate_sdhc(struct clk *clk)
191{
192 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
193 unsigned long div, rate;
194
195 if (pdr3 & (1 << 6))
196 rate = get_rate_arm();
197 else
198 rate = get_rate_ppll();
199
200 switch (clk->id) {
201 default:
202 case 0:
203 div = pdr3 & 0x3f;
204 break;
205 case 1:
206 div = (pdr3 >> 8) & 0x3f;
207 break;
208 case 2:
209 div = (pdr3 >> 16) & 0x3f;
210 break;
211 }
212
213 return rate / (div + 1);
214}
215
216static unsigned long get_rate_mshc(struct clk *clk)
217{
218 unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
219 unsigned long div1, div2, rate;
220
221 if (pdr1 & (1 << 7))
222 rate = get_rate_arm();
223 else
224 rate = get_rate_ppll();
225
226 div1 = (pdr1 >> 29) & 0x7;
227 div2 = (pdr1 >> 22) & 0x3f;
228
229 return rate / ((div1 + 1) * (div2 + 1));
230}
231
232static unsigned long get_rate_ssi(struct clk *clk)
233{
234 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
235 unsigned long div1, div2, rate;
236
237 if (pdr2 & (1 << 6))
238 rate = get_rate_arm();
239 else
240 rate = get_rate_ppll();
241
242 switch (clk->id) {
243 default:
244 case 0:
245 div1 = pdr2 & 0x3f;
246 div2 = (pdr2 >> 24) & 0x7;
247 break;
248 case 1:
249 div1 = (pdr2 >> 8) & 0x3f;
250 div2 = (pdr2 >> 27) & 0x7;
251 break;
252 }
253
254 return rate / ((div1 + 1) * (div2 + 1));
255}
256
257static unsigned long get_rate_csi(struct clk *clk)
258{
259 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
260 unsigned long rate;
261
262 if (pdr2 & (1 << 7))
263 rate = get_rate_arm();
264 else
265 rate = get_rate_ppll();
266
267 return rate / (((pdr2 >> 16) & 0x3f) + 1);
268}
269
270static unsigned long get_rate_otg(struct clk *clk)
271{
272 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
273 unsigned long rate;
274
275 if (pdr4 & (1 << 9))
276 rate = get_rate_arm();
277 else
278 rate = get_rate_ppll();
279
280 return rate / (((pdr4 >> 22) & 0x3f) + 1);
281}
282
283static unsigned long get_rate_ipg_per(struct clk *clk)
284{
285 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
286 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
287 unsigned long div;
288
289 if (pdr0 & (1 << 26)) {
290 div = (pdr4 >> 16) & 0x3f;
291 return get_rate_arm() / (div + 1);
292 } else {
293 div = (pdr0 >> 12) & 0x7;
294 return get_rate_ahb(NULL) / (div + 1);
295 }
296}
297
298static unsigned long get_rate_hsp(struct clk *clk)
299{
300 unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
301 unsigned long fref = get_rate_mpll();
302
303 if (fref > 400 * 1000 * 1000) {
304 switch (hsp_podf) {
305 case 0:
306 return fref >> 2;
307 case 1:
308 return fref >> 3;
309 case 2:
310 return fref / 3;
311 }
312 } else {
313 switch (hsp_podf) {
314 case 0:
315 case 2:
316 return fref / 3;
317 case 1:
318 return fref / 6;
319 }
320 }
321
322 return 0;
323}
324
325static int clk_cgr_enable(struct clk *clk)
326{
327 u32 reg;
328
329 reg = __raw_readl(clk->enable_reg);
330 reg |= 3 << clk->enable_shift;
331 __raw_writel(reg, clk->enable_reg);
332
333 return 0;
334}
335
336static void clk_cgr_disable(struct clk *clk)
337{
338 u32 reg;
339
340 reg = __raw_readl(clk->enable_reg);
341 reg &= ~(3 << clk->enable_shift);
342 __raw_writel(reg, clk->enable_reg);
343}
344
345#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
346 static struct clk name = { \
347 .id = i, \
348 .enable_reg = CCM_BASE + er, \
349 .enable_shift = es, \
350 .get_rate = gr, \
351 .set_rate = sr, \
352 .enable = clk_cgr_enable, \
353 .disable = clk_cgr_disable, \
354 }
355
356DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
357DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
358/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
359DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
360DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
361DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
362DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
363DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
364DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
365DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
366DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL);
367DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL);
368DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
369DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
370DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
371DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
372
373DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL);
374DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL);
375DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL);
376DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL);
377DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL);
378DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
379DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
380DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
381DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
382DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_hsp, NULL);
383DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
384DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
385DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
386DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
387DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
388DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL);
389
390DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
391DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
392DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
393DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
394DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
395DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
396DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
397DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
398DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
399DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
400DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
401DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
402DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
403DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
404DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
405
406DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
407DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
408DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
409
410DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
411
412static int clk_dummy_enable(struct clk *clk)
413{
414 return 0;
415}
416
417static void clk_dummy_disable(struct clk *clk)
418{
419}
420
421static unsigned long get_rate_nfc(struct clk *clk)
422{
423 unsigned long div1;
424
425 div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
426
427 return get_rate_ahb(NULL) / div1;
428}
429
430/* NAND Controller: It seems it can't be disabled */
431static struct clk nfc_clk = {
432 .id = 0,
433 .enable_reg = 0,
434 .enable_shift = 0,
435 .get_rate = get_rate_nfc,
436 .set_rate = NULL, /* set_rate_nfc, */
437 .enable = clk_dummy_enable,
438 .disable = clk_dummy_disable
439};
440
441#define _REGISTER_CLOCK(d, n, c) \
442 { \
443 .dev_id = d, \
444 .con_id = n, \
445 .clk = &c, \
446 },
447
448static struct clk_lookup lookups[] = {
449 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
450 _REGISTER_CLOCK(NULL, "ata", ata_clk)
451 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
452 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
453 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
454 _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
455 _REGISTER_CLOCK(NULL, "ect", ect_clk)
456 _REGISTER_CLOCK(NULL, "edio", edio_clk)
457 _REGISTER_CLOCK(NULL, "emi", emi_clk)
458 _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
459 _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
460 _REGISTER_CLOCK(NULL, "esai", esai_clk)
461 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
462 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
463 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
464 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
465 _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
466 _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
467 _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
468 _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
469 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
470 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
471 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
472 _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
473 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
474 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
475 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
476 _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
477 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
478 _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
479 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
480 _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
481 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
482 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
483 _REGISTER_CLOCK(NULL, "scc", scc_clk)
484 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
485 _REGISTER_CLOCK(NULL, "spba", spba_clk)
486 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
487 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
488 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
489 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
490 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
491 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
492 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
493 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
494 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
495 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
496 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
497 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
498 _REGISTER_CLOCK(NULL, "max", max_clk)
499 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
500 _REGISTER_CLOCK(NULL, "csi", csi_clk)
501 _REGISTER_CLOCK(NULL, "iim", iim_clk)
502 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
503 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
504};
505
506int __init mx35_clocks_init()
507{
508 unsigned int cgr2 = 3 << 26, cgr3 = 0;
509
510#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
511 cgr2 |= 3 << 16;
512#endif
513
514 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
515
516 /* Turn off all clocks except the ones we need to survive, namely:
517 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
518 */
519 __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
520 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
521 CCM_BASE + CCM_CGR1);
522
523 /*
524 * Check if we came up in internal boot mode. If yes, we need some
525 * extra clocks turned on, otherwise the MX35 boot ROM code will
526 * hang after a watchdog reset.
527 */
528 if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
529 /* Additionally turn on UART1, SCC, and IIM clocks */
530 cgr2 |= 3 << 16 | 3 << 4;
531 cgr3 |= 3 << 2;
532 }
533
534 __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
535 __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
536
537 clk_enable(&iim_clk);
538 mx35_read_cpu_rev();
539
540#ifdef CONFIG_MXC_USE_EPIT
541 epit_timer_init(&epit1_clk,
542 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
543#else
544 mxc_timer_init(&gpt_clk,
545 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
546#endif
547
548 return 0;
549}
550
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
deleted file mode 100644
index d1d339576fdf..000000000000
--- a/arch/arm/mach-mx3/cpu.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * MX3 CPU type detection
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/io.h>
14#include <mach/hardware.h>
15#include <mach/iim.h>
16
17unsigned int mx31_cpu_rev;
18EXPORT_SYMBOL(mx31_cpu_rev);
19
20struct mx3_cpu_type {
21 u8 srev;
22 const char *name;
23 const char *v;
24 unsigned int rev;
25};
26
27static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
37};
38
39void __init mx31_read_cpu_rev(void)
40{
41 u32 i, srev;
42
43 /* read SREV register from IIM module */
44 srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
45
46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
47 if (srev == mx31_cpu_type[i].srev) {
48 printk(KERN_INFO
49 "CPU identified as %s, silicon rev %s\n",
50 mx31_cpu_type[i].name, mx31_cpu_type[i].v);
51
52 mx31_cpu_rev = mx31_cpu_type[i].rev;
53 return;
54 }
55
56 mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
57
58 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
59}
60
61unsigned int mx35_cpu_rev;
62EXPORT_SYMBOL(mx35_cpu_rev);
63
64void __init mx35_read_cpu_rev(void)
65{
66 u32 rev;
67 char *srev;
68
69 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
70 switch (rev) {
71 case 0x00:
72 mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
73 srev = "1.0";
74 break;
75 case 0x10:
76 mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
77 srev = "2.0";
78 break;
79 case 0x11:
80 mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
81 srev = "2.1";
82 break;
83 default:
84 mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
85 srev = "unknown";
86 }
87
88 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
89}
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
deleted file mode 100644
index 37a8a07beda3..000000000000
--- a/arch/arm/mach-mx3/crm_regs.h
+++ /dev/null
@@ -1,248 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
21#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
22
23#define CKIH_CLK_FREQ 26000000
24#define CKIH_CLK_FREQ_27MHZ 27000000
25#define CKIL_CLK_FREQ 32768
26
27#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
28
29/* Register addresses */
30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
31#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
32#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
33#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C)
34#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10)
35#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14)
36#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18)
37#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C)
38#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20)
39#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24)
40#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28)
41#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C)
42#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30)
43#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34)
44#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38)
45#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C)
46#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40)
47#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44)
48#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48)
49#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C)
50#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50)
51#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54)
52#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58)
53#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C)
54#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60)
55#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64)
56
57/* Register bit definitions */
58#define MXC_CCM_CCMR_WBEN (1 << 27)
59#define MXC_CCM_CCMR_CSCS (1 << 25)
60#define MXC_CCM_CCMR_PERCS (1 << 24)
61#define MXC_CCM_CCMR_SSI1S_OFFSET 18
62#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18)
63#define MXC_CCM_CCMR_SSI2S_OFFSET 21
64#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
65#define MXC_CCM_CCMR_LPM_OFFSET 14
66#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
67#define MXC_CCM_CCMR_FIRS_OFFSET 11
68#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
69#define MXC_CCM_CCMR_UPE (1 << 9)
70#define MXC_CCM_CCMR_SPE (1 << 8)
71#define MXC_CCM_CCMR_MDS (1 << 7)
72#define MXC_CCM_CCMR_SBYCS (1 << 4)
73#define MXC_CCM_CCMR_MPE (1 << 3)
74#define MXC_CCM_CCMR_PRCS_OFFSET 1
75#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
76
77#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26
78#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26)
79#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23
80#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23)
81#define MXC_CCM_PDR0_PER_PODF_OFFSET 16
82#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16)
83#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11
84#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11)
85#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8
86#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8)
87#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6
88#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6)
89#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3
90#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3)
91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
93
94#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
95#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
96#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
97#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27)
98#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24
99#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24)
100#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18
101#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18)
102#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15
103#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15)
104#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9
105#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9)
106#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6
107#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6)
108#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0
109#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
110
111/* Bit definitions for RCSR */
112#define MXC_CCM_RCSR_NF16B 0x80000000
113
114/*
115 * LTR0 register offsets
116 */
117#define MXC_CCM_LTR0_DIV3CK_OFFSET 1
118#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
119#define MXC_CCM_LTR0_DNTHR_OFFSET 16
120#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
121#define MXC_CCM_LTR0_UPTHR_OFFSET 22
122#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
123
124/*
125 * LTR1 register offsets
126 */
127#define MXC_CCM_LTR1_PNCTHR_OFFSET 0
128#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
129#define MXC_CCM_LTR1_UPCNT_OFFSET 6
130#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
131#define MXC_CCM_LTR1_DNCNT_OFFSET 14
132#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
133#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
134#define MXC_CCM_LTR1_LTBRSR_OFFSET 22
135#define MXC_CCM_LTR1_LTBRSR 0x400000
136#define MXC_CCM_LTR1_LTBRSH 0x800000
137
138/*
139 * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
140 */
141#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
142#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \
143 MXC_CCM_LTR2_WSW_OFFSET((x)))
144#define MXC_CCM_LTR2_EMAC_OFFSET 0
145#define MXC_CCM_LTR2_EMAC_MASK 0x1FF
146
147/*
148 * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
149 */
150#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
151#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \
152 MXC_CCM_LTR3_WSW_OFFSET((x)))
153
154#define MXC_CCM_PMCR0_DFSUP1 0x80000000
155#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31)
156#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31)
157#define MXC_CCM_PMCR0_DFSUP0 0x40000000
158#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30)
159#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30)
160#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30)
161
162#define DVSUP_TURBO 0
163#define DVSUP_HIGH 1
164#define DVSUP_MEDIUM 2
165#define DVSUP_LOW 3
166#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28)
167#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28)
168#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28)
169#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28)
170#define MXC_CCM_PMCR0_DVSUP_OFFSET 28
171#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28)
172#define MXC_CCM_PMCR0_UDSC 0x08000000
173#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27)
174#define MXC_CCM_PMCR0_UDSC_UP (1 << 27)
175#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27)
176
177#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24)
178#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24)
179#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24)
180#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24)
181#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24)
182#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24)
183#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24)
184#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24)
185#define MXC_CCM_PMCR0_VSCNT_OFFSET 24
186#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24)
187#define MXC_CCM_PMCR0_DVFEV 0x00800000
188#define MXC_CCM_PMCR0_DVFIS 0x00400000
189#define MXC_CCM_PMCR0_LBMI 0x00200000
190#define MXC_CCM_PMCR0_LBFL 0x00100000
191#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18)
192#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18)
193#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18)
194#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18)
195#define MXC_CCM_PMCR0_LBCF_OFFSET 18
196#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18)
197#define MXC_CCM_PMCR0_PTVIS 0x00020000
198#define MXC_CCM_PMCR0_UPDTEN 0x00010000
199#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16)
200#define MXC_CCM_PMCR0_FSVAIM 0x00008000
201#define MXC_CCM_PMCR0_FSVAI_OFFSET 13
202#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13)
203#define MXC_CCM_PMCR0_DPVCR 0x00001000
204#define MXC_CCM_PMCR0_DPVV 0x00000800
205#define MXC_CCM_PMCR0_WFIM 0x00000400
206#define MXC_CCM_PMCR0_DRCE3 0x00000200
207#define MXC_CCM_PMCR0_DRCE2 0x00000100
208#define MXC_CCM_PMCR0_DRCE1 0x00000080
209#define MXC_CCM_PMCR0_DRCE0 0x00000040
210#define MXC_CCM_PMCR0_DCR 0x00000020
211#define MXC_CCM_PMCR0_DVFEN 0x00000010
212#define MXC_CCM_PMCR0_PTVAIM 0x00000008
213#define MXC_CCM_PMCR0_PTVAI_OFFSET 1
214#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1)
215#define MXC_CCM_PMCR0_DPTEN 0x00000001
216
217#define MXC_CCM_PMCR1_DVGP_OFFSET 0
218#define MXC_CCM_PMCR1_DVGP_MASK (0xF)
219
220#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7)
221#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8)
222
223#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22)
224#define MXC_CCM_DCVR_ULV_OFFSET 22
225#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12)
226#define MXC_CCM_DCVR_LLV_OFFSET 12
227#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2)
228#define MXC_CCM_DCVR_ELV_OFFSET 2
229
230#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7)
231#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7
232#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F
233#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0
234
235#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F
236#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
237#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6)
238#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6
239#define MXC_CCM_COSR_CLKOEN (1 << 9)
240
241/*
242 * PMCR0 register offsets
243 */
244#define MXC_CCM_PMCR0_LBFL_OFFSET 20
245#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
246#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
247
248#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
deleted file mode 100644
index 40f4e848a671..000000000000
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx31.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
13#define imx31_add_fsl_usb2_udc(pdata) \
14 imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
15
16extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
17#define imx31_add_imx2_wdt(pdata) \
18 imx_add_imx2_wdt(&imx31_imx2_wdt_data)
19
20extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
21#define imx31_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
23#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
24#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
25#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
26
27extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
28#define imx31_add_imx_keypad(pdata) \
29 imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
30
31extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
32#define imx31_add_imx_ssi(id, pdata) \
33 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
34
35extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
36#define imx31_add_imx_uart(id, pdata) \
37 imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
38#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
39#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
40#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
41#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
42#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
43
44extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
45#define imx31_add_mxc_ehci_otg(pdata) \
46 imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
47extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
48#define imx31_add_mxc_ehci_hs(id, pdata) \
49 imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
50
51extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
52#define imx31_add_mxc_mmc(id, pdata) \
53 imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
54
55extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
56#define imx31_add_mxc_nand(pdata) \
57 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
58
59extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
60#define imx31_add_mxc_w1(pdata) \
61 imx_add_mxc_w1(&imx31_mxc_w1_data)
62
63extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
64#define imx31_add_cspi(id, pdata) \
65 imx_add_spi_imx(&imx31_cspi_data[id], pdata)
66#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
67#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata)
68#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
deleted file mode 100644
index d545d86cc202..000000000000
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx35.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fec_data imx35_fec_data __initconst;
13#define imx35_add_fec(pdata) \
14 imx_add_fec(&imx35_fec_data, pdata)
15
16extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
17#define imx35_add_fsl_usb2_udc(pdata) \
18 imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
19
20extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
21#define imx35_add_flexcan(id, pdata) \
22 imx_add_flexcan(&imx35_flexcan_data[id], pdata)
23#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
24#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
25
26extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
27#define imx35_add_imx2_wdt(pdata) \
28 imx_add_imx2_wdt(&imx35_imx2_wdt_data)
29
30extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
31#define imx35_add_imx_i2c(id, pdata) \
32 imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
33#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
34#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
36
37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
38#define imx35_add_imx_keypad(pdata) \
39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
40
41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
42#define imx35_add_imx_ssi(id, pdata) \
43 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
44
45extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
46#define imx35_add_imx_uart(id, pdata) \
47 imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
48#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
49#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
50#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
51
52extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
53#define imx35_add_mxc_ehci_otg(pdata) \
54 imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
55extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
56#define imx35_add_mxc_ehci_hs(pdata) \
57 imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
58
59extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
60#define imx35_add_mxc_nand(pdata) \
61 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
62
63extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
64#define imx35_add_mxc_w1(pdata) \
65 imx_add_mxc_w1(&imx35_mxc_w1_data)
66
67extern const struct imx_sdhci_esdhc_imx_data
68imx35_sdhci_esdhc_imx_data[] __initconst;
69#define imx35_add_sdhci_esdhc_imx(id, pdata) \
70 imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
71
72extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
73#define imx35_add_cspi(id, pdata) \
74 imx_add_spi_imx(&imx35_cspi_data[id], pdata)
75#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
76#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
deleted file mode 100644
index b6672db788fb..000000000000
--- a/arch/arm/mach-mx3/devices.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/serial.h>
24#include <linux/gpio.h>
25#include <mach/hardware.h>
26#include <mach/irqs.h>
27#include <mach/common.h>
28#include <mach/mx3_camera.h>
29
30#include "devices.h"
31
32/* i.MX31 Image Processing Unit */
33
34/* The resource order is important! */
35static struct resource mx3_ipu_rsrc[] = {
36 {
37 .start = MX3x_IPU_CTRL_BASE_ADDR,
38 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
39 .flags = IORESOURCE_MEM,
40 }, {
41 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
42 .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
43 .flags = IORESOURCE_MEM,
44 }, {
45 .start = MX3x_INT_IPU_SYN,
46 .end = MX3x_INT_IPU_SYN,
47 .flags = IORESOURCE_IRQ,
48 }, {
49 .start = MX3x_INT_IPU_ERR,
50 .end = MX3x_INT_IPU_ERR,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55struct platform_device mx3_ipu = {
56 .name = "ipu-core",
57 .id = -1,
58 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
59 .resource = mx3_ipu_rsrc,
60};
61
62static struct resource fb_resources[] = {
63 {
64 .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
65 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
66 .flags = IORESOURCE_MEM,
67 },
68};
69
70struct platform_device mx3_fb = {
71 .name = "mx3_sdc_fb",
72 .id = -1,
73 .num_resources = ARRAY_SIZE(fb_resources),
74 .resource = fb_resources,
75 .dev = {
76 .coherent_dma_mask = DMA_BIT_MASK(32),
77 },
78};
79
80static struct resource camera_resources[] = {
81 {
82 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
83 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
84 .flags = IORESOURCE_MEM,
85 },
86};
87
88struct platform_device mx3_camera = {
89 .name = "mx3-camera",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(camera_resources),
92 .resource = camera_resources,
93 .dev = {
94 .coherent_dma_mask = DMA_BIT_MASK(32),
95 },
96};
97
98static struct resource imx_rtc_resources[] = {
99 {
100 .start = MX31_RTC_BASE_ADDR,
101 .end = MX31_RTC_BASE_ADDR + 0x3fff,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .start = MX31_INT_RTC,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110struct platform_device imx_rtc_device0 = {
111 .name = "mxc_rtc",
112 .id = -1,
113 .num_resources = ARRAY_SIZE(imx_rtc_resources),
114 .resource = imx_rtc_resources,
115};
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
deleted file mode 100644
index 121962c568d1..000000000000
--- a/arch/arm/mach-mx3/devices.h
+++ /dev/null
@@ -1,4 +0,0 @@
1extern struct platform_device mx3_ipu;
2extern struct platform_device mx3_fb;
3extern struct platform_device mx3_camera;
4extern struct platform_device imx_rtc_device0;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
deleted file mode 100644
index 314a983ac614..000000000000
--- a/arch/arm/mach-mx3/ehci-imx31.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX31_OTG_SIC_SHIFT 29
25#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
26#define MX31_OTG_PM_BIT (1 << 24)
27
28#define MX31_H2_SIC_SHIFT 21
29#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
30#define MX31_H2_PM_BIT (1 << 16)
31#define MX31_H2_DT_BIT (1 << 5)
32
33#define MX31_H1_SIC_SHIFT 13
34#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
35#define MX31_H1_PM_BIT (1 << 8)
36#define MX31_H1_DT_BIT (1 << 4)
37
38int mx31_initialize_usb_hw(int port, unsigned int flags)
39{
40 unsigned int v;
41
42 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
43
44 switch (port) {
45 case 0: /* OTG port */
46 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
47 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
48
49 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
50 v |= MX31_OTG_PM_BIT;
51
52 break;
53 case 1: /* H1 port */
54 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
55 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
56
57 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
58 v |= MX31_H1_PM_BIT;
59
60 if (!(flags & MXC_EHCI_TTL_ENABLED))
61 v |= MX31_H1_DT_BIT;
62
63 break;
64 case 2: /* H2 port */
65 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
66 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
67
68 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
69 v |= MX31_H2_PM_BIT;
70
71 if (!(flags & MXC_EHCI_TTL_ENABLED))
72 v |= MX31_H2_DT_BIT;
73
74 break;
75 default:
76 return -EINVAL;
77 }
78
79 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
80
81 return 0;
82}
83
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
deleted file mode 100644
index 33983a478c6b..000000000000
--- a/arch/arm/mach-mx3/ehci-imx35.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX35_OTG_SIC_SHIFT 29
25#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
26#define MX35_OTG_PM_BIT (1 << 24)
27
28#define MX35_H1_SIC_SHIFT 21
29#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
30#define MX35_H1_PM_BIT (1 << 8)
31#define MX35_H1_IPPUE_UP_BIT (1 << 7)
32#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
33#define MX35_H1_TLL_BIT (1 << 5)
34#define MX35_H1_USBTE_BIT (1 << 4)
35
36int mx35_initialize_usb_hw(int port, unsigned int flags)
37{
38 unsigned int v;
39
40 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
41
42 switch (port) {
43 case 0: /* OTG port */
44 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
45 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
46
47 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
48 v |= MX35_OTG_PM_BIT;
49
50 break;
51 case 1: /* H1 port */
52 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
53 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX35_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX35_H1_TLL_BIT;
61
62 if (flags & MXC_EHCI_INTERNAL_PHY)
63 v |= MX35_H1_USBTE_BIT;
64
65 if (flags & MXC_EHCI_IPPUE_DOWN)
66 v |= MX35_H1_IPPUE_DOWN_BIT;
67
68 if (flags & MXC_EHCI_IPPUE_UP)
69 v |= MX35_H1_IPPUE_UP_BIT;
70
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
77
78 return 0;
79}
80
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
deleted file mode 100644
index 2e288b38b4ad..000000000000
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ /dev/null
@@ -1,318 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <video/platform_lcd.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx35.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/audmux.h>
46#include <mach/esdhc.h>
47
48#include "devices-imx35.h"
49#include "devices.h"
50
51static const struct fb_videomode fb_modedb[] = {
52 {
53 .name = "CMO-QVGA",
54 .refresh = 60,
55 .xres = 320,
56 .yres = 240,
57 .pixclock = KHZ2PICOS(6500),
58 .left_margin = 68,
59 .right_margin = 20,
60 .upper_margin = 15,
61 .lower_margin = 4,
62 .hsync_len = 30,
63 .vsync_len = 3,
64 .sync = 0,
65 .vmode = FB_VMODE_NONINTERLACED,
66 .flag = 0,
67 },
68 {
69 .name = "DVI-VGA",
70 .refresh = 60,
71 .xres = 640,
72 .yres = 480,
73 .pixclock = 32000,
74 .left_margin = 100,
75 .right_margin = 100,
76 .upper_margin = 7,
77 .lower_margin = 100,
78 .hsync_len = 7,
79 .vsync_len = 7,
80 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
81 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
82 .vmode = FB_VMODE_NONINTERLACED,
83 .flag = 0,
84 },
85 {
86 .name = "DVI-SVGA",
87 .refresh = 60,
88 .xres = 800,
89 .yres = 600,
90 .pixclock = 25000,
91 .left_margin = 75,
92 .right_margin = 75,
93 .upper_margin = 7,
94 .lower_margin = 75,
95 .hsync_len = 7,
96 .vsync_len = 7,
97 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
98 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
99 .vmode = FB_VMODE_NONINTERLACED,
100 .flag = 0,
101 },
102};
103
104static struct ipu_platform_data mx3_ipu_data = {
105 .irq_base = MXC_IPU_IRQ_START,
106};
107
108static struct mx3fb_platform_data mx3fb_pdata = {
109 .dma_dev = &mx3_ipu.dev,
110 .name = "CMO-QVGA",
111 .mode = fb_modedb,
112 .num_modes = ARRAY_SIZE(fb_modedb),
113};
114
115static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
116 /* LCD */
117 MX35_PAD_LD0__IPU_DISPB_DAT_0,
118 MX35_PAD_LD1__IPU_DISPB_DAT_1,
119 MX35_PAD_LD2__IPU_DISPB_DAT_2,
120 MX35_PAD_LD3__IPU_DISPB_DAT_3,
121 MX35_PAD_LD4__IPU_DISPB_DAT_4,
122 MX35_PAD_LD5__IPU_DISPB_DAT_5,
123 MX35_PAD_LD6__IPU_DISPB_DAT_6,
124 MX35_PAD_LD7__IPU_DISPB_DAT_7,
125 MX35_PAD_LD8__IPU_DISPB_DAT_8,
126 MX35_PAD_LD9__IPU_DISPB_DAT_9,
127 MX35_PAD_LD10__IPU_DISPB_DAT_10,
128 MX35_PAD_LD11__IPU_DISPB_DAT_11,
129 MX35_PAD_LD12__IPU_DISPB_DAT_12,
130 MX35_PAD_LD13__IPU_DISPB_DAT_13,
131 MX35_PAD_LD14__IPU_DISPB_DAT_14,
132 MX35_PAD_LD15__IPU_DISPB_DAT_15,
133 MX35_PAD_LD16__IPU_DISPB_DAT_16,
134 MX35_PAD_LD17__IPU_DISPB_DAT_17,
135 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
136 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
137 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
138 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
139 /* Backlight */
140 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
141 /* LCD_PWR */
142 MX35_PAD_D3_CLS__GPIO1_4,
143 /* LED */
144 MX35_PAD_LD23__GPIO3_29,
145 /* SWITCH */
146 MX35_PAD_LD19__GPIO3_25,
147 /* UART2 */
148 MX35_PAD_CTS2__UART2_CTS,
149 MX35_PAD_RTS2__UART2_RTS,
150 MX35_PAD_TXD2__UART2_TXD_MUX,
151 MX35_PAD_RXD2__UART2_RXD_MUX,
152 /* I2S */
153 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
154 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
155 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
156 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
157 /* CAN2 */
158 MX35_PAD_TX5_RX0__CAN2_TXCAN,
159 MX35_PAD_TX4_RX1__CAN2_RXCAN,
160 /* SDCARD */
161 MX35_PAD_SD1_CMD__ESDHC1_CMD,
162 MX35_PAD_SD1_CLK__ESDHC1_CLK,
163 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
164 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
165 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
166 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
167 /* SD1 CD */
168 MX35_PAD_LD18__GPIO3_24,
169};
170
171#define GPIO_LED1 IMX_GPIO_NR(3, 29)
172#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
173#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
174#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
175
176static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
177 unsigned int power)
178{
179 if (power)
180 gpio_direction_output(GPIO_LCDPWR, 1);
181 else
182 gpio_direction_output(GPIO_LCDPWR, 0);
183}
184
185static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
186 .set_power = eukrea_mbimxsd_lcd_power_set,
187};
188
189static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
190 .name = "platform-lcd",
191 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
192};
193
194static struct gpio_led eukrea_mbimxsd_leds[] = {
195 {
196 .name = "led1",
197 .default_trigger = "heartbeat",
198 .active_low = 1,
199 .gpio = GPIO_LED1,
200 },
201};
202
203static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
204 .leds = eukrea_mbimxsd_leds,
205 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
206};
207
208static struct platform_device eukrea_mbimxsd_leds_gpio = {
209 .name = "leds-gpio",
210 .id = -1,
211 .dev = {
212 .platform_data = &eukrea_mbimxsd_led_info,
213 },
214};
215
216static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
217 {
218 .gpio = GPIO_SWITCH1,
219 .code = BTN_0,
220 .desc = "BP1",
221 .active_low = 1,
222 .wakeup = 1,
223 },
224};
225
226static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
227 .buttons = eukrea_mbimxsd_gpio_buttons,
228 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
229};
230
231static struct platform_device eukrea_mbimxsd_button_device = {
232 .name = "gpio-keys",
233 .id = -1,
234 .num_resources = 0,
235 .dev = {
236 .platform_data = &eukrea_mbimxsd_button_data,
237 }
238};
239
240static struct platform_device *platform_devices[] __initdata = {
241 &eukrea_mbimxsd_leds_gpio,
242 &eukrea_mbimxsd_button_device,
243 &eukrea_mbimxsd_lcd_powerdev,
244};
245
246static const struct imxuart_platform_data uart_pdata __initconst = {
247 .flags = IMXUART_HAVE_RTSCTS,
248};
249
250static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
251 {
252 I2C_BOARD_INFO("tlv320aic23", 0x1a),
253 },
254};
255
256static const
257struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
258 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
259};
260
261static struct esdhc_platform_data sd1_pdata = {
262 .cd_gpio = GPIO_SD1CD,
263 .wp_gpio = -EINVAL,
264};
265
266/*
267 * system init for baseboard usage. Will be called by cpuimx35 init.
268 *
269 * Add platform devices present on this baseboard and init
270 * them from CPU side as far as required to use them later on
271 */
272void __init eukrea_mbimxsd35_baseboard_init(void)
273{
274 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
275 ARRAY_SIZE(eukrea_mbimxsd_pads)))
276 printk(KERN_ERR "error setting mbimxsd pads !\n");
277
278#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
279 /* SSI unit master I2S codec connected to SSI_AUD4 */
280 mxc_audmux_v2_configure_port(0,
281 MXC_AUDMUX_V2_PTCR_SYN |
282 MXC_AUDMUX_V2_PTCR_TFSDIR |
283 MXC_AUDMUX_V2_PTCR_TFSEL(3) |
284 MXC_AUDMUX_V2_PTCR_TCLKDIR |
285 MXC_AUDMUX_V2_PTCR_TCSEL(3),
286 MXC_AUDMUX_V2_PDCR_RXDSEL(3)
287 );
288 mxc_audmux_v2_configure_port(3,
289 MXC_AUDMUX_V2_PTCR_SYN,
290 MXC_AUDMUX_V2_PDCR_RXDSEL(0)
291 );
292#endif
293
294 imx35_add_imx_uart1(&uart_pdata);
295 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
296 mxc_register_device(&mx3_fb, &mx3fb_pdata);
297
298 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
299
300 imx35_add_flexcan1(NULL);
301 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
302
303 gpio_request(GPIO_LED1, "LED1");
304 gpio_direction_output(GPIO_LED1, 1);
305 gpio_free(GPIO_LED1);
306
307 gpio_request(GPIO_SWITCH1, "SWITCH1");
308 gpio_direction_input(GPIO_SWITCH1);
309 gpio_free(GPIO_SWITCH1);
310
311 gpio_request(GPIO_LCDPWR, "LCDPWR");
312 gpio_direction_output(GPIO_LCDPWR, 1);
313
314 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
315 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
316
317 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
318}
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c
deleted file mode 100644
index cf8f8099ebd7..000000000000
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mx3.h>
28
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
35#define IOMUXGPR (IOMUX_BASE + 0x008)
36#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
37#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
38
39static DEFINE_SPINLOCK(gpio_mux_lock);
40
41#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
42
43unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
44/*
45 * set the mode for a IOMUX pin.
46 */
47int mxc_iomux_mode(unsigned int pin_mode)
48{
49 u32 field, l, mode, ret = 0;
50 void __iomem *reg;
51
52 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
53 field = pin_mode & 0x3;
54 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
55
56 spin_lock(&gpio_mux_lock);
57
58 l = __raw_readl(reg);
59 l &= ~(0xff << (field * 8));
60 l |= mode << (field * 8);
61 __raw_writel(l, reg);
62
63 spin_unlock(&gpio_mux_lock);
64
65 return ret;
66}
67EXPORT_SYMBOL(mxc_iomux_mode);
68
69/*
70 * This function configures the pad value for a IOMUX pin.
71 */
72void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
73{
74 u32 field, l;
75 void __iomem *reg;
76
77 pin &= IOMUX_PADNUM_MASK;
78 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
79 field = (pin + 2) % 3;
80
81 pr_debug("%s: reg offset = 0x%x, field = %d\n",
82 __func__, (pin + 2) / 3, field);
83
84 spin_lock(&gpio_mux_lock);
85
86 l = __raw_readl(reg);
87 l &= ~(0x1ff << (field * 10));
88 l |= config << (field * 10);
89 __raw_writel(l, reg);
90
91 spin_unlock(&gpio_mux_lock);
92}
93EXPORT_SYMBOL(mxc_iomux_set_pad);
94
95/*
96 * allocs a single pin:
97 * - reserves the pin so that it is not claimed by another driver
98 * - setups the iomux according to the configuration
99 */
100int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
101{
102 unsigned pad = pin & IOMUX_PADNUM_MASK;
103
104 if (pad >= (PIN_MAX + 1)) {
105 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
106 pad, label ? label : "?");
107 return -EINVAL;
108 }
109
110 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
111 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
112 pad, label ? label : "?");
113 return -EBUSY;
114 }
115 mxc_iomux_mode(pin);
116
117 return 0;
118}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120
121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label)
123{
124 const unsigned int *p = pin_list;
125 int i;
126 int ret = -EINVAL;
127
128 for (i = 0; i < count; i++) {
129 ret = mxc_iomux_alloc_pin(*p, label);
130 if (ret)
131 goto setup_error;
132 p++;
133 }
134 return 0;
135
136setup_error:
137 mxc_iomux_release_multiple_pins(pin_list, i);
138 return ret;
139}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141
142void mxc_iomux_release_pin(unsigned int pin)
143{
144 unsigned pad = pin & IOMUX_PADNUM_MASK;
145
146 if (pad < (PIN_MAX + 1))
147 clear_bit(pad, mxc_pin_alloc_map);
148}
149EXPORT_SYMBOL(mxc_iomux_release_pin);
150
151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{
153 const unsigned int *p = pin_list;
154 int i;
155
156 for (i = 0; i < count; i++) {
157 mxc_iomux_release_pin(*p);
158 p++;
159 }
160}
161EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
162
163/*
164 * This function enables/disables the general purpose function for a particular
165 * signal.
166 */
167void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
168{
169 u32 l;
170
171 spin_lock(&gpio_mux_lock);
172 l = __raw_readl(IOMUXGPR);
173 if (en)
174 l |= gp;
175 else
176 l &= ~gp;
177
178 __raw_writel(l, IOMUXGPR);
179 spin_unlock(&gpio_mux_lock);
180}
181EXPORT_SYMBOL(mxc_iomux_set_gpr);
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
deleted file mode 100644
index 226829bf7c25..000000000000
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ /dev/null
@@ -1,578 +0,0 @@
1/*
2 * armadillo5x0.c
3 *
4 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 * updates in http://alberdroid.blogspot.com/
6 *
7 * Based on Atmark Techno, Inc. armadillo 500 BSP 2008
8 * Based on mx31ads.c and pcm037.c Great Work!
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26#include <linux/types.h>
27#include <linux/init.h>
28#include <linux/clk.h>
29#include <linux/platform_device.h>
30#include <linux/gpio.h>
31#include <linux/smsc911x.h>
32#include <linux/interrupt.h>
33#include <linux/irq.h>
34#include <linux/mtd/physmap.h>
35#include <linux/io.h>
36#include <linux/input.h>
37#include <linux/gpio_keys.h>
38#include <linux/i2c.h>
39#include <linux/usb/otg.h>
40#include <linux/usb/ulpi.h>
41#include <linux/delay.h>
42
43#include <mach/hardware.h>
44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/time.h>
47#include <asm/memory.h>
48#include <asm/mach/map.h>
49
50#include <mach/common.h>
51#include <mach/iomux-mx3.h>
52#include <mach/ipu.h>
53#include <mach/mx3fb.h>
54#include <mach/ulpi.h>
55
56#include "devices-imx31.h"
57#include "devices.h"
58#include "crm_regs.h"
59
60static int armadillo5x0_pins[] = {
61 /* UART1 */
62 MX31_PIN_CTS1__CTS1,
63 MX31_PIN_RTS1__RTS1,
64 MX31_PIN_TXD1__TXD1,
65 MX31_PIN_RXD1__RXD1,
66 /* UART2 */
67 MX31_PIN_CTS2__CTS2,
68 MX31_PIN_RTS2__RTS2,
69 MX31_PIN_TXD2__TXD2,
70 MX31_PIN_RXD2__RXD2,
71 /* LAN9118_IRQ */
72 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO),
73 /* SDHC1 */
74 MX31_PIN_SD1_DATA3__SD1_DATA3,
75 MX31_PIN_SD1_DATA2__SD1_DATA2,
76 MX31_PIN_SD1_DATA1__SD1_DATA1,
77 MX31_PIN_SD1_DATA0__SD1_DATA0,
78 MX31_PIN_SD1_CLK__SD1_CLK,
79 MX31_PIN_SD1_CMD__SD1_CMD,
80 /* Framebuffer */
81 MX31_PIN_LD0__LD0,
82 MX31_PIN_LD1__LD1,
83 MX31_PIN_LD2__LD2,
84 MX31_PIN_LD3__LD3,
85 MX31_PIN_LD4__LD4,
86 MX31_PIN_LD5__LD5,
87 MX31_PIN_LD6__LD6,
88 MX31_PIN_LD7__LD7,
89 MX31_PIN_LD8__LD8,
90 MX31_PIN_LD9__LD9,
91 MX31_PIN_LD10__LD10,
92 MX31_PIN_LD11__LD11,
93 MX31_PIN_LD12__LD12,
94 MX31_PIN_LD13__LD13,
95 MX31_PIN_LD14__LD14,
96 MX31_PIN_LD15__LD15,
97 MX31_PIN_LD16__LD16,
98 MX31_PIN_LD17__LD17,
99 MX31_PIN_VSYNC3__VSYNC3,
100 MX31_PIN_HSYNC__HSYNC,
101 MX31_PIN_FPSHIFT__FPSHIFT,
102 MX31_PIN_DRDY0__DRDY0,
103 IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
104 /* I2C2 */
105 MX31_PIN_CSPI2_MOSI__SCL,
106 MX31_PIN_CSPI2_MISO__SDA,
107 /* OTG */
108 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
109 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
110 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
111 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
112 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
113 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
114 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
115 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
116 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
117 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
118 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
119 MX31_PIN_USBOTG_STP__USBOTG_STP,
120 /* USB host 2 */
121 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
122 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
123 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
124 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
125 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
126 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
127 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
128 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
129 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
130 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
131 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
132 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
133};
134
135/* USB */
136
137#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
138#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
139#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
140
141#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
142 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
143
144static int usbotg_init(struct platform_device *pdev)
145{
146 int err;
147
148 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
149 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
152 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
153 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
160
161 /* Chip already enabled by hardware */
162 /* OTG phy reset*/
163 err = gpio_request(OTG_RESET, "USB-OTG-RESET");
164 if (err) {
165 pr_err("Failed to request the usb otg reset gpio\n");
166 return err;
167 }
168
169 err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
170 if (err) {
171 pr_err("Failed to reset the usb otg phy\n");
172 goto otg_free_reset;
173 }
174
175 gpio_set_value(OTG_RESET, 0/*LOW*/);
176 mdelay(5);
177 gpio_set_value(OTG_RESET, 1/*HIGH*/);
178 mdelay(10);
179
180 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
181 MXC_EHCI_INTERFACE_DIFF_UNI);
182
183otg_free_reset:
184 gpio_free(OTG_RESET);
185 return err;
186}
187
188static int usbh2_init(struct platform_device *pdev)
189{
190 int err;
191
192 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
193 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
194 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
195 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
196 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
197 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
199 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
200 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
201 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
202 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
203 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
204
205 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
206
207
208 /* Enable the chip */
209 err = gpio_request(USBH2_CS, "USB-H2-CS");
210 if (err) {
211 pr_err("Failed to request the usb host 2 CS gpio\n");
212 return err;
213 }
214
215 err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
216 if (err) {
217 pr_err("Failed to drive the usb host 2 CS gpio\n");
218 goto h2_free_cs;
219 }
220
221 /* H2 phy reset*/
222 err = gpio_request(USBH2_RESET, "USB-H2-RESET");
223 if (err) {
224 pr_err("Failed to request the usb host 2 reset gpio\n");
225 goto h2_free_cs;
226 }
227
228 err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
229 if (err) {
230 pr_err("Failed to reset the usb host 2 phy\n");
231 goto h2_free_reset;
232 }
233
234 gpio_set_value(USBH2_RESET, 0/*LOW*/);
235 mdelay(5);
236 gpio_set_value(USBH2_RESET, 1/*HIGH*/);
237 mdelay(10);
238
239 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
240 MXC_EHCI_INTERFACE_DIFF_UNI);
241
242h2_free_reset:
243 gpio_free(USBH2_RESET);
244h2_free_cs:
245 gpio_free(USBH2_CS);
246 return err;
247}
248
249static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
250 .init = usbotg_init,
251 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
252};
253
254static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
255 .init = usbh2_init,
256 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
257};
258
259/* RTC over I2C*/
260#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
261
262static struct i2c_board_info armadillo5x0_i2c_rtc = {
263 I2C_BOARD_INFO("s35390a", 0x30),
264};
265
266/* GPIO BUTTONS */
267static struct gpio_keys_button armadillo5x0_buttons[] = {
268 {
269 .code = KEY_ENTER, /*28*/
270 .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
271 .active_low = 1,
272 .desc = "menu",
273 .wakeup = 1,
274 }, {
275 .code = KEY_BACK, /*158*/
276 .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
277 .active_low = 1,
278 .desc = "back",
279 .wakeup = 1,
280 }
281};
282
283static struct gpio_keys_platform_data armadillo5x0_button_data = {
284 .buttons = armadillo5x0_buttons,
285 .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
286};
287
288static struct platform_device armadillo5x0_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &armadillo5x0_button_data,
294 }
295};
296
297/*
298 * NAND Flash
299 */
300static const struct mxc_nand_platform_data
301armadillo5x0_nand_board_info __initconst = {
302 .width = 1,
303 .hw_ecc = 1,
304};
305
306/*
307 * MTD NOR Flash
308 */
309static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
310 {
311 .name = "nor.bootloader",
312 .offset = 0x00000000,
313 .size = 4*32*1024,
314 }, {
315 .name = "nor.kernel",
316 .offset = MTDPART_OFS_APPEND,
317 .size = 16*128*1024,
318 }, {
319 .name = "nor.userland",
320 .offset = MTDPART_OFS_APPEND,
321 .size = 110*128*1024,
322 }, {
323 .name = "nor.config",
324 .offset = MTDPART_OFS_APPEND,
325 .size = 1*128*1024,
326 },
327};
328
329static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
330 .width = 2,
331 .parts = armadillo5x0_nor_flash_partitions,
332 .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
333};
334
335static struct resource armadillo5x0_nor_flash_resource = {
336 .flags = IORESOURCE_MEM,
337 .start = MX31_CS0_BASE_ADDR,
338 .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
339};
340
341static struct platform_device armadillo5x0_nor_flash = {
342 .name = "physmap-flash",
343 .id = -1,
344 .num_resources = 1,
345 .resource = &armadillo5x0_nor_flash_resource,
346};
347
348/*
349 * FB support
350 */
351static const struct fb_videomode fb_modedb[] = {
352 { /* 640x480 @ 60 Hz */
353 .name = "CRT-VGA",
354 .refresh = 60,
355 .xres = 640,
356 .yres = 480,
357 .pixclock = 39721,
358 .left_margin = 35,
359 .right_margin = 115,
360 .upper_margin = 43,
361 .lower_margin = 1,
362 .hsync_len = 10,
363 .vsync_len = 1,
364 .sync = FB_SYNC_OE_ACT_HIGH,
365 .vmode = FB_VMODE_NONINTERLACED,
366 .flag = 0,
367 }, {/* 800x600 @ 56 Hz */
368 .name = "CRT-SVGA",
369 .refresh = 56,
370 .xres = 800,
371 .yres = 600,
372 .pixclock = 30000,
373 .left_margin = 30,
374 .right_margin = 108,
375 .upper_margin = 13,
376 .lower_margin = 10,
377 .hsync_len = 10,
378 .vsync_len = 1,
379 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT |
380 FB_SYNC_VERT_HIGH_ACT,
381 .vmode = FB_VMODE_NONINTERLACED,
382 .flag = 0,
383 },
384};
385
386static struct ipu_platform_data mx3_ipu_data = {
387 .irq_base = MXC_IPU_IRQ_START,
388};
389
390static struct mx3fb_platform_data mx3fb_pdata = {
391 .dma_dev = &mx3_ipu.dev,
392 .name = "CRT-VGA",
393 .mode = fb_modedb,
394 .num_modes = ARRAY_SIZE(fb_modedb),
395};
396
397/*
398 * SDHC 1
399 * MMC support
400 */
401static int armadillo5x0_sdhc1_get_ro(struct device *dev)
402{
403 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
404}
405
406static int armadillo5x0_sdhc1_init(struct device *dev,
407 irq_handler_t detect_irq, void *data)
408{
409 int ret;
410 int gpio_det, gpio_wp;
411
412 gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK);
413 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B);
414
415 ret = gpio_request(gpio_det, "sdhc-card-detect");
416 if (ret)
417 return ret;
418
419 gpio_direction_input(gpio_det);
420
421 ret = gpio_request(gpio_wp, "sdhc-write-protect");
422 if (ret)
423 goto err_gpio_free;
424
425 gpio_direction_input(gpio_wp);
426
427 /* When supported the trigger type have to be BOTH */
428 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
429 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
430 "sdhc-detect", data);
431
432 if (ret)
433 goto err_gpio_free_2;
434
435 return 0;
436
437err_gpio_free_2:
438 gpio_free(gpio_wp);
439
440err_gpio_free:
441 gpio_free(gpio_det);
442
443 return ret;
444
445}
446
447static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
448{
449 free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
450 gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
451 gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
452}
453
454static const struct imxmmc_platform_data sdhc_pdata __initconst = {
455 .get_ro = armadillo5x0_sdhc1_get_ro,
456 .init = armadillo5x0_sdhc1_init,
457 .exit = armadillo5x0_sdhc1_exit,
458};
459
460/*
461 * SMSC 9118
462 * Network support
463 */
464static struct resource armadillo5x0_smc911x_resources[] = {
465 {
466 .start = MX31_CS3_BASE_ADDR,
467 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
468 .flags = IORESOURCE_MEM,
469 }, {
470 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
471 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
472 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
473 },
474};
475
476static struct smsc911x_platform_config smsc911x_info = {
477 .flags = SMSC911X_USE_16BIT,
478 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
479 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
480};
481
482static struct platform_device armadillo5x0_smc911x_device = {
483 .name = "smsc911x",
484 .id = -1,
485 .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources),
486 .resource = armadillo5x0_smc911x_resources,
487 .dev = {
488 .platform_data = &smsc911x_info,
489 },
490};
491
492/* UART device data */
493static const struct imxuart_platform_data uart_pdata __initconst = {
494 .flags = IMXUART_HAVE_RTSCTS,
495};
496
497static struct platform_device *devices[] __initdata = {
498 &armadillo5x0_smc911x_device,
499 &armadillo5x0_button_device,
500};
501
502/*
503 * Perform board specific initializations
504 */
505static void __init armadillo5x0_init(void)
506{
507 mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
508 ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
509
510 platform_add_devices(devices, ARRAY_SIZE(devices));
511 imx31_add_imx_i2c1(NULL);
512
513 /* Register UART */
514 imx31_add_imx_uart0(&uart_pdata);
515 imx31_add_imx_uart1(&uart_pdata);
516
517 /* SMSC9118 IRQ pin */
518 gpio_direction_input(MX31_PIN_GPIO1_0);
519
520 /* Register SDHC */
521 imx31_add_mxc_mmc(0, &sdhc_pdata);
522
523 /* Register FB */
524 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
525 mxc_register_device(&mx3_fb, &mx3fb_pdata);
526
527 /* Register NOR Flash */
528 mxc_register_device(&armadillo5x0_nor_flash,
529 &armadillo5x0_nor_flash_pdata);
530
531 /* Register NAND Flash */
532 imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
533
534 /* set NAND page size to 2k if not configured via boot mode pins */
535 __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
536
537 /* RTC */
538 /* Get RTC IRQ and register the chip */
539 if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
540 if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
541 armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
542 else
543 gpio_free(ARMADILLO5X0_RTC_GPIO);
544 }
545 if (armadillo5x0_i2c_rtc.irq == 0)
546 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
547 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
548
549 /* USB */
550
551 usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
552 ULPI_OTG_DRVVBUS_EXT);
553 if (usbotg_pdata.otg)
554 imx31_add_mxc_ehci_otg(&usbotg_pdata);
555 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
556 ULPI_OTG_DRVVBUS_EXT);
557 if (usbh2_pdata.otg)
558 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
559}
560
561static void __init armadillo5x0_timer_init(void)
562{
563 mx31_clocks_init(26000000);
564}
565
566static struct sys_timer armadillo5x0_timer = {
567 .init = armadillo5x0_timer_init,
568};
569
570MACHINE_START(ARMADILLO5X0, "Armadillo-500")
571 /* Maintainer: Alberto Panizzo */
572 .boot_params = MX3x_PHYS_OFFSET + 0x100,
573 .map_io = mx31_map_io,
574 .init_early = imx31_init_early,
575 .init_irq = mx31_init_irq,
576 .timer = &armadillo5x0_timer,
577 .init_machine = armadillo5x0_init,
578MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
deleted file mode 100644
index d137d7078ee9..000000000000
--- a/arch/arm/mach-mx3/mach-bug.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21
22#include <mach/iomux-mx3.h>
23#include <mach/imx-uart.h>
24#include <mach/hardware.h>
25#include <mach/common.h>
26
27#include <asm/mach/time.h>
28#include <asm/mach/arch.h>
29#include <asm/mach-types.h>
30
31#include "devices-imx31.h"
32
33static const struct imxuart_platform_data uart_pdata __initconst = {
34 .flags = IMXUART_HAVE_RTSCTS,
35};
36
37static const unsigned int bug_pins[] __initconst = {
38 MX31_PIN_PC_RST__CTS5,
39 MX31_PIN_PC_VS2__RTS5,
40 MX31_PIN_PC_BVD2__TXD5,
41 MX31_PIN_PC_BVD1__RXD5,
42};
43
44static void __init bug_board_init(void)
45{
46 mxc_iomux_setup_multiple_pins(bug_pins,
47 ARRAY_SIZE(bug_pins), "uart-4");
48 imx31_add_imx_uart4(&uart_pdata);
49}
50
51static void __init bug_timer_init(void)
52{
53 mx31_clocks_init(26000000);
54}
55
56static struct sys_timer bug_timer = {
57 .init = bug_timer_init,
58};
59
60MACHINE_START(BUG, "BugLabs BUGBase")
61 .map_io = mx31_map_io,
62 .init_early = imx31_init_early,
63 .init_irq = mx31_init_irq,
64 .timer = &bug_timer,
65 .init_machine = bug_board_init,
66MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
deleted file mode 100644
index ec63d998f647..000000000000
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ /dev/null
@@ -1,203 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/i2c/tsc2007.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/i2c-gpio.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38#include <asm/mach/map.h>
39
40#include <mach/eukrea-baseboards.h>
41#include <mach/hardware.h>
42#include <mach/common.h>
43#include <mach/iomux-mx35.h>
44#include <mach/mxc_nand.h>
45
46#include "devices-imx35.h"
47#include "devices.h"
48
49static const struct imxuart_platform_data uart_pdata __initconst = {
50 .flags = IMXUART_HAVE_RTSCTS,
51};
52
53static const struct imxi2c_platform_data
54 eukrea_cpuimx35_i2c0_data __initconst = {
55 .bitrate = 100000,
56};
57
58static struct tsc2007_platform_data tsc2007_info = {
59 .model = 2007,
60 .x_plate_ohms = 180,
61};
62
63#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
64static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
65 {
66 I2C_BOARD_INFO("pcf8563", 0x51),
67 }, {
68 I2C_BOARD_INFO("tsc2007", 0x48),
69 .type = "tsc2007",
70 .platform_data = &tsc2007_info,
71 .irq = gpio_to_irq(TSC2007_IRQGPIO),
72 },
73};
74
75static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
76 /* UART1 */
77 MX35_PAD_CTS1__UART1_CTS,
78 MX35_PAD_RTS1__UART1_RTS,
79 MX35_PAD_TXD1__UART1_TXD_MUX,
80 MX35_PAD_RXD1__UART1_RXD_MUX,
81 /* FEC */
82 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
83 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
84 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
85 MX35_PAD_FEC_COL__FEC_COL,
86 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
87 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
88 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
89 MX35_PAD_FEC_MDC__FEC_MDC,
90 MX35_PAD_FEC_MDIO__FEC_MDIO,
91 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
92 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
93 MX35_PAD_FEC_CRS__FEC_CRS,
94 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
95 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
96 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
97 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
98 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
99 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
100 /* I2C1 */
101 MX35_PAD_I2C1_CLK__I2C1_SCL,
102 MX35_PAD_I2C1_DAT__I2C1_SDA,
103 /* TSC2007 IRQ */
104 MX35_PAD_ATA_DA2__GPIO3_2,
105};
106
107static const struct mxc_nand_platform_data
108 eukrea_cpuimx35_nand_board_info __initconst = {
109 .width = 1,
110 .hw_ecc = 1,
111 .flash_bbt = 1,
112};
113
114static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
115{
116 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
117}
118
119static const struct mxc_usbh_platform_data otg_pdata __initconst = {
120 .init = eukrea_cpuimx35_otg_init,
121 .portsc = MXC_EHCI_MODE_UTMI,
122};
123
124static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
125{
126 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
127 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
128}
129
130static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
131 .init = eukrea_cpuimx35_usbh1_init,
132 .portsc = MXC_EHCI_MODE_SERIAL,
133};
134
135static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
136 .operating_mode = FSL_USB2_DR_DEVICE,
137 .phy_mode = FSL_USB2_PHY_UTMI,
138 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
139};
140
141static int otg_mode_host;
142
143static int __init eukrea_cpuimx35_otg_mode(char *options)
144{
145 if (!strcmp(options, "host"))
146 otg_mode_host = 1;
147 else if (!strcmp(options, "device"))
148 otg_mode_host = 0;
149 else
150 pr_info("otg_mode neither \"host\" nor \"device\". "
151 "Defaulting to device\n");
152 return 0;
153}
154__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
155
156/*
157 * Board specific initialization.
158 */
159static void __init eukrea_cpuimx35_init(void)
160{
161 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
162 ARRAY_SIZE(eukrea_cpuimx35_pads));
163
164 imx35_add_fec(NULL);
165 imx35_add_imx2_wdt(NULL);
166
167 imx35_add_imx_uart0(&uart_pdata);
168 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
169
170 i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
171 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
172 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
173
174 if (otg_mode_host)
175 imx35_add_mxc_ehci_otg(&otg_pdata);
176 else
177 imx35_add_fsl_usb2_udc(&otg_device_pdata);
178
179 imx35_add_mxc_ehci_hs(&usbh1_pdata);
180
181#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
182 eukrea_mbimxsd35_baseboard_init();
183#endif
184}
185
186static void __init eukrea_cpuimx35_timer_init(void)
187{
188 mx35_clocks_init();
189}
190
191struct sys_timer eukrea_cpuimx35_timer = {
192 .init = eukrea_cpuimx35_timer_init,
193};
194
195MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
196 /* Maintainer: Eukrea Electromatique */
197 .boot_params = MX3x_PHYS_OFFSET + 0x100,
198 .map_io = mx35_map_io,
199 .init_early = imx35_init_early,
200 .init_irq = mx35_init_irq,
201 .timer = &eukrea_cpuimx35_timer,
202 .init_machine = eukrea_cpuimx35_init,
203MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
deleted file mode 100644
index d35621d62b4d..000000000000
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
4 *
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/gpio.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25#include <linux/smsc911x.h>
26#include <linux/types.h>
27
28#include <asm/irq.h>
29#include <asm/mach-types.h>
30#include <asm/memory.h>
31#include <asm/setup.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/irq.h>
34#include <asm/mach/map.h>
35#include <asm/mach/time.h>
36
37#include <mach/clock.h>
38#include <mach/common.h>
39#include <mach/iomux-mx3.h>
40
41#include "devices-imx31.h"
42#include "devices.h"
43
44#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
46 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
47 MX31_IO_ADDRESS(x))
48
49/*
50 * KZM-ARM11-01 Board Control Registers on FPGA
51 */
52#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
53#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
54#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
55#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
56#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
57#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
58#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
59#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
60
61/*
62 * External UART for touch panel on FPGA
63 */
64#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
65
66#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
67/*
68 * KZM-ARM11-01 has an external UART on FPGA
69 */
70static struct plat_serial8250_port serial_platform_data[] = {
71 {
72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
73 .mapbase = KZM_ARM11_16550,
74 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
75 .irqflags = IRQ_TYPE_EDGE_RISING,
76 .uartclk = 14745600,
77 .regshift = 0,
78 .iotype = UPIO_MEM,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_BUGGY_UART,
81 },
82 {},
83};
84
85static struct resource serial8250_resources[] = {
86 {
87 .start = KZM_ARM11_16550,
88 .end = KZM_ARM11_16550 + 0x10,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
93 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct platform_device serial_device = {
99 .name = "serial8250",
100 .id = PLAT8250_DEV_PLATFORM,
101 .dev = {
102 .platform_data = serial_platform_data,
103 },
104 .num_resources = ARRAY_SIZE(serial8250_resources),
105 .resource = serial8250_resources,
106};
107
108static int __init kzm_init_ext_uart(void)
109{
110 u8 tmp;
111
112 /*
113 * GPIO 1-1: external UART interrupt line
114 */
115 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
116 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
117 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
118
119 /*
120 * Unmask UART interrupt
121 */
122 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
123 tmp |= 0x2;
124 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
125
126 return platform_device_register(&serial_device);
127}
128#else
129static inline int kzm_init_ext_uart(void)
130{
131 return 0;
132}
133#endif
134
135/*
136 * SMSC LAN9118
137 */
138#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
139static struct smsc911x_platform_config kzm_smsc9118_config = {
140 .phy_interface = PHY_INTERFACE_MODE_MII,
141 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
142 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
143 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
144};
145
146static struct resource kzm_smsc9118_resources[] = {
147 {
148 .start = MX31_CS5_BASE_ADDR,
149 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 {
153 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
154 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
155 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
156 },
157};
158
159static struct platform_device kzm_smsc9118_device = {
160 .name = "smsc911x",
161 .id = -1,
162 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
163 .resource = kzm_smsc9118_resources,
164 .dev = {
165 .platform_data = &kzm_smsc9118_config,
166 },
167};
168
169static int __init kzm_init_smsc9118(void)
170{
171 /*
172 * GPIO 1-2: SMSC9118 interrupt line
173 */
174 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
175 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
176 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
177
178 return platform_device_register(&kzm_smsc9118_device);
179}
180#else
181static inline int kzm_init_smsc9118(void)
182{
183 return 0;
184}
185#endif
186
187#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
188static const struct imxuart_platform_data uart_pdata __initconst = {
189 .flags = IMXUART_HAVE_RTSCTS,
190};
191
192static void __init kzm_init_imx_uart(void)
193{
194 imx31_add_imx_uart0(&uart_pdata);
195 imx31_add_imx_uart1(&uart_pdata);
196}
197#else
198static inline void kzm_init_imx_uart(void)
199{
200}
201#endif
202
203static int kzm_pins[] __initdata = {
204 MX31_PIN_CTS1__CTS1,
205 MX31_PIN_RTS1__RTS1,
206 MX31_PIN_TXD1__TXD1,
207 MX31_PIN_RXD1__RXD1,
208 MX31_PIN_DCD_DCE1__DCD_DCE1,
209 MX31_PIN_RI_DCE1__RI_DCE1,
210 MX31_PIN_DSR_DCE1__DSR_DCE1,
211 MX31_PIN_DTR_DCE1__DTR_DCE1,
212 MX31_PIN_CTS2__CTS2,
213 MX31_PIN_RTS2__RTS2,
214 MX31_PIN_TXD2__TXD2,
215 MX31_PIN_RXD2__RXD2,
216 MX31_PIN_DCD_DTE1__DCD_DTE2,
217 MX31_PIN_RI_DTE1__RI_DTE2,
218 MX31_PIN_DSR_DTE1__DSR_DTE2,
219 MX31_PIN_DTR_DTE1__DTR_DTE2,
220};
221
222/*
223 * Board specific initialization.
224 */
225static void __init kzm_board_init(void)
226{
227 mxc_iomux_setup_multiple_pins(kzm_pins,
228 ARRAY_SIZE(kzm_pins), "kzm");
229 kzm_init_ext_uart();
230 kzm_init_smsc9118();
231 kzm_init_imx_uart();
232
233 pr_info("Clock input source is 26MHz\n");
234}
235
236/*
237 * This structure defines static mappings for the kzm-arm11-01 board.
238 */
239static struct map_desc kzm_io_desc[] __initdata = {
240 {
241 .virtual = MX31_CS4_BASE_ADDR_VIRT,
242 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
243 .length = MX31_CS4_SIZE,
244 .type = MT_DEVICE
245 },
246 {
247 .virtual = MX31_CS5_BASE_ADDR_VIRT,
248 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
249 .length = MX31_CS5_SIZE,
250 .type = MT_DEVICE
251 },
252};
253
254/*
255 * Set up static virtual mappings.
256 */
257static void __init kzm_map_io(void)
258{
259 mx31_map_io();
260 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
261}
262
263static void __init kzm_timer_init(void)
264{
265 mx31_clocks_init(26000000);
266}
267
268static struct sys_timer kzm_timer = {
269 .init = kzm_timer_init,
270};
271
272MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
273 .boot_params = MX3x_PHYS_OFFSET + 0x100,
274 .map_io = kzm_map_io,
275 .init_early = imx31_init_early,
276 .init_irq = mx31_init_irq,
277 .timer = &kzm_timer,
278 .init_machine = kzm_board_init,
279MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
deleted file mode 100644
index 034be624d35c..000000000000
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ /dev/null
@@ -1,771 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
20#include <linux/gpio.h>
21#include <linux/platform_device.h>
22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/l4f00242t03.h>
25#include <linux/regulator/machine.h>
26#include <linux/usb/otg.h>
27#include <linux/usb/ulpi.h>
28#include <linux/memblock.h>
29
30#include <media/soc_camera.h>
31
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <asm/memory.h>
37#include <asm/mach/map.h>
38#include <mach/common.h>
39#include <mach/iomux-mx3.h>
40#include <mach/3ds_debugboard.h>
41#include <mach/ulpi.h>
42#include <mach/mmc.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/mx3_camera.h>
46
47#include "devices-imx31.h"
48#include "devices.h"
49
50/* CPLD IRQ line for external uart, external ethernet etc */
51#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
52
53static int mx31_3ds_pins[] = {
54 /* UART1 */
55 MX31_PIN_CTS1__CTS1,
56 MX31_PIN_RTS1__RTS1,
57 MX31_PIN_TXD1__TXD1,
58 MX31_PIN_RXD1__RXD1,
59 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
60 /*SPI0*/
61 MX31_PIN_CSPI1_SCLK__SCLK,
62 MX31_PIN_CSPI1_MOSI__MOSI,
63 MX31_PIN_CSPI1_MISO__MISO,
64 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
65 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
66 /* SPI 1 */
67 MX31_PIN_CSPI2_SCLK__SCLK,
68 MX31_PIN_CSPI2_MOSI__MOSI,
69 MX31_PIN_CSPI2_MISO__MISO,
70 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
71 MX31_PIN_CSPI2_SS0__SS0,
72 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
73 /* MC13783 IRQ */
74 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
75 /* USB OTG reset */
76 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
77 /* USB OTG */
78 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
79 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
80 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
81 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
82 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
83 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
84 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
85 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
86 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
87 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
88 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
89 MX31_PIN_USBOTG_STP__USBOTG_STP,
90 /*Keyboard*/
91 MX31_PIN_KEY_ROW0_KEY_ROW0,
92 MX31_PIN_KEY_ROW1_KEY_ROW1,
93 MX31_PIN_KEY_ROW2_KEY_ROW2,
94 MX31_PIN_KEY_COL0_KEY_COL0,
95 MX31_PIN_KEY_COL1_KEY_COL1,
96 MX31_PIN_KEY_COL2_KEY_COL2,
97 MX31_PIN_KEY_COL3_KEY_COL3,
98 /* USB Host 2 */
99 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
100 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
101 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
102 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
103 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
104 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
105 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
106 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
107 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
108 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
109 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
110 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
111 /* USB Host2 reset */
112 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
113 /* I2C1 */
114 MX31_PIN_I2C_CLK__I2C1_SCL,
115 MX31_PIN_I2C_DAT__I2C1_SDA,
116 /* SDHC1 */
117 MX31_PIN_SD1_DATA3__SD1_DATA3,
118 MX31_PIN_SD1_DATA2__SD1_DATA2,
119 MX31_PIN_SD1_DATA1__SD1_DATA1,
120 MX31_PIN_SD1_DATA0__SD1_DATA0,
121 MX31_PIN_SD1_CLK__SD1_CLK,
122 MX31_PIN_SD1_CMD__SD1_CMD,
123 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
124 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
125 /* Framebuffer */
126 MX31_PIN_LD0__LD0,
127 MX31_PIN_LD1__LD1,
128 MX31_PIN_LD2__LD2,
129 MX31_PIN_LD3__LD3,
130 MX31_PIN_LD4__LD4,
131 MX31_PIN_LD5__LD5,
132 MX31_PIN_LD6__LD6,
133 MX31_PIN_LD7__LD7,
134 MX31_PIN_LD8__LD8,
135 MX31_PIN_LD9__LD9,
136 MX31_PIN_LD10__LD10,
137 MX31_PIN_LD11__LD11,
138 MX31_PIN_LD12__LD12,
139 MX31_PIN_LD13__LD13,
140 MX31_PIN_LD14__LD14,
141 MX31_PIN_LD15__LD15,
142 MX31_PIN_LD16__LD16,
143 MX31_PIN_LD17__LD17,
144 MX31_PIN_VSYNC3__VSYNC3,
145 MX31_PIN_HSYNC__HSYNC,
146 MX31_PIN_FPSHIFT__FPSHIFT,
147 MX31_PIN_CONTRAST__CONTRAST,
148 /* CSI */
149 MX31_PIN_CSI_D6__CSI_D6,
150 MX31_PIN_CSI_D7__CSI_D7,
151 MX31_PIN_CSI_D8__CSI_D8,
152 MX31_PIN_CSI_D9__CSI_D9,
153 MX31_PIN_CSI_D10__CSI_D10,
154 MX31_PIN_CSI_D11__CSI_D11,
155 MX31_PIN_CSI_D12__CSI_D12,
156 MX31_PIN_CSI_D13__CSI_D13,
157 MX31_PIN_CSI_D14__CSI_D14,
158 MX31_PIN_CSI_D15__CSI_D15,
159 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
160 MX31_PIN_CSI_MCLK__CSI_MCLK,
161 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
162 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
163 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
164 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
165};
166
167/*
168 * Camera support
169 */
170static phys_addr_t mx3_camera_base __initdata;
171#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
172
173#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
174#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
175
176static struct gpio mx31_3ds_camera_gpios[] = {
177 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
178 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
179};
180
181static int __init mx31_3ds_camera_alloc_dma(void)
182{
183 int dma;
184
185 if (!mx3_camera_base)
186 return -ENOMEM;
187
188 dma = dma_declare_coherent_memory(&mx3_camera.dev,
189 mx3_camera_base, mx3_camera_base,
190 MX31_3DS_CAMERA_BUF_SIZE,
191 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
192
193 if (!(dma & DMA_MEMORY_MAP))
194 return -ENOMEM;
195
196 return 0;
197}
198
199static int mx31_3ds_camera_power(struct device *dev, int on)
200{
201 /* enable or disable the camera */
202 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
203 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
204
205 if (!on)
206 goto out;
207
208 /* If enabled, give a reset impulse */
209 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
210 msleep(20);
211 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
212 msleep(100);
213
214out:
215 return 0;
216}
217
218static struct i2c_board_info mx31_3ds_i2c_camera = {
219 I2C_BOARD_INFO("ov2640", 0x30),
220};
221
222static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
223 { .supply = "cmos_vcore" },
224 { .supply = "cmos_2v8" },
225};
226
227static struct soc_camera_link iclink_ov2640 = {
228 .bus_id = 0,
229 .board_info = &mx31_3ds_i2c_camera,
230 .i2c_adapter_id = 0,
231 .power = mx31_3ds_camera_power,
232 .regulators = mx31_3ds_camera_regs,
233 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
234};
235
236static struct platform_device mx31_3ds_ov2640 = {
237 .name = "soc-camera-pdrv",
238 .id = 0,
239 .dev = {
240 .platform_data = &iclink_ov2640,
241 },
242};
243
244struct mx3_camera_pdata mx31_3ds_camera_pdata = {
245 .dma_dev = &mx3_ipu.dev,
246 .flags = MX3_CAMERA_DATAWIDTH_10,
247 .mclk_10khz = 2600,
248};
249
250/*
251 * FB support
252 */
253static const struct fb_videomode fb_modedb[] = {
254 { /* 480x640 @ 60 Hz */
255 .name = "Epson-VGA",
256 .refresh = 60,
257 .xres = 480,
258 .yres = 640,
259 .pixclock = 41701,
260 .left_margin = 20,
261 .right_margin = 41,
262 .upper_margin = 10,
263 .lower_margin = 5,
264 .hsync_len = 20,
265 .vsync_len = 10,
266 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
267 .vmode = FB_VMODE_NONINTERLACED,
268 .flag = 0,
269 },
270};
271
272static struct ipu_platform_data mx3_ipu_data = {
273 .irq_base = MXC_IPU_IRQ_START,
274};
275
276static struct mx3fb_platform_data mx3fb_pdata = {
277 .dma_dev = &mx3_ipu.dev,
278 .name = "Epson-VGA",
279 .mode = fb_modedb,
280 .num_modes = ARRAY_SIZE(fb_modedb),
281};
282
283/* LCD */
284static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
285 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
286 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
287 .core_supply = "lcd_2v8",
288 .io_supply = "vdd_lcdio",
289};
290
291/*
292 * Support for SD card slot in personality board
293 */
294#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
295#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
296
297static struct gpio mx31_3ds_sdhc1_gpios[] = {
298 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
299 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
300};
301
302static int mx31_3ds_sdhc1_init(struct device *dev,
303 irq_handler_t detect_irq,
304 void *data)
305{
306 int ret;
307
308 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
309 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
310 if (ret) {
311 pr_warning("Unable to request the SD/MMC GPIOs.\n");
312 return ret;
313 }
314
315 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
316 detect_irq, IRQF_DISABLED |
317 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
318 "sdhc1-detect", data);
319 if (ret) {
320 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
321 goto gpio_free;
322 }
323
324 return 0;
325
326gpio_free:
327 gpio_free_array(mx31_3ds_sdhc1_gpios,
328 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
329 return ret;
330}
331
332static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
333{
334 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
335 gpio_free_array(mx31_3ds_sdhc1_gpios,
336 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
337}
338
339static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
340{
341 /*
342 * While the voltage stuff is done by the driver, activate the
343 * Buffer Enable Pin only if there is a card in slot to fix the card
344 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
345 * Done here because at this stage we have for sure a debounced value
346 * of the presence of the card, showed by the value of vdd.
347 * 7 == ilog2(MMC_VDD_165_195)
348 */
349 if (vdd > 7)
350 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
351 else
352 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
353}
354
355static struct imxmmc_platform_data sdhc1_pdata = {
356 .init = mx31_3ds_sdhc1_init,
357 .exit = mx31_3ds_sdhc1_exit,
358 .setpower = mx31_3ds_sdhc1_setpower,
359};
360
361/*
362 * Matrix keyboard
363 */
364
365static const uint32_t mx31_3ds_keymap[] = {
366 KEY(0, 0, KEY_UP),
367 KEY(0, 1, KEY_DOWN),
368 KEY(1, 0, KEY_RIGHT),
369 KEY(1, 1, KEY_LEFT),
370 KEY(1, 2, KEY_ENTER),
371 KEY(2, 0, KEY_F6),
372 KEY(2, 1, KEY_F8),
373 KEY(2, 2, KEY_F9),
374 KEY(2, 3, KEY_F10),
375};
376
377static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
378 .keymap = mx31_3ds_keymap,
379 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
380};
381
382/* Regulators */
383static struct regulator_init_data pwgtx_init = {
384 .constraints = {
385 .boot_on = 1,
386 .always_on = 1,
387 },
388};
389
390static struct regulator_init_data gpo_init = {
391 .constraints = {
392 .boot_on = 1,
393 .always_on = 1,
394 }
395};
396
397static struct regulator_consumer_supply vmmc2_consumers[] = {
398 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
399};
400
401static struct regulator_init_data vmmc2_init = {
402 .constraints = {
403 .min_uV = 3000000,
404 .max_uV = 3000000,
405 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
406 REGULATOR_CHANGE_STATUS,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
409 .consumer_supplies = vmmc2_consumers,
410};
411
412static struct regulator_consumer_supply vmmc1_consumers[] = {
413 REGULATOR_SUPPLY("lcd_2v8", NULL),
414 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
415};
416
417static struct regulator_init_data vmmc1_init = {
418 .constraints = {
419 .min_uV = 2800000,
420 .max_uV = 2800000,
421 .apply_uV = 1,
422 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
423 REGULATOR_CHANGE_STATUS,
424 },
425 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
426 .consumer_supplies = vmmc1_consumers,
427};
428
429static struct regulator_consumer_supply vgen_consumers[] = {
430 REGULATOR_SUPPLY("vdd_lcdio", NULL),
431};
432
433static struct regulator_init_data vgen_init = {
434 .constraints = {
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
439 REGULATOR_CHANGE_STATUS,
440 },
441 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
442 .consumer_supplies = vgen_consumers,
443};
444
445static struct regulator_consumer_supply vvib_consumers[] = {
446 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
447};
448
449static struct regulator_init_data vvib_init = {
450 .constraints = {
451 .min_uV = 1300000,
452 .max_uV = 1300000,
453 .apply_uV = 1,
454 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
455 REGULATOR_CHANGE_STATUS,
456 },
457 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
458 .consumer_supplies = vvib_consumers,
459};
460
461static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
462 {
463 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
464 .init_data = &pwgtx_init,
465 }, {
466 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
467 .init_data = &pwgtx_init,
468 }, {
469
470 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
471 .init_data = &gpo_init,
472 }, {
473 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
474 .init_data = &gpo_init,
475 }, {
476 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
477 .init_data = &vmmc2_init,
478 }, {
479 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
480 .init_data = &vmmc1_init,
481 }, {
482 .id = MC13783_REG_VGEN, /* Power LCD */
483 .init_data = &vgen_init,
484 }, {
485 .id = MC13783_REG_VVIB, /* Power CMOS */
486 .init_data = &vvib_init,
487 },
488};
489
490/* MC13783 */
491static struct mc13xxx_platform_data mc13783_pdata = {
492 .regulators = {
493 .regulators = mx31_3ds_regulators,
494 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
495 },
496 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
497};
498
499/* SPI */
500static int spi0_internal_chipselect[] = {
501 MXC_SPI_CS(2),
502};
503
504static const struct spi_imx_master spi0_pdata __initconst = {
505 .chipselect = spi0_internal_chipselect,
506 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
507};
508
509static int spi1_internal_chipselect[] = {
510 MXC_SPI_CS(0),
511 MXC_SPI_CS(2),
512};
513
514static const struct spi_imx_master spi1_pdata __initconst = {
515 .chipselect = spi1_internal_chipselect,
516 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
517};
518
519static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
520 {
521 .modalias = "mc13783",
522 .max_speed_hz = 1000000,
523 .bus_num = 1,
524 .chip_select = 1, /* SS2 */
525 .platform_data = &mc13783_pdata,
526 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
527 .mode = SPI_CS_HIGH,
528 }, {
529 .modalias = "l4f00242t03",
530 .max_speed_hz = 5000000,
531 .bus_num = 0,
532 .chip_select = 0, /* SS2 */
533 .platform_data = &mx31_3ds_l4f00242t03_pdata,
534 },
535};
536
537/*
538 * NAND Flash
539 */
540static const struct mxc_nand_platform_data
541mx31_3ds_nand_board_info __initconst = {
542 .width = 1,
543 .hw_ecc = 1,
544#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
545 .flash_bbt = 1,
546#endif
547};
548
549/*
550 * USB OTG
551 */
552
553#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
554 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
555
556#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
557#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
558
559static int mx31_3ds_usbotg_init(void)
560{
561 int err;
562
563 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
564 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
565 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
566 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
567 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
568 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
569 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
570 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
571 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
572 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
573 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
574 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
575
576 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
577 if (err) {
578 pr_err("Failed to request the USB OTG reset gpio\n");
579 return err;
580 }
581
582 err = gpio_direction_output(USBOTG_RST_B, 0);
583 if (err) {
584 pr_err("Failed to drive the USB OTG reset gpio\n");
585 goto usbotg_free_reset;
586 }
587
588 mdelay(1);
589 gpio_set_value(USBOTG_RST_B, 1);
590 return 0;
591
592usbotg_free_reset:
593 gpio_free(USBOTG_RST_B);
594 return err;
595}
596
597static int mx31_3ds_otg_init(struct platform_device *pdev)
598{
599 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
600}
601
602static int mx31_3ds_host2_init(struct platform_device *pdev)
603{
604 int err;
605
606 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
607 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
608 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
609 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
610 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
611 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
612 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
613 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
614 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
615 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
616 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
617 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
618
619 err = gpio_request(USBH2_RST_B, "usbh2-reset");
620 if (err) {
621 pr_err("Failed to request the USB Host 2 reset gpio\n");
622 return err;
623 }
624
625 err = gpio_direction_output(USBH2_RST_B, 0);
626 if (err) {
627 pr_err("Failed to drive the USB Host 2 reset gpio\n");
628 goto usbotg_free_reset;
629 }
630
631 mdelay(1);
632 gpio_set_value(USBH2_RST_B, 1);
633
634 mdelay(10);
635
636 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
637
638usbotg_free_reset:
639 gpio_free(USBH2_RST_B);
640 return err;
641}
642
643static struct mxc_usbh_platform_data otg_pdata __initdata = {
644 .init = mx31_3ds_otg_init,
645 .portsc = MXC_EHCI_MODE_ULPI,
646};
647
648static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
649 .init = mx31_3ds_host2_init,
650 .portsc = MXC_EHCI_MODE_ULPI,
651};
652
653static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
654 .operating_mode = FSL_USB2_DR_DEVICE,
655 .phy_mode = FSL_USB2_PHY_ULPI,
656};
657
658static int otg_mode_host;
659
660static int __init mx31_3ds_otg_mode(char *options)
661{
662 if (!strcmp(options, "host"))
663 otg_mode_host = 1;
664 else if (!strcmp(options, "device"))
665 otg_mode_host = 0;
666 else
667 pr_info("otg_mode neither \"host\" nor \"device\". "
668 "Defaulting to device\n");
669 return 0;
670}
671__setup("otg_mode=", mx31_3ds_otg_mode);
672
673static const struct imxuart_platform_data uart_pdata __initconst = {
674 .flags = IMXUART_HAVE_RTSCTS,
675};
676
677static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
678 .bitrate = 100000,
679};
680
681static struct platform_device *devices[] __initdata = {
682 &mx31_3ds_ov2640,
683};
684
685static void __init mx31_3ds_init(void)
686{
687 int ret;
688
689 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
690 "mx31_3ds");
691
692 imx31_add_imx_uart0(&uart_pdata);
693 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
694
695 imx31_add_spi_imx1(&spi1_pdata);
696 spi_register_board_info(mx31_3ds_spi_devs,
697 ARRAY_SIZE(mx31_3ds_spi_devs));
698
699 platform_add_devices(devices, ARRAY_SIZE(devices));
700
701 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
702
703 mx31_3ds_usbotg_init();
704 if (otg_mode_host) {
705 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
706 ULPI_OTG_DRVVBUS_EXT);
707 if (otg_pdata.otg)
708 imx31_add_mxc_ehci_otg(&otg_pdata);
709 }
710 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
711 ULPI_OTG_DRVVBUS_EXT);
712 if (usbh2_pdata.otg)
713 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
714
715 if (!otg_mode_host)
716 imx31_add_fsl_usb2_udc(&usbotg_pdata);
717
718 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
719 printk(KERN_WARNING "Init of the debug board failed, all "
720 "devices on the debug board are unusable.\n");
721 imx31_add_imx2_wdt(NULL);
722 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
723 imx31_add_mxc_mmc(0, &sdhc1_pdata);
724
725 imx31_add_spi_imx0(&spi0_pdata);
726 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
727 mxc_register_device(&mx3_fb, &mx3fb_pdata);
728
729 /* CSI */
730 /* Camera power: default - off */
731 ret = gpio_request_array(mx31_3ds_camera_gpios,
732 ARRAY_SIZE(mx31_3ds_camera_gpios));
733 if (ret) {
734 pr_err("Failed to request camera gpios");
735 iclink_ov2640.power = NULL;
736 }
737
738 if (!mx31_3ds_camera_alloc_dma())
739 mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
740 else
741 pr_err("Failed to allocate dma memory for camera");
742}
743
744static void __init mx31_3ds_timer_init(void)
745{
746 mx31_clocks_init(26000000);
747}
748
749static struct sys_timer mx31_3ds_timer = {
750 .init = mx31_3ds_timer_init,
751};
752
753static void __init mx31_3ds_reserve(void)
754{
755 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
756 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
757 MX31_3DS_CAMERA_BUF_SIZE);
758 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
759 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
760}
761
762MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
763 /* Maintainer: Freescale Semiconductor, Inc. */
764 .boot_params = MX3x_PHYS_OFFSET + 0x100,
765 .map_io = mx31_map_io,
766 .init_early = imx31_init_early,
767 .init_irq = mx31_init_irq,
768 .timer = &mx31_3ds_timer,
769 .init_machine = mx31_3ds_init,
770 .reserve = mx31_3ds_reserve,
771MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
deleted file mode 100644
index 3d095d69bc68..000000000000
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ /dev/null
@@ -1,543 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/serial_8250.h>
21#include <linux/gpio.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/time.h>
28#include <asm/memory.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <mach/board-mx31ads.h>
32#include <mach/iomux-mx3.h>
33
34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
35#include <linux/mfd/wm8350/audio.h>
36#include <linux/mfd/wm8350/core.h>
37#include <linux/mfd/wm8350/pmic.h>
38#endif
39
40#include "devices-imx31.h"
41#include "devices.h"
42
43/* PBC Board interrupt status register */
44#define PBC_INTSTATUS 0x000016
45
46/* PBC Board interrupt current status register */
47#define PBC_INTCURR_STATUS 0x000018
48
49/* PBC Interrupt mask register set address */
50#define PBC_INTMASK_SET 0x00001A
51
52/* PBC Interrupt mask register clear address */
53#define PBC_INTMASK_CLEAR 0x00001C
54
55/* External UART A */
56#define PBC_SC16C652_UARTA 0x010000
57
58/* External UART B */
59#define PBC_SC16C652_UARTB 0x010010
60
61#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
62#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
63#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
64#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
65
66#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
67
68#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
70
71#define MXC_MAX_EXP_IO_LINES 16
72
73/*
74 * The serial port definition structure.
75 */
76static struct plat_serial8250_port serial_platform_data[] = {
77 {
78 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
79 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
80 .irq = EXPIO_INT_XUART_INTA,
81 .uartclk = 14745600,
82 .regshift = 0,
83 .iotype = UPIO_MEM,
84 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
85 }, {
86 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
87 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
88 .irq = EXPIO_INT_XUART_INTB,
89 .uartclk = 14745600,
90 .regshift = 0,
91 .iotype = UPIO_MEM,
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
93 },
94 {},
95};
96
97static struct platform_device serial_device = {
98 .name = "serial8250",
99 .id = 0,
100 .dev = {
101 .platform_data = serial_platform_data,
102 },
103};
104
105static int __init mxc_init_extuart(void)
106{
107 return platform_device_register(&serial_device);
108}
109
110static const struct imxuart_platform_data uart_pdata __initconst = {
111 .flags = IMXUART_HAVE_RTSCTS,
112};
113
114static unsigned int uart_pins[] = {
115 MX31_PIN_CTS1__CTS1,
116 MX31_PIN_RTS1__RTS1,
117 MX31_PIN_TXD1__TXD1,
118 MX31_PIN_RXD1__RXD1
119};
120
121static inline void mxc_init_imx_uart(void)
122{
123 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
124 imx31_add_imx_uart0(&uart_pdata);
125}
126
127static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
128{
129 u32 imr_val;
130 u32 int_valid;
131 u32 expio_irq;
132
133 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
134 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
135
136 expio_irq = MXC_EXP_IO_BASE;
137 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
138 if ((int_valid & 1) == 0)
139 continue;
140
141 generic_handle_irq(expio_irq);
142 }
143}
144
145/*
146 * Disable an expio pin's interrupt by setting the bit in the imr.
147 * @param d an expio virtual irq description
148 */
149static void expio_mask_irq(struct irq_data *d)
150{
151 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
152 /* mask the interrupt */
153 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
154 __raw_readw(PBC_INTMASK_CLEAR_REG);
155}
156
157/*
158 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
159 * @param d an expio virtual irq description
160 */
161static void expio_ack_irq(struct irq_data *d)
162{
163 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
164 /* clear the interrupt status */
165 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
166}
167
168/*
169 * Enable a expio pin's interrupt by clearing the bit in the imr.
170 * @param d an expio virtual irq description
171 */
172static void expio_unmask_irq(struct irq_data *d)
173{
174 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
175 /* unmask the interrupt */
176 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
177}
178
179static struct irq_chip expio_irq_chip = {
180 .name = "EXPIO(CPLD)",
181 .irq_ack = expio_ack_irq,
182 .irq_mask = expio_mask_irq,
183 .irq_unmask = expio_unmask_irq,
184};
185
186static void __init mx31ads_init_expio(void)
187{
188 int i;
189
190 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
191
192 /*
193 * Configure INT line as GPIO input
194 */
195 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
196
197 /* disable the interrupt and clear the status */
198 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
201 i++) {
202 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
203 set_irq_flags(i, IRQF_VALID);
204 }
205 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
206 irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
207}
208
209#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
210/* This section defines setup for the Wolfson Microelectronics
211 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
212 * regulator definitions may be shared with them, but for now they can
213 * only be used with this board so would generate warnings about
214 * unused statics and some of the configuration is specific to this
215 * module.
216 */
217
218/* CPU */
219static struct regulator_consumer_supply sw1a_consumers[] = {
220 {
221 .supply = "cpu_vcc",
222 }
223};
224
225static struct regulator_init_data sw1a_data = {
226 .constraints = {
227 .name = "SW1A",
228 .min_uV = 1275000,
229 .max_uV = 1600000,
230 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
231 REGULATOR_CHANGE_MODE,
232 .valid_modes_mask = REGULATOR_MODE_NORMAL |
233 REGULATOR_MODE_FAST,
234 .state_mem = {
235 .uV = 1400000,
236 .mode = REGULATOR_MODE_NORMAL,
237 .enabled = 1,
238 },
239 .initial_state = PM_SUSPEND_MEM,
240 .always_on = 1,
241 .boot_on = 1,
242 },
243 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
244 .consumer_supplies = sw1a_consumers,
245};
246
247/* System IO - High */
248static struct regulator_init_data viohi_data = {
249 .constraints = {
250 .name = "VIOHO",
251 .min_uV = 2800000,
252 .max_uV = 2800000,
253 .state_mem = {
254 .uV = 2800000,
255 .mode = REGULATOR_MODE_NORMAL,
256 .enabled = 1,
257 },
258 .initial_state = PM_SUSPEND_MEM,
259 .always_on = 1,
260 .boot_on = 1,
261 },
262};
263
264/* System IO - Low */
265static struct regulator_init_data violo_data = {
266 .constraints = {
267 .name = "VIOLO",
268 .min_uV = 1800000,
269 .max_uV = 1800000,
270 .state_mem = {
271 .uV = 1800000,
272 .mode = REGULATOR_MODE_NORMAL,
273 .enabled = 1,
274 },
275 .initial_state = PM_SUSPEND_MEM,
276 .always_on = 1,
277 .boot_on = 1,
278 },
279};
280
281/* DDR RAM */
282static struct regulator_init_data sw2a_data = {
283 .constraints = {
284 .name = "SW2A",
285 .min_uV = 1800000,
286 .max_uV = 1800000,
287 .valid_modes_mask = REGULATOR_MODE_NORMAL,
288 .state_mem = {
289 .uV = 1800000,
290 .mode = REGULATOR_MODE_NORMAL,
291 .enabled = 1,
292 },
293 .state_disk = {
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 0,
296 },
297 .always_on = 1,
298 .boot_on = 1,
299 .initial_state = PM_SUSPEND_MEM,
300 },
301};
302
303static struct regulator_init_data ldo1_data = {
304 .constraints = {
305 .name = "VCAM/VMMC1/VMMC2",
306 .min_uV = 2800000,
307 .max_uV = 2800000,
308 .valid_modes_mask = REGULATOR_MODE_NORMAL,
309 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
310 .apply_uV = 1,
311 },
312};
313
314static struct regulator_consumer_supply ldo2_consumers[] = {
315 { .supply = "AVDD", .dev_name = "1-001a" },
316 { .supply = "HPVDD", .dev_name = "1-001a" },
317};
318
319/* CODEC and SIM */
320static struct regulator_init_data ldo2_data = {
321 .constraints = {
322 .name = "VESIM/VSIM/AVDD",
323 .min_uV = 3300000,
324 .max_uV = 3300000,
325 .valid_modes_mask = REGULATOR_MODE_NORMAL,
326 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
327 .apply_uV = 1,
328 },
329 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
330 .consumer_supplies = ldo2_consumers,
331};
332
333/* General */
334static struct regulator_init_data vdig_data = {
335 .constraints = {
336 .name = "VDIG",
337 .min_uV = 1500000,
338 .max_uV = 1500000,
339 .valid_modes_mask = REGULATOR_MODE_NORMAL,
340 .apply_uV = 1,
341 .always_on = 1,
342 .boot_on = 1,
343 },
344};
345
346/* Tranceivers */
347static struct regulator_init_data ldo4_data = {
348 .constraints = {
349 .name = "VRF1/CVDD_2.775",
350 .min_uV = 2500000,
351 .max_uV = 2500000,
352 .valid_modes_mask = REGULATOR_MODE_NORMAL,
353 .apply_uV = 1,
354 .always_on = 1,
355 .boot_on = 1,
356 },
357};
358
359static struct wm8350_led_platform_data wm8350_led_data = {
360 .name = "wm8350:white",
361 .default_trigger = "heartbeat",
362 .max_uA = 27899,
363};
364
365static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
366 .vmid_discharge_msecs = 1000,
367 .drain_msecs = 30,
368 .cap_discharge_msecs = 700,
369 .vmid_charge_msecs = 700,
370 .vmid_s_curve = WM8350_S_CURVE_SLOW,
371 .dis_out4 = WM8350_DISCHARGE_SLOW,
372 .dis_out3 = WM8350_DISCHARGE_SLOW,
373 .dis_out2 = WM8350_DISCHARGE_SLOW,
374 .dis_out1 = WM8350_DISCHARGE_SLOW,
375 .vroi_out4 = WM8350_TIE_OFF_500R,
376 .vroi_out3 = WM8350_TIE_OFF_500R,
377 .vroi_out2 = WM8350_TIE_OFF_500R,
378 .vroi_out1 = WM8350_TIE_OFF_500R,
379 .vroi_enable = 0,
380 .codec_current_on = WM8350_CODEC_ISEL_1_0,
381 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
382 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
383};
384
385static int mx31_wm8350_init(struct wm8350 *wm8350)
386{
387 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
388 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
389 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
390 WM8350_GPIO_DEBOUNCE_ON);
391
392 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
393 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
394 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
395 WM8350_GPIO_DEBOUNCE_ON);
396
397 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
398 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
399 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
400 WM8350_GPIO_DEBOUNCE_OFF);
401
402 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
403 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
404 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
405 WM8350_GPIO_DEBOUNCE_OFF);
406
407 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
408 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
409 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
410 WM8350_GPIO_DEBOUNCE_OFF);
411
412 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
413 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
414 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
415 WM8350_GPIO_DEBOUNCE_OFF);
416
417 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
418 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
419 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_OFF);
421
422 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
423 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
424 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
425 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
426 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
427 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
428 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
429 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
430
431 /* LEDs */
432 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
433 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
434 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
435 WM8350_ISINK_FLASH_DISABLE,
436 WM8350_ISINK_FLASH_TRIG_BIT,
437 WM8350_ISINK_FLASH_DUR_32MS,
438 WM8350_ISINK_FLASH_ON_INSTANT,
439 WM8350_ISINK_FLASH_OFF_INSTANT,
440 WM8350_ISINK_FLASH_MODE_EN);
441 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
442 WM8350_ISINK_MODE_BOOST,
443 WM8350_ISINK_ILIM_NORMAL,
444 WM8350_DC5_RMP_20V,
445 WM8350_DC5_FBSRC_ISINKA);
446 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
447 &wm8350_led_data);
448
449 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
450
451 regulator_has_full_constraints();
452
453 return 0;
454}
455
456static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
457 .init = mx31_wm8350_init,
458 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
459};
460#endif
461
462static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
463#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
464 {
465 I2C_BOARD_INFO("wm8350", 0x1a),
466 .platform_data = &mx31_wm8350_pdata,
467 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
468 },
469#endif
470};
471
472static void mxc_init_i2c(void)
473{
474 i2c_register_board_info(1, mx31ads_i2c1_devices,
475 ARRAY_SIZE(mx31ads_i2c1_devices));
476
477 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
478 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
479
480 imx31_add_imx_i2c1(NULL);
481}
482
483static unsigned int ssi_pins[] = {
484 MX31_PIN_SFS5__SFS5,
485 MX31_PIN_SCK5__SCK5,
486 MX31_PIN_SRXD5__SRXD5,
487 MX31_PIN_STXD5__STXD5,
488};
489
490static void mxc_init_audio(void)
491{
492 imx31_add_imx_ssi(0, NULL);
493 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
494}
495
496/* static mappings */
497static struct map_desc mx31ads_io_desc[] __initdata = {
498 {
499 .virtual = MX31_CS4_BASE_ADDR_VIRT,
500 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
501 .length = MX31_CS4_SIZE / 2,
502 .type = MT_DEVICE
503 },
504};
505
506static void __init mx31ads_map_io(void)
507{
508 mx31_map_io();
509 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
510}
511
512static void __init mx31ads_init_irq(void)
513{
514 mx31_init_irq();
515 mx31ads_init_expio();
516}
517
518static void __init mx31ads_init(void)
519{
520 mxc_init_extuart();
521 mxc_init_imx_uart();
522 mxc_init_i2c();
523 mxc_init_audio();
524}
525
526static void __init mx31ads_timer_init(void)
527{
528 mx31_clocks_init(26000000);
529}
530
531static struct sys_timer mx31ads_timer = {
532 .init = mx31ads_timer_init,
533};
534
535MACHINE_START(MX31ADS, "Freescale MX31ADS")
536 /* Maintainer: Freescale Semiconductor, Inc. */
537 .boot_params = MX3x_PHYS_OFFSET + 0x100,
538 .map_io = mx31ads_map_io,
539 .init_early = imx31_init_early,
540 .init_irq = mx31ads_init_irq,
541 .timer = &mx31ads_timer,
542 .init_machine = mx31ads_init,
543MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
deleted file mode 100644
index ed95745163b8..000000000000
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ /dev/null
@@ -1,303 +0,0 @@
1/*
2 * LILLY-1131 module support
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * based on code for other MX31 boards,
7 *
8 * Copyright 2005-2007 Freescale Semiconductor
9 * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
10 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/clk.h>
26#include <linux/gpio.h>
27#include <linux/delay.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/smsc911x.h>
31#include <linux/mtd/physmap.h>
32#include <linux/spi/spi.h>
33#include <linux/mfd/mc13783.h>
34#include <linux/usb/otg.h>
35#include <linux/usb/ulpi.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/mach/map.h>
41
42#include <mach/hardware.h>
43#include <mach/common.h>
44#include <mach/iomux-mx3.h>
45#include <mach/board-mx31lilly.h>
46#include <mach/ulpi.h>
47
48#include "devices-imx31.h"
49#include "devices.h"
50
51/*
52 * This file contains module-specific initialization routines for LILLY-1131.
53 * Initialization of peripherals found on the baseboard is implemented in the
54 * appropriate baseboard support code.
55 */
56
57/* SMSC ethernet support */
58
59static struct resource smsc91x_resources[] = {
60 {
61 .start = MX31_CS4_BASE_ADDR,
62 .end = MX31_CS4_BASE_ADDR + 0xffff,
63 .flags = IORESOURCE_MEM,
64 },
65 {
66 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
67 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
68 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
69 }
70};
71
72static struct smsc911x_platform_config smsc911x_config = {
73 .phy_interface = PHY_INTERFACE_MODE_MII,
74 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
75 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
76 .flags = SMSC911X_USE_32BIT |
77 SMSC911X_SAVE_MAC_ADDRESS |
78 SMSC911X_FORCE_INTERNAL_PHY,
79};
80
81static struct platform_device smsc91x_device = {
82 .name = "smsc911x",
83 .id = -1,
84 .num_resources = ARRAY_SIZE(smsc91x_resources),
85 .resource = smsc91x_resources,
86 .dev = {
87 .platform_data = &smsc911x_config,
88 }
89};
90
91/* NOR flash */
92static struct physmap_flash_data nor_flash_data = {
93 .width = 2,
94};
95
96static struct resource nor_flash_resource = {
97 .start = 0xa0000000,
98 .end = 0xa1ffffff,
99 .flags = IORESOURCE_MEM,
100};
101
102static struct platform_device physmap_flash_device = {
103 .name = "physmap-flash",
104 .id = 0,
105 .dev = {
106 .platform_data = &nor_flash_data,
107 },
108 .resource = &nor_flash_resource,
109 .num_resources = 1,
110};
111
112/* USB */
113
114#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
115 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
116
117static int usbh1_init(struct platform_device *pdev)
118{
119 int pins[] = {
120 MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
121 MX31_PIN_CSPI1_MISO__USBH1_RXDP,
122 MX31_PIN_CSPI1_SS0__USBH1_TXDM,
123 MX31_PIN_CSPI1_SS1__USBH1_TXDP,
124 MX31_PIN_CSPI1_SS2__USBH1_RCV,
125 MX31_PIN_CSPI1_SCLK__USBH1_OEB,
126 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
127 };
128
129 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
130
131 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
132 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
133 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
134 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
135 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
136 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
137 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
138
139 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
140
141 mdelay(10);
142
143 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
144 MXC_EHCI_INTERFACE_SINGLE_UNI);
145}
146
147static int usbh2_init(struct platform_device *pdev)
148{
149 int pins[] = {
150 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
151 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
152 MX31_PIN_USBH2_CLK__USBH2_CLK,
153 MX31_PIN_USBH2_DIR__USBH2_DIR,
154 MX31_PIN_USBH2_NXT__USBH2_NXT,
155 MX31_PIN_USBH2_STP__USBH2_STP,
156 };
157
158 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
159
160 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
165 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
166 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
167 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
168 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
169 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
170 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
171 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
172
173 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
174
175 /* chip select */
176 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
177 "USBH2_CS");
178 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
179 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
180
181 mdelay(10);
182
183 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
184}
185
186static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
187 .init = usbh1_init,
188 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
189};
190
191static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
192 .init = usbh2_init,
193 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
194};
195
196static void lilly1131_usb_init(void)
197{
198 imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
199
200 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
201 ULPI_OTG_DRVVBUS_EXT);
202 if (usbh2_pdata.otg)
203 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
204}
205
206/* SPI */
207
208static int spi_internal_chipselect[] = {
209 MXC_SPI_CS(0),
210 MXC_SPI_CS(1),
211 MXC_SPI_CS(2),
212};
213
214static const struct spi_imx_master spi0_pdata __initconst = {
215 .chipselect = spi_internal_chipselect,
216 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
217};
218
219static const struct spi_imx_master spi1_pdata __initconst = {
220 .chipselect = spi_internal_chipselect,
221 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
222};
223
224static struct mc13xxx_platform_data mc13783_pdata __initdata = {
225 .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
226};
227
228static struct spi_board_info mc13783_dev __initdata = {
229 .modalias = "mc13783",
230 .max_speed_hz = 1000000,
231 .bus_num = 1,
232 .chip_select = 0,
233 .platform_data = &mc13783_pdata,
234 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
235};
236
237static struct platform_device *devices[] __initdata = {
238 &smsc91x_device,
239 &physmap_flash_device,
240};
241
242static int mx31lilly_baseboard;
243core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
244
245static void __init mx31lilly_board_init(void)
246{
247 switch (mx31lilly_baseboard) {
248 case MX31LILLY_NOBOARD:
249 break;
250 case MX31LILLY_DB:
251 mx31lilly_db_init();
252 break;
253 default:
254 printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n",
255 mx31lilly_baseboard);
256 }
257
258 mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
259
260 /* SPI */
261 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
262 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
263 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
264 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
265 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
266 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
267 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
268
269 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
270 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
271 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
272 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
273 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
274 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
275 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
276
277 imx31_add_spi_imx0(&spi0_pdata);
278 imx31_add_spi_imx1(&spi1_pdata);
279 spi_register_board_info(&mc13783_dev, 1);
280
281 platform_add_devices(devices, ARRAY_SIZE(devices));
282
283 /* USB */
284 lilly1131_usb_init();
285}
286
287static void __init mx31lilly_timer_init(void)
288{
289 mx31_clocks_init(26000000);
290}
291
292static struct sys_timer mx31lilly_timer = {
293 .init = mx31lilly_timer_init,
294};
295
296MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
297 .boot_params = MX3x_PHYS_OFFSET + 0x100,
298 .map_io = mx31_map_io,
299 .init_early = imx31_init_early,
300 .init_irq = mx31_init_irq,
301 .timer = &mx31lilly_timer,
302 .init_machine = mx31lilly_board_init,
303MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
deleted file mode 100644
index 24a21a384bf1..000000000000
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/memory.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/smsc911x.h>
25#include <linux/mfd/mc13783.h>
26#include <linux/spi/spi.h>
27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
29#include <linux/mtd/physmap.h>
30#include <linux/delay.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36#include <asm/page.h>
37#include <asm/setup.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/board-mx31lite.h>
42#include <mach/iomux-mx3.h>
43#include <mach/irqs.h>
44#include <mach/ulpi.h>
45
46#include "devices-imx31.h"
47#include "devices.h"
48
49/*
50 * This file contains the module-specific initialization routines.
51 */
52
53static unsigned int mx31lite_pins[] = {
54 /* LAN9117 IRQ pin */
55 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
56 /* SPI 1 */
57 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI,
59 MX31_PIN_CSPI2_MISO__MISO,
60 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
61 MX31_PIN_CSPI2_SS0__SS0,
62 MX31_PIN_CSPI2_SS1__SS1,
63 MX31_PIN_CSPI2_SS2__SS2,
64};
65
66static const struct mxc_nand_platform_data
67mx31lite_nand_board_info __initconst = {
68 .width = 1,
69 .hw_ecc = 1,
70};
71
72static struct smsc911x_platform_config smsc911x_config = {
73 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
74 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
75 .flags = SMSC911X_USE_16BIT,
76};
77
78static struct resource smsc911x_resources[] = {
79 {
80 .start = MX31_CS4_BASE_ADDR,
81 .end = MX31_CS4_BASE_ADDR + 0x100,
82 .flags = IORESOURCE_MEM,
83 }, {
84 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
85 .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
86 .flags = IORESOURCE_IRQ,
87 },
88};
89
90static struct platform_device smsc911x_device = {
91 .name = "smsc911x",
92 .id = -1,
93 .num_resources = ARRAY_SIZE(smsc911x_resources),
94 .resource = smsc911x_resources,
95 .dev = {
96 .platform_data = &smsc911x_config,
97 },
98};
99
100/*
101 * SPI
102 *
103 * The MC13783 is the only hard-wired SPI device on the module.
104 */
105
106static int spi_internal_chipselect[] = {
107 MXC_SPI_CS(0),
108};
109
110static const struct spi_imx_master spi1_pdata __initconst = {
111 .chipselect = spi_internal_chipselect,
112 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
113};
114
115static struct mc13xxx_platform_data mc13783_pdata __initdata = {
116 .flags = MC13XXX_USE_RTC |
117 MC13XXX_USE_REGULATOR,
118};
119
120static struct spi_board_info mc13783_spi_dev __initdata = {
121 .modalias = "mc13783",
122 .max_speed_hz = 1000000,
123 .bus_num = 1,
124 .chip_select = 0,
125 .platform_data = &mc13783_pdata,
126 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
127};
128
129/*
130 * USB
131 */
132
133#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
135
136static int usbh2_init(struct platform_device *pdev)
137{
138 int pins[] = {
139 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
140 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
141 MX31_PIN_USBH2_CLK__USBH2_CLK,
142 MX31_PIN_USBH2_DIR__USBH2_DIR,
143 MX31_PIN_USBH2_NXT__USBH2_NXT,
144 MX31_PIN_USBH2_STP__USBH2_STP,
145 };
146
147 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
148
149 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
152 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
153 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
161
162 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
163
164 /* chip select */
165 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
166 "USBH2_CS");
167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
169
170 mdelay(10);
171
172 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
173}
174
175static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
176 .init = usbh2_init,
177 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
178};
179
180/*
181 * NOR flash
182 */
183
184static struct physmap_flash_data nor_flash_data = {
185 .width = 2,
186};
187
188static struct resource nor_flash_resource = {
189 .start = 0xa0000000,
190 .end = 0xa1ffffff,
191 .flags = IORESOURCE_MEM,
192};
193
194static struct platform_device physmap_flash_device = {
195 .name = "physmap-flash",
196 .id = 0,
197 .dev = {
198 .platform_data = &nor_flash_data,
199 },
200 .resource = &nor_flash_resource,
201 .num_resources = 1,
202};
203
204
205
206/*
207 * This structure defines the MX31 memory map.
208 */
209static struct map_desc mx31lite_io_desc[] __initdata = {
210 {
211 .virtual = MX31_CS4_BASE_ADDR_VIRT,
212 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
213 .length = MX31_CS4_SIZE,
214 .type = MT_DEVICE
215 }
216};
217
218/*
219 * Set up static virtual mappings.
220 */
221void __init mx31lite_map_io(void)
222{
223 mx31_map_io();
224 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
225}
226
227static int mx31lite_baseboard;
228core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
229
230static void __init mx31lite_init(void)
231{
232 int ret;
233
234 switch (mx31lite_baseboard) {
235 case MX31LITE_NOBOARD:
236 break;
237 case MX31LITE_DB:
238 mx31lite_db_init();
239 break;
240 default:
241 printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
242 mx31lite_baseboard);
243 }
244
245 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
246 "mx31lite");
247
248 /* NOR and NAND flash */
249 platform_device_register(&physmap_flash_device);
250 imx31_add_mxc_nand(&mx31lite_nand_board_info);
251
252 imx31_add_spi_imx1(&spi1_pdata);
253 spi_register_board_info(&mc13783_spi_dev, 1);
254
255 /* USB */
256 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
257 ULPI_OTG_DRVVBUS_EXT);
258 if (usbh2_pdata.otg)
259 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
260
261 /* SMSC9117 IRQ pin */
262 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
263 if (ret)
264 pr_warning("could not get LAN irq gpio\n");
265 else {
266 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
267 platform_device_register(&smsc911x_device);
268 }
269}
270
271static void __init mx31lite_timer_init(void)
272{
273 mx31_clocks_init(26000000);
274}
275
276struct sys_timer mx31lite_timer = {
277 .init = mx31lite_timer_init,
278};
279
280MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
281 /* Maintainer: Freescale Semiconductor, Inc. */
282 .boot_params = MX3x_PHYS_OFFSET + 0x100,
283 .map_io = mx31lite_map_io,
284 .init_early = imx31_init_early,
285 .init_irq = mx31_init_irq,
286 .timer = &mx31lite_timer,
287 .init_machine = mx31lite_init,
288MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
deleted file mode 100644
index 3a021b01161d..000000000000
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ /dev/null
@@ -1,576 +0,0 @@
1/*
2 * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/gfp.h>
18#include <linux/gpio.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/leds.h>
22#include <linux/memory.h>
23#include <linux/mtd/physmap.h>
24#include <linux/mtd/partitions.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/machine.h>
27#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h>
29#include <linux/types.h>
30
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38#include <mach/board-mx31moboard.h>
39#include <mach/common.h>
40#include <mach/hardware.h>
41#include <mach/iomux-mx3.h>
42#include <mach/ipu.h>
43#include <mach/mx3_camera.h>
44#include <mach/spi.h>
45#include <mach/ulpi.h>
46
47#include "devices-imx31.h"
48#include "devices.h"
49
50static unsigned int moboard_pins[] = {
51 /* UART0 */
52 MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
53 MX31_PIN_CTS1__GPIO2_7,
54 /* UART4 */
55 MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
56 MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
57 /* I2C0 */
58 MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
59 /* I2C1 */
60 MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
61 /* SDHC1 */
62 MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
63 MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
64 MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
65 MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
66 /* USB reset */
67 MX31_PIN_GPIO1_0__GPIO1_0,
68 /* USB OTG */
69 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
70 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
71 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
72 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
73 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
74 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
75 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
76 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
77 MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
78 MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
79 MX31_PIN_USB_OC__GPIO1_30,
80 /* USB H2 */
81 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
82 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
83 MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
84 MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
85 MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
86 MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
87 MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
88 MX31_PIN_SCK6__GPIO1_25,
89 /* LEDs */
90 MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
91 MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
92 /* SPI1 */
93 MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
94 MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
95 MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
96 /* Atlas IRQ */
97 MX31_PIN_GPIO1_3__GPIO1_3,
98 /* SPI2 */
99 MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
100 MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
101 MX31_PIN_CSPI2_SS1__CSPI3_SS1,
102};
103
104static struct physmap_flash_data mx31moboard_flash_data = {
105 .width = 2,
106};
107
108static struct resource mx31moboard_flash_resource = {
109 .start = 0xa0000000,
110 .end = 0xa1ffffff,
111 .flags = IORESOURCE_MEM,
112};
113
114static struct platform_device mx31moboard_flash = {
115 .name = "physmap-flash",
116 .id = 0,
117 .dev = {
118 .platform_data = &mx31moboard_flash_data,
119 },
120 .resource = &mx31moboard_flash_resource,
121 .num_resources = 1,
122};
123
124static int moboard_uart0_init(struct platform_device *pdev)
125{
126 int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
127 if (ret)
128 return ret;
129
130 ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
131 if (ret)
132 gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
133
134 return ret;
135}
136
137static void moboard_uart0_exit(struct platform_device *pdev)
138{
139 gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
140}
141
142static const struct imxuart_platform_data uart0_pdata __initconst = {
143 .init = moboard_uart0_init,
144 .exit = moboard_uart0_exit,
145};
146
147static const struct imxuart_platform_data uart4_pdata __initconst = {
148 .flags = IMXUART_HAVE_RTSCTS,
149};
150
151static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
152 .bitrate = 400000,
153};
154
155static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
156 .bitrate = 100000,
157};
158
159static int moboard_spi1_cs[] = {
160 MXC_SPI_CS(0),
161 MXC_SPI_CS(2),
162};
163
164static const struct spi_imx_master moboard_spi1_pdata __initconst = {
165 .chipselect = moboard_spi1_cs,
166 .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
167};
168
169static struct regulator_consumer_supply sdhc_consumers[] = {
170 {
171 .dev_name = "mxc-mmc.0",
172 .supply = "sdhc0_vcc",
173 },
174 {
175 .dev_name = "mxc-mmc.1",
176 .supply = "sdhc1_vcc",
177 },
178};
179
180static struct regulator_init_data sdhc_vreg_data = {
181 .constraints = {
182 .min_uV = 2700000,
183 .max_uV = 3000000,
184 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
185 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
186 .valid_modes_mask = REGULATOR_MODE_NORMAL |
187 REGULATOR_MODE_FAST,
188 .always_on = 0,
189 .boot_on = 1,
190 },
191 .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
192 .consumer_supplies = sdhc_consumers,
193};
194
195static struct regulator_consumer_supply cam_consumers[] = {
196 {
197 .dev = &mx3_camera.dev,
198 .supply = "cam_vcc",
199 },
200};
201
202static struct regulator_init_data cam_vreg_data = {
203 .constraints = {
204 .min_uV = 2700000,
205 .max_uV = 3000000,
206 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
207 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
208 .valid_modes_mask = REGULATOR_MODE_NORMAL |
209 REGULATOR_MODE_FAST,
210 .always_on = 0,
211 .boot_on = 1,
212 },
213 .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
214 .consumer_supplies = cam_consumers,
215};
216
217static struct mc13xxx_regulator_init_data moboard_regulators[] = {
218 {
219 .id = MC13783_REG_VMMC1,
220 .init_data = &sdhc_vreg_data,
221 },
222 {
223 .id = MC13783_REG_VCAM,
224 .init_data = &cam_vreg_data,
225 },
226};
227
228static struct mc13783_led_platform_data moboard_led[] = {
229 {
230 .id = MC13783_LED_R1,
231 .name = "coreboard-led-4:red",
232 .max_current = 2,
233 },
234 {
235 .id = MC13783_LED_G1,
236 .name = "coreboard-led-4:green",
237 .max_current = 2,
238 },
239 {
240 .id = MC13783_LED_B1,
241 .name = "coreboard-led-4:blue",
242 .max_current = 2,
243 },
244 {
245 .id = MC13783_LED_R2,
246 .name = "coreboard-led-5:red",
247 .max_current = 3,
248 },
249 {
250 .id = MC13783_LED_G2,
251 .name = "coreboard-led-5:green",
252 .max_current = 3,
253 },
254 {
255 .id = MC13783_LED_B2,
256 .name = "coreboard-led-5:blue",
257 .max_current = 3,
258 },
259};
260
261static struct mc13783_leds_platform_data moboard_leds = {
262 .num_leds = ARRAY_SIZE(moboard_led),
263 .led = moboard_led,
264 .flags = MC13783_LED_SLEWLIMTC,
265 .abmode = MC13783_LED_AB_DISABLED,
266 .tc1_period = MC13783_LED_PERIOD_10MS,
267 .tc2_period = MC13783_LED_PERIOD_10MS,
268};
269
270static struct mc13xxx_platform_data moboard_pmic = {
271 .regulators = {
272 .regulators = moboard_regulators,
273 .num_regulators = ARRAY_SIZE(moboard_regulators),
274 },
275 .leds = &moboard_leds,
276 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
277 MC13XXX_USE_ADC | MC13XXX_USE_LED,
278};
279
280static struct spi_board_info moboard_spi_board_info[] __initdata = {
281 {
282 .modalias = "mc13783",
283 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
284 .max_speed_hz = 300000,
285 .bus_num = 1,
286 .chip_select = 0,
287 .platform_data = &moboard_pmic,
288 .mode = SPI_CS_HIGH,
289 },
290};
291
292static int moboard_spi2_cs[] = {
293 MXC_SPI_CS(1),
294};
295
296static const struct spi_imx_master moboard_spi2_pdata __initconst = {
297 .chipselect = moboard_spi2_cs,
298 .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
299};
300
301#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
302#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
303
304static int moboard_sdhc1_get_ro(struct device *dev)
305{
306 return !gpio_get_value(SDHC1_WP);
307}
308
309static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
310 void *data)
311{
312 int ret;
313
314 ret = gpio_request(SDHC1_CD, "sdhc-detect");
315 if (ret)
316 return ret;
317
318 gpio_direction_input(SDHC1_CD);
319
320 ret = gpio_request(SDHC1_WP, "sdhc-wp");
321 if (ret)
322 goto err_gpio_free;
323 gpio_direction_input(SDHC1_WP);
324
325 ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
326 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
327 "sdhc1-card-detect", data);
328 if (ret)
329 goto err_gpio_free_2;
330
331 return 0;
332
333err_gpio_free_2:
334 gpio_free(SDHC1_WP);
335err_gpio_free:
336 gpio_free(SDHC1_CD);
337
338 return ret;
339}
340
341static void moboard_sdhc1_exit(struct device *dev, void *data)
342{
343 free_irq(gpio_to_irq(SDHC1_CD), data);
344 gpio_free(SDHC1_WP);
345 gpio_free(SDHC1_CD);
346}
347
348static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
349 .get_ro = moboard_sdhc1_get_ro,
350 .init = moboard_sdhc1_init,
351 .exit = moboard_sdhc1_exit,
352};
353
354/*
355 * this pin is dedicated for all mx31moboard systems, so we do it here
356 */
357#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
358#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
359 PAD_CTL_ODE_CMOS)
360
361#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
362#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
363
364static void usb_xcvr_reset(void)
365{
366 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
367 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
368 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
369 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
370 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
371 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
372 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
373 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
374 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
375 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
376 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
377 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
378
379 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
380 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
381 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
382 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
383 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
384 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
385 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
386 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
387 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
388 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
389 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
390 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
391 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
392
393 gpio_request(OTG_EN_B, "usb-udc-en");
394 gpio_direction_output(OTG_EN_B, 0);
395 gpio_request(USBH2_EN_B, "usbh2-en");
396 gpio_direction_output(USBH2_EN_B, 0);
397
398 gpio_request(USB_RESET_B, "usb-reset");
399 gpio_direction_output(USB_RESET_B, 0);
400 mdelay(1);
401 gpio_set_value(USB_RESET_B, 1);
402 mdelay(1);
403}
404
405static int moboard_usbh2_init_hw(struct platform_device *pdev)
406{
407 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
408}
409
410static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
411 .init = moboard_usbh2_init_hw,
412 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
413};
414
415static int __init moboard_usbh2_init(void)
416{
417 struct platform_device *pdev;
418
419 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
420 ULPI_OTG_DRVVBUS_EXT);
421 if (!usbh2_pdata.otg)
422 return -ENODEV;
423
424 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
425 if (IS_ERR(pdev))
426 return PTR_ERR(pdev);
427
428 return 0;
429}
430
431static struct gpio_led mx31moboard_leds[] = {
432 {
433 .name = "coreboard-led-0:red:running",
434 .default_trigger = "heartbeat",
435 .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
436 }, {
437 .name = "coreboard-led-1:red",
438 .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
439 }, {
440 .name = "coreboard-led-2:red",
441 .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
442 }, {
443 .name = "coreboard-led-3:red",
444 .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
445 },
446};
447
448static struct gpio_led_platform_data mx31moboard_led_pdata = {
449 .num_leds = ARRAY_SIZE(mx31moboard_leds),
450 .leds = mx31moboard_leds,
451};
452
453static struct platform_device mx31moboard_leds_device = {
454 .name = "leds-gpio",
455 .id = -1,
456 .dev = {
457 .platform_data = &mx31moboard_led_pdata,
458 },
459};
460
461static struct ipu_platform_data mx3_ipu_data = {
462 .irq_base = MXC_IPU_IRQ_START,
463};
464
465static struct platform_device *devices[] __initdata = {
466 &mx31moboard_flash,
467 &mx31moboard_leds_device,
468};
469
470static struct mx3_camera_pdata camera_pdata = {
471 .dma_dev = &mx3_ipu.dev,
472 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
473 .mclk_10khz = 4800,
474};
475
476#define CAMERA_BUF_SIZE (4*1024*1024)
477
478static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
479{
480 dma_addr_t dma_handle;
481 void *buf;
482 int dma;
483
484 if (buf_size < 2 * 1024 * 1024)
485 return -EINVAL;
486
487 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
488 if (!buf) {
489 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
490 return -ENOMEM;
491 }
492
493 memset(buf, 0, buf_size);
494
495 dma = dma_declare_coherent_memory(&mx3_camera.dev,
496 dma_handle, dma_handle, buf_size,
497 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
498
499 /* The way we call dma_declare_coherent_memory only a malloc can fail */
500 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
501}
502
503static int mx31moboard_baseboard;
504core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
505
506/*
507 * Board specific initialization.
508 */
509static void __init mx31moboard_init(void)
510{
511 mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
512 "moboard");
513
514 platform_add_devices(devices, ARRAY_SIZE(devices));
515
516 imx31_add_imx_uart0(&uart0_pdata);
517 imx31_add_imx_uart4(&uart4_pdata);
518
519 imx31_add_imx_i2c0(&moboard_i2c0_data);
520 imx31_add_imx_i2c1(&moboard_i2c1_data);
521
522 imx31_add_spi_imx1(&moboard_spi1_pdata);
523 imx31_add_spi_imx2(&moboard_spi2_pdata);
524
525 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
526 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
527 spi_register_board_info(moboard_spi_board_info,
528 ARRAY_SIZE(moboard_spi_board_info));
529
530 imx31_add_mxc_mmc(0, &sdhc1_pdata);
531
532 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
533 if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
534 mxc_register_device(&mx3_camera, &camera_pdata);
535
536 usb_xcvr_reset();
537
538 moboard_usbh2_init();
539
540 switch (mx31moboard_baseboard) {
541 case MX31NOBOARD:
542 break;
543 case MX31DEVBOARD:
544 mx31moboard_devboard_init();
545 break;
546 case MX31MARXBOT:
547 mx31moboard_marxbot_init();
548 break;
549 case MX31SMARTBOT:
550 case MX31EYEBOT:
551 mx31moboard_smartbot_init(mx31moboard_baseboard);
552 break;
553 default:
554 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
555 mx31moboard_baseboard);
556 }
557}
558
559static void __init mx31moboard_timer_init(void)
560{
561 mx31_clocks_init(26000000);
562}
563
564struct sys_timer mx31moboard_timer = {
565 .init = mx31moboard_timer_init,
566};
567
568MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
569 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
570 .boot_params = MX3x_PHYS_OFFSET + 0x100,
571 .map_io = mx31_map_io,
572 .init_early = imx31_init_early,
573 .init_irq = mx31_init_irq,
574 .timer = &mx31moboard_timer,
575 .init_machine = mx31moboard_init,
576MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
deleted file mode 100644
index ff5fe231b8d6..000000000000
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18/*
19 * This machine is known as:
20 * - i.MX35 3-Stack Development System
21 * - i.MX35 Platform Development Kit (i.MX35 PDK)
22 */
23
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/memory.h>
28#include <linux/gpio.h>
29#include <linux/usb/otg.h>
30
31#include <linux/mtd/physmap.h>
32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39#include <mach/common.h>
40#include <mach/iomux-mx35.h>
41#include <mach/irqs.h>
42#include <mach/3ds_debugboard.h>
43
44#include "devices-imx35.h"
45#include "devices.h"
46
47#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
48
49static const struct imxuart_platform_data uart_pdata __initconst = {
50 .flags = IMXUART_HAVE_RTSCTS,
51};
52
53static struct physmap_flash_data mx35pdk_flash_data = {
54 .width = 2,
55};
56
57static struct resource mx35pdk_flash_resource = {
58 .start = MX35_CS0_BASE_ADDR,
59 .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
60 .flags = IORESOURCE_MEM,
61};
62
63static struct platform_device mx35pdk_flash = {
64 .name = "physmap-flash",
65 .id = 0,
66 .dev = {
67 .platform_data = &mx35pdk_flash_data,
68 },
69 .resource = &mx35pdk_flash_resource,
70 .num_resources = 1,
71};
72
73static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
74 .width = 1,
75 .hw_ecc = 1,
76 .flash_bbt = 1,
77};
78
79static struct platform_device *devices[] __initdata = {
80 &mx35pdk_flash,
81};
82
83static iomux_v3_cfg_t mx35pdk_pads[] = {
84 /* UART1 */
85 MX35_PAD_CTS1__UART1_CTS,
86 MX35_PAD_RTS1__UART1_RTS,
87 MX35_PAD_TXD1__UART1_TXD_MUX,
88 MX35_PAD_RXD1__UART1_RXD_MUX,
89 /* FEC */
90 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
91 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
92 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
93 MX35_PAD_FEC_COL__FEC_COL,
94 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
95 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
96 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
97 MX35_PAD_FEC_MDC__FEC_MDC,
98 MX35_PAD_FEC_MDIO__FEC_MDIO,
99 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
100 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
101 MX35_PAD_FEC_CRS__FEC_CRS,
102 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
103 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
104 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
105 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
106 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
107 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
108 /* USBOTG */
109 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
110 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
111 /* USBH1 */
112 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
113 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
114 /* SDCARD */
115 MX35_PAD_SD1_CMD__ESDHC1_CMD,
116 MX35_PAD_SD1_CLK__ESDHC1_CLK,
117 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
118 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
119 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
120 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
121 /* I2C1 */
122 MX35_PAD_I2C1_CLK__I2C1_SCL,
123 MX35_PAD_I2C1_DAT__I2C1_SDA,
124};
125
126static int mx35_3ds_otg_init(struct platform_device *pdev)
127{
128 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
129}
130
131/* OTG config */
132static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
133 .operating_mode = FSL_USB2_DR_DEVICE,
134 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
135 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
136/*
137 * ENGCM09152 also requires a hardware change.
138 * Please check the MX35 Chip Errata document for details.
139 */
140};
141
142static struct mxc_usbh_platform_data otg_pdata __initdata = {
143 .init = mx35_3ds_otg_init,
144 .portsc = MXC_EHCI_MODE_UTMI,
145};
146
147static int mx35_3ds_usbh_init(struct platform_device *pdev)
148{
149 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
150 MXC_EHCI_INTERNAL_PHY);
151}
152
153/* USB HOST config */
154static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
155 .init = mx35_3ds_usbh_init,
156 .portsc = MXC_EHCI_MODE_SERIAL,
157};
158
159static int otg_mode_host;
160
161static int __init mx35_3ds_otg_mode(char *options)
162{
163 if (!strcmp(options, "host"))
164 otg_mode_host = 1;
165 else if (!strcmp(options, "device"))
166 otg_mode_host = 0;
167 else
168 pr_info("otg_mode neither \"host\" nor \"device\". "
169 "Defaulting to device\n");
170 return 0;
171}
172__setup("otg_mode=", mx35_3ds_otg_mode);
173
174static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
175 .bitrate = 100000,
176};
177
178/*
179 * Board specific initialization.
180 */
181static void __init mx35_3ds_init(void)
182{
183 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
184
185 imx35_add_fec(NULL);
186 imx35_add_imx2_wdt(NULL);
187 platform_add_devices(devices, ARRAY_SIZE(devices));
188
189 imx35_add_imx_uart0(&uart_pdata);
190
191 if (otg_mode_host)
192 imx35_add_mxc_ehci_otg(&otg_pdata);
193
194 imx35_add_mxc_ehci_hs(&usb_host_pdata);
195
196 if (!otg_mode_host)
197 imx35_add_fsl_usb2_udc(&usb_otg_pdata);
198
199 imx35_add_mxc_nand(&mx35pdk_nand_board_info);
200 imx35_add_sdhci_esdhc_imx(0, NULL);
201
202 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
203 pr_warn("Init of the debugboard failed, all "
204 "devices on the debugboard are unusable.\n");
205 imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
206}
207
208static void __init mx35pdk_timer_init(void)
209{
210 mx35_clocks_init();
211}
212
213struct sys_timer mx35pdk_timer = {
214 .init = mx35pdk_timer_init,
215};
216
217MACHINE_START(MX35_3DS, "Freescale MX35PDK")
218 /* Maintainer: Freescale Semiconductor, Inc */
219 .boot_params = MX3x_PHYS_OFFSET + 0x100,
220 .map_io = mx35_map_io,
221 .init_early = imx35_init_early,
222 .init_irq = mx35_init_irq,
223 .timer = &mx35pdk_timer,
224 .init_machine = mx35_3ds_init,
225MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
deleted file mode 100644
index f07d3bded674..000000000000
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ /dev/null
@@ -1,691 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/plat-ram.h>
21#include <linux/memory.h>
22#include <linux/gpio.h>
23#include <linux/smsc911x.h>
24#include <linux/interrupt.h>
25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
30#include <linux/can/platform/sja1000.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/gfp.h>
34
35#include <media/soc_camera.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/mach/map.h>
41#include <mach/common.h>
42#include <mach/hardware.h>
43#include <mach/iomux-mx3.h>
44#include <mach/ipu.h>
45#include <mach/mx3_camera.h>
46#include <mach/mx3fb.h>
47#include <mach/ulpi.h>
48
49#include "devices-imx31.h"
50#include "devices.h"
51#include "pcm037.h"
52
53static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
54
55static int __init pcm037_variant_setup(char *str)
56{
57 if (!strcmp("eet", str))
58 pcm037_instance = PCM037_EET;
59 else if (strcmp("pcm970", str))
60 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
61
62 return 1;
63}
64
65/* Supported values: "pcm970" (default) and "eet" */
66__setup("pcm037_variant=", pcm037_variant_setup);
67
68enum pcm037_board_variant pcm037_variant(void)
69{
70 return pcm037_instance;
71}
72
73/* UART1 with RTS/CTS handshake signals */
74static unsigned int pcm037_uart1_handshake_pins[] = {
75 MX31_PIN_CTS1__CTS1,
76 MX31_PIN_RTS1__RTS1,
77 MX31_PIN_TXD1__TXD1,
78 MX31_PIN_RXD1__RXD1,
79};
80
81/* UART1 without RTS/CTS handshake signals */
82static unsigned int pcm037_uart1_pins[] = {
83 MX31_PIN_TXD1__TXD1,
84 MX31_PIN_RXD1__RXD1,
85};
86
87static unsigned int pcm037_pins[] = {
88 /* I2C */
89 MX31_PIN_CSPI2_MOSI__SCL,
90 MX31_PIN_CSPI2_MISO__SDA,
91 MX31_PIN_CSPI2_SS2__I2C3_SDA,
92 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
93 /* SDHC1 */
94 MX31_PIN_SD1_DATA3__SD1_DATA3,
95 MX31_PIN_SD1_DATA2__SD1_DATA2,
96 MX31_PIN_SD1_DATA1__SD1_DATA1,
97 MX31_PIN_SD1_DATA0__SD1_DATA0,
98 MX31_PIN_SD1_CLK__SD1_CLK,
99 MX31_PIN_SD1_CMD__SD1_CMD,
100 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
101 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
102 /* SPI1 */
103 MX31_PIN_CSPI1_MOSI__MOSI,
104 MX31_PIN_CSPI1_MISO__MISO,
105 MX31_PIN_CSPI1_SCLK__SCLK,
106 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
107 MX31_PIN_CSPI1_SS0__SS0,
108 MX31_PIN_CSPI1_SS1__SS1,
109 MX31_PIN_CSPI1_SS2__SS2,
110 /* UART2 */
111 MX31_PIN_TXD2__TXD2,
112 MX31_PIN_RXD2__RXD2,
113 MX31_PIN_CTS2__CTS2,
114 MX31_PIN_RTS2__RTS2,
115 /* UART3 */
116 MX31_PIN_CSPI3_MOSI__RXD3,
117 MX31_PIN_CSPI3_MISO__TXD3,
118 MX31_PIN_CSPI3_SCLK__RTS3,
119 MX31_PIN_CSPI3_SPI_RDY__CTS3,
120 /* LAN9217 irq pin */
121 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
122 /* Onewire */
123 MX31_PIN_BATT_LINE__OWIRE,
124 /* Framebuffer */
125 MX31_PIN_LD0__LD0,
126 MX31_PIN_LD1__LD1,
127 MX31_PIN_LD2__LD2,
128 MX31_PIN_LD3__LD3,
129 MX31_PIN_LD4__LD4,
130 MX31_PIN_LD5__LD5,
131 MX31_PIN_LD6__LD6,
132 MX31_PIN_LD7__LD7,
133 MX31_PIN_LD8__LD8,
134 MX31_PIN_LD9__LD9,
135 MX31_PIN_LD10__LD10,
136 MX31_PIN_LD11__LD11,
137 MX31_PIN_LD12__LD12,
138 MX31_PIN_LD13__LD13,
139 MX31_PIN_LD14__LD14,
140 MX31_PIN_LD15__LD15,
141 MX31_PIN_LD16__LD16,
142 MX31_PIN_LD17__LD17,
143 MX31_PIN_VSYNC3__VSYNC3,
144 MX31_PIN_HSYNC__HSYNC,
145 MX31_PIN_FPSHIFT__FPSHIFT,
146 MX31_PIN_DRDY0__DRDY0,
147 MX31_PIN_D3_REV__D3_REV,
148 MX31_PIN_CONTRAST__CONTRAST,
149 MX31_PIN_D3_SPL__D3_SPL,
150 MX31_PIN_D3_CLS__D3_CLS,
151 MX31_PIN_LCS0__GPI03_23,
152 /* CSI */
153 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
154 MX31_PIN_CSI_D6__CSI_D6,
155 MX31_PIN_CSI_D7__CSI_D7,
156 MX31_PIN_CSI_D8__CSI_D8,
157 MX31_PIN_CSI_D9__CSI_D9,
158 MX31_PIN_CSI_D10__CSI_D10,
159 MX31_PIN_CSI_D11__CSI_D11,
160 MX31_PIN_CSI_D12__CSI_D12,
161 MX31_PIN_CSI_D13__CSI_D13,
162 MX31_PIN_CSI_D14__CSI_D14,
163 MX31_PIN_CSI_D15__CSI_D15,
164 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
165 MX31_PIN_CSI_MCLK__CSI_MCLK,
166 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
167 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
168 /* GPIO */
169 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
170 /* OTG */
171 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
172 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
173 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
174 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
175 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
176 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
177 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
178 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
179 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
180 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
181 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
182 MX31_PIN_USBOTG_STP__USBOTG_STP,
183 /* USB host 2 */
184 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
196};
197
198static struct physmap_flash_data pcm037_flash_data = {
199 .width = 2,
200};
201
202static struct resource pcm037_flash_resource = {
203 .start = 0xa0000000,
204 .end = 0xa1ffffff,
205 .flags = IORESOURCE_MEM,
206};
207
208static struct platform_device pcm037_flash = {
209 .name = "physmap-flash",
210 .id = 0,
211 .dev = {
212 .platform_data = &pcm037_flash_data,
213 },
214 .resource = &pcm037_flash_resource,
215 .num_resources = 1,
216};
217
218static const struct imxuart_platform_data uart_pdata __initconst = {
219 .flags = IMXUART_HAVE_RTSCTS,
220};
221
222static struct resource smsc911x_resources[] = {
223 {
224 .start = MX31_CS1_BASE_ADDR + 0x300,
225 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
226 .flags = IORESOURCE_MEM,
227 }, {
228 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
229 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
230 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
231 },
232};
233
234static struct smsc911x_platform_config smsc911x_info = {
235 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
236 SMSC911X_SAVE_MAC_ADDRESS,
237 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
238 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
239 .phy_interface = PHY_INTERFACE_MODE_MII,
240};
241
242static struct platform_device pcm037_eth = {
243 .name = "smsc911x",
244 .id = -1,
245 .num_resources = ARRAY_SIZE(smsc911x_resources),
246 .resource = smsc911x_resources,
247 .dev = {
248 .platform_data = &smsc911x_info,
249 },
250};
251
252static struct platdata_mtd_ram pcm038_sram_data = {
253 .bankwidth = 2,
254};
255
256static struct resource pcm038_sram_resource = {
257 .start = MX31_CS4_BASE_ADDR,
258 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
259 .flags = IORESOURCE_MEM,
260};
261
262static struct platform_device pcm037_sram_device = {
263 .name = "mtd-ram",
264 .id = 0,
265 .dev = {
266 .platform_data = &pcm038_sram_data,
267 },
268 .num_resources = 1,
269 .resource = &pcm038_sram_resource,
270};
271
272static const struct mxc_nand_platform_data
273pcm037_nand_board_info __initconst = {
274 .width = 1,
275 .hw_ecc = 1,
276};
277
278static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
279 .bitrate = 100000,
280};
281
282static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
283 .bitrate = 20000,
284};
285
286static struct at24_platform_data board_eeprom = {
287 .byte_len = 4096,
288 .page_size = 32,
289 .flags = AT24_FLAG_ADDR16,
290};
291
292static int pcm037_camera_power(struct device *dev, int on)
293{
294 /* disable or enable the camera in X7 or X8 PCM970 connector */
295 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
296 return 0;
297}
298
299static struct i2c_board_info pcm037_i2c_camera[] = {
300 {
301 I2C_BOARD_INFO("mt9t031", 0x5d),
302 }, {
303 I2C_BOARD_INFO("mt9v022", 0x48),
304 },
305};
306
307static struct soc_camera_link iclink_mt9v022 = {
308 .bus_id = 0, /* Must match with the camera ID */
309 .board_info = &pcm037_i2c_camera[1],
310 .i2c_adapter_id = 2,
311};
312
313static struct soc_camera_link iclink_mt9t031 = {
314 .bus_id = 0, /* Must match with the camera ID */
315 .power = pcm037_camera_power,
316 .board_info = &pcm037_i2c_camera[0],
317 .i2c_adapter_id = 2,
318};
319
320static struct i2c_board_info pcm037_i2c_devices[] = {
321 {
322 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
323 .platform_data = &board_eeprom,
324 }, {
325 I2C_BOARD_INFO("pcf8563", 0x51),
326 }
327};
328
329static struct platform_device pcm037_mt9t031 = {
330 .name = "soc-camera-pdrv",
331 .id = 0,
332 .dev = {
333 .platform_data = &iclink_mt9t031,
334 },
335};
336
337static struct platform_device pcm037_mt9v022 = {
338 .name = "soc-camera-pdrv",
339 .id = 1,
340 .dev = {
341 .platform_data = &iclink_mt9v022,
342 },
343};
344
345/* Not connected by default */
346#ifdef PCM970_SDHC_RW_SWITCH
347static int pcm970_sdhc1_get_ro(struct device *dev)
348{
349 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
350}
351#endif
352
353#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
354#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
355
356static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
357 void *data)
358{
359 int ret;
360
361 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
362 if (ret)
363 return ret;
364
365 gpio_direction_input(SDHC1_GPIO_DET);
366
367#ifdef PCM970_SDHC_RW_SWITCH
368 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
369 if (ret)
370 goto err_gpio_free;
371 gpio_direction_input(SDHC1_GPIO_WP);
372#endif
373
374 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
375 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
376 "sdhc-detect", data);
377 if (ret)
378 goto err_gpio_free_2;
379
380 return 0;
381
382err_gpio_free_2:
383#ifdef PCM970_SDHC_RW_SWITCH
384 gpio_free(SDHC1_GPIO_WP);
385err_gpio_free:
386#endif
387 gpio_free(SDHC1_GPIO_DET);
388
389 return ret;
390}
391
392static void pcm970_sdhc1_exit(struct device *dev, void *data)
393{
394 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
395 gpio_free(SDHC1_GPIO_DET);
396 gpio_free(SDHC1_GPIO_WP);
397}
398
399static const struct imxmmc_platform_data sdhc_pdata __initconst = {
400#ifdef PCM970_SDHC_RW_SWITCH
401 .get_ro = pcm970_sdhc1_get_ro,
402#endif
403 .init = pcm970_sdhc1_init,
404 .exit = pcm970_sdhc1_exit,
405};
406
407struct mx3_camera_pdata camera_pdata = {
408 .dma_dev = &mx3_ipu.dev,
409 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
410 .mclk_10khz = 2000,
411};
412
413static int __init pcm037_camera_alloc_dma(const size_t buf_size)
414{
415 dma_addr_t dma_handle;
416 void *buf;
417 int dma;
418
419 if (buf_size < 2 * 1024 * 1024)
420 return -EINVAL;
421
422 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
423 if (!buf) {
424 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
425 return -ENOMEM;
426 }
427
428 memset(buf, 0, buf_size);
429
430 dma = dma_declare_coherent_memory(&mx3_camera.dev,
431 dma_handle, dma_handle, buf_size,
432 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
433
434 /* The way we call dma_declare_coherent_memory only a malloc can fail */
435 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
436}
437
438static struct platform_device *devices[] __initdata = {
439 &pcm037_flash,
440 &pcm037_sram_device,
441 &pcm037_mt9t031,
442 &pcm037_mt9v022,
443};
444
445static struct ipu_platform_data mx3_ipu_data = {
446 .irq_base = MXC_IPU_IRQ_START,
447};
448
449static const struct fb_videomode fb_modedb[] = {
450 {
451 /* 240x320 @ 60 Hz Sharp */
452 .name = "Sharp-LQ035Q7DH06-QVGA",
453 .refresh = 60,
454 .xres = 240,
455 .yres = 320,
456 .pixclock = 185925,
457 .left_margin = 9,
458 .right_margin = 16,
459 .upper_margin = 7,
460 .lower_margin = 9,
461 .hsync_len = 1,
462 .vsync_len = 1,
463 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
464 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
465 .vmode = FB_VMODE_NONINTERLACED,
466 .flag = 0,
467 }, {
468 /* 240x320 @ 60 Hz */
469 .name = "TX090",
470 .refresh = 60,
471 .xres = 240,
472 .yres = 320,
473 .pixclock = 38255,
474 .left_margin = 144,
475 .right_margin = 0,
476 .upper_margin = 7,
477 .lower_margin = 40,
478 .hsync_len = 96,
479 .vsync_len = 1,
480 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
481 .vmode = FB_VMODE_NONINTERLACED,
482 .flag = 0,
483 }, {
484 /* 240x320 @ 60 Hz */
485 .name = "CMEL-OLED",
486 .refresh = 60,
487 .xres = 240,
488 .yres = 320,
489 .pixclock = 185925,
490 .left_margin = 9,
491 .right_margin = 16,
492 .upper_margin = 7,
493 .lower_margin = 9,
494 .hsync_len = 1,
495 .vsync_len = 1,
496 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
497 .vmode = FB_VMODE_NONINTERLACED,
498 .flag = 0,
499 },
500};
501
502static struct mx3fb_platform_data mx3fb_pdata = {
503 .dma_dev = &mx3_ipu.dev,
504 .name = "Sharp-LQ035Q7DH06-QVGA",
505 .mode = fb_modedb,
506 .num_modes = ARRAY_SIZE(fb_modedb),
507};
508
509static struct resource pcm970_sja1000_resources[] = {
510 {
511 .start = MX31_CS5_BASE_ADDR,
512 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
513 .flags = IORESOURCE_MEM,
514 }, {
515 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
516 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
518 },
519};
520
521struct sja1000_platform_data pcm970_sja1000_platform_data = {
522 .osc_freq = 16000000,
523 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
524 .cdr = CDR_CBP,
525};
526
527static struct platform_device pcm970_sja1000 = {
528 .name = "sja1000_platform",
529 .dev = {
530 .platform_data = &pcm970_sja1000_platform_data,
531 },
532 .resource = pcm970_sja1000_resources,
533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
534};
535
536static int pcm037_otg_init(struct platform_device *pdev)
537{
538 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
539}
540
541static struct mxc_usbh_platform_data otg_pdata __initdata = {
542 .init = pcm037_otg_init,
543 .portsc = MXC_EHCI_MODE_ULPI,
544};
545
546static int pcm037_usbh2_init(struct platform_device *pdev)
547{
548 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
549}
550
551static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
552 .init = pcm037_usbh2_init,
553 .portsc = MXC_EHCI_MODE_ULPI,
554};
555
556static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
557 .operating_mode = FSL_USB2_DR_DEVICE,
558 .phy_mode = FSL_USB2_PHY_ULPI,
559};
560
561static int otg_mode_host;
562
563static int __init pcm037_otg_mode(char *options)
564{
565 if (!strcmp(options, "host"))
566 otg_mode_host = 1;
567 else if (!strcmp(options, "device"))
568 otg_mode_host = 0;
569 else
570 pr_info("otg_mode neither \"host\" nor \"device\". "
571 "Defaulting to device\n");
572 return 0;
573}
574__setup("otg_mode=", pcm037_otg_mode);
575
576/*
577 * Board specific initialization.
578 */
579static void __init pcm037_init(void)
580{
581 int ret;
582
583 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
584
585 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
586 "pcm037");
587
588#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
589 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
590
591 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
592 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
593 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
594 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
595 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
596 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
597 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
598 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
599 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
600 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
601 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
602 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
603
604 if (pcm037_variant() == PCM037_EET)
605 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
606 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
607 else
608 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
609 ARRAY_SIZE(pcm037_uart1_handshake_pins),
610 "pcm037_uart1");
611
612 platform_add_devices(devices, ARRAY_SIZE(devices));
613
614 imx31_add_imx2_wdt(NULL);
615 imx31_add_imx_uart0(&uart_pdata);
616 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
617 imx31_add_imx_uart1(&uart_pdata);
618 imx31_add_imx_uart2(&uart_pdata);
619
620 imx31_add_mxc_w1(NULL);
621
622 /* LAN9217 IRQ pin */
623 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
624 if (ret)
625 pr_warning("could not get LAN irq gpio\n");
626 else {
627 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
628 platform_device_register(&pcm037_eth);
629 }
630
631
632 /* I2C adapters and devices */
633 i2c_register_board_info(1, pcm037_i2c_devices,
634 ARRAY_SIZE(pcm037_i2c_devices));
635
636 imx31_add_imx_i2c1(&pcm037_i2c1_data);
637 imx31_add_imx_i2c2(&pcm037_i2c2_data);
638
639 imx31_add_mxc_nand(&pcm037_nand_board_info);
640 imx31_add_mxc_mmc(0, &sdhc_pdata);
641 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
642 mxc_register_device(&mx3_fb, &mx3fb_pdata);
643
644 /* CSI */
645 /* Camera power: default - off */
646 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
647 if (!ret)
648 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
649 else
650 iclink_mt9t031.power = NULL;
651
652 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
653 mxc_register_device(&mx3_camera, &camera_pdata);
654
655 platform_device_register(&pcm970_sja1000);
656
657 if (otg_mode_host) {
658 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
659 ULPI_OTG_DRVVBUS_EXT);
660 if (otg_pdata.otg)
661 imx31_add_mxc_ehci_otg(&otg_pdata);
662 }
663
664 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
665 ULPI_OTG_DRVVBUS_EXT);
666 if (usbh2_pdata.otg)
667 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
668
669 if (!otg_mode_host)
670 imx31_add_fsl_usb2_udc(&otg_device_pdata);
671
672}
673
674static void __init pcm037_timer_init(void)
675{
676 mx31_clocks_init(26000000);
677}
678
679struct sys_timer pcm037_timer = {
680 .init = pcm037_timer_init,
681};
682
683MACHINE_START(PCM037, "Phytec Phycore pcm037")
684 /* Maintainer: Pengutronix */
685 .boot_params = MX3x_PHYS_OFFSET + 0x100,
686 .map_io = mx31_map_io,
687 .init_early = imx31_init_early,
688 .init_irq = mx31_init_irq,
689 .timer = &pcm037_timer,
690 .init_machine = pcm037_init,
691MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
deleted file mode 100644
index df6fb07d037e..000000000000
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * Copyright (C) 2009
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/gpio.h>
10#include <linux/gpio_keys.h>
11#include <linux/input.h>
12#include <linux/platform_device.h>
13#include <linux/spi/spi.h>
14
15#include <mach/common.h>
16#include <mach/iomux-mx3.h>
17#include <mach/spi.h>
18
19#include <asm/mach-types.h>
20
21#include "pcm037.h"
22#include "devices.h"
23#include "devices-imx31.h"
24
25static unsigned int pcm037_eet_pins[] = {
26 /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
27 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
28 /* GPIO keys */
29 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */
30 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */
31 IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */
32 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */
33 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */
34 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */
35 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */
36 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */
37 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */
38 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */
39 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */
40 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */
41 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */
42 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */
43
44 /* LEDs */
45 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */
46 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */
47 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */
48 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */
49};
50
51/* SPI */
52static struct spi_board_info pcm037_spi_dev[] = {
53 {
54 .modalias = "dac124s085",
55 .max_speed_hz = 400000,
56 .bus_num = 0,
57 .chip_select = 0, /* Index in pcm037_spi1_cs[] */
58 .mode = SPI_CPHA,
59 },
60};
61
62/* Platform Data for MXC CSPI */
63static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
64
65static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
66 .chipselect = pcm037_spi1_cs,
67 .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
68};
69
70/* GPIO-keys input device */
71static struct gpio_keys_button pcm037_gpio_keys[] = {
72 {
73 .type = EV_KEY,
74 .code = KEY_L,
75 .gpio = 0,
76 .desc = "Wheel Manual",
77 .wakeup = 0,
78 }, {
79 .type = EV_KEY,
80 .code = KEY_A,
81 .gpio = 1,
82 .desc = "Wheel AF",
83 .wakeup = 0,
84 }, {
85 .type = EV_KEY,
86 .code = KEY_V,
87 .gpio = 2,
88 .desc = "Wheel View",
89 .wakeup = 0,
90 }, {
91 .type = EV_KEY,
92 .code = KEY_M,
93 .gpio = 3,
94 .desc = "Wheel Menu",
95 .wakeup = 0,
96 }, {
97 .type = EV_KEY,
98 .code = KEY_UP,
99 .gpio = 32,
100 .desc = "Nav Pad Up",
101 .wakeup = 0,
102 }, {
103 .type = EV_KEY,
104 .code = KEY_RIGHT,
105 .gpio = 33,
106 .desc = "Nav Pad Right",
107 .wakeup = 0,
108 }, {
109 .type = EV_KEY,
110 .code = KEY_DOWN,
111 .gpio = 34,
112 .desc = "Nav Pad Down",
113 .wakeup = 0,
114 }, {
115 .type = EV_KEY,
116 .code = KEY_LEFT,
117 .gpio = 35,
118 .desc = "Nav Pad Left",
119 .wakeup = 0,
120 }, {
121 .type = EV_KEY,
122 .code = KEY_ENTER,
123 .gpio = 38,
124 .desc = "Nav Pad Ok",
125 .wakeup = 0,
126 }, {
127 .type = EV_KEY,
128 .code = KEY_O,
129 .gpio = 39,
130 .desc = "Wheel Off",
131 .wakeup = 0,
132 }, {
133 .type = EV_KEY,
134 .code = BTN_FORWARD,
135 .gpio = 50,
136 .desc = "Focus Forward",
137 .wakeup = 0,
138 }, {
139 .type = EV_KEY,
140 .code = BTN_BACK,
141 .gpio = 51,
142 .desc = "Focus Backward",
143 .wakeup = 0,
144 }, {
145 .type = EV_KEY,
146 .code = BTN_MIDDLE,
147 .gpio = 52,
148 .desc = "Release Half",
149 .wakeup = 0,
150 }, {
151 .type = EV_KEY,
152 .code = BTN_EXTRA,
153 .gpio = 53,
154 .desc = "Release Full",
155 .wakeup = 0,
156 },
157};
158
159static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
160 .buttons = pcm037_gpio_keys,
161 .nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
162 .rep = 0, /* No auto-repeat */
163};
164
165static struct platform_device pcm037_gpio_keys_device = {
166 .name = "gpio-keys",
167 .id = -1,
168 .dev = {
169 .platform_data = &pcm037_gpio_keys_platform_data,
170 },
171};
172
173static int __init eet_init_devices(void)
174{
175 if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
176 return 0;
177
178 mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
179 ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet");
180
181 /* SPI */
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183 imx31_add_spi_imx0(&pcm037_spi1_pdata);
184
185 platform_device_register(&pcm037_gpio_keys_device);
186
187 return 0;
188}
189
190late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
deleted file mode 100644
index 036ba1a4704b..000000000000
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ /dev/null
@@ -1,428 +0,0 @@
1/*
2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/plat-ram.h>
21#include <linux/memory.h>
22#include <linux/gpio.h>
23#include <linux/smc911x.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/i2c/at24.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34#include <asm/mach/map.h>
35
36#include <mach/hardware.h>
37#include <mach/common.h>
38#include <mach/iomux-mx35.h>
39#include <mach/ipu.h>
40#include <mach/mx3fb.h>
41#include <mach/ulpi.h>
42#include <mach/audmux.h>
43#include <mach/esdhc.h>
44
45#include "devices-imx35.h"
46#include "devices.h"
47
48static const struct fb_videomode fb_modedb[] = {
49 {
50 /* 240x320 @ 60 Hz */
51 .name = "Sharp-LQ035Q7",
52 .refresh = 60,
53 .xres = 240,
54 .yres = 320,
55 .pixclock = 185925,
56 .left_margin = 9,
57 .right_margin = 16,
58 .upper_margin = 7,
59 .lower_margin = 9,
60 .hsync_len = 1,
61 .vsync_len = 1,
62 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
63 .vmode = FB_VMODE_NONINTERLACED,
64 .flag = 0,
65 }, {
66 /* 240x320 @ 60 Hz */
67 .name = "TX090",
68 .refresh = 60,
69 .xres = 240,
70 .yres = 320,
71 .pixclock = 38255,
72 .left_margin = 144,
73 .right_margin = 0,
74 .upper_margin = 7,
75 .lower_margin = 40,
76 .hsync_len = 96,
77 .vsync_len = 1,
78 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
79 .vmode = FB_VMODE_NONINTERLACED,
80 .flag = 0,
81 },
82};
83
84static struct ipu_platform_data mx3_ipu_data = {
85 .irq_base = MXC_IPU_IRQ_START,
86};
87
88static struct mx3fb_platform_data mx3fb_pdata = {
89 .dma_dev = &mx3_ipu.dev,
90 .name = "Sharp-LQ035Q7",
91 .mode = fb_modedb,
92 .num_modes = ARRAY_SIZE(fb_modedb),
93};
94
95static struct physmap_flash_data pcm043_flash_data = {
96 .width = 2,
97};
98
99static struct resource pcm043_flash_resource = {
100 .start = 0xa0000000,
101 .end = 0xa1ffffff,
102 .flags = IORESOURCE_MEM,
103};
104
105static struct platform_device pcm043_flash = {
106 .name = "physmap-flash",
107 .id = 0,
108 .dev = {
109 .platform_data = &pcm043_flash_data,
110 },
111 .resource = &pcm043_flash_resource,
112 .num_resources = 1,
113};
114
115static const struct imxuart_platform_data uart_pdata __initconst = {
116 .flags = IMXUART_HAVE_RTSCTS,
117};
118
119static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
120 .bitrate = 50000,
121};
122
123static struct at24_platform_data board_eeprom = {
124 .byte_len = 4096,
125 .page_size = 32,
126 .flags = AT24_FLAG_ADDR16,
127};
128
129static struct i2c_board_info pcm043_i2c_devices[] = {
130 {
131 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
132 .platform_data = &board_eeprom,
133 }, {
134 I2C_BOARD_INFO("pcf8563", 0x51),
135 }
136};
137
138static struct platform_device *devices[] __initdata = {
139 &pcm043_flash,
140};
141
142static iomux_v3_cfg_t pcm043_pads[] = {
143 /* UART1 */
144 MX35_PAD_CTS1__UART1_CTS,
145 MX35_PAD_RTS1__UART1_RTS,
146 MX35_PAD_TXD1__UART1_TXD_MUX,
147 MX35_PAD_RXD1__UART1_RXD_MUX,
148 /* UART2 */
149 MX35_PAD_CTS2__UART2_CTS,
150 MX35_PAD_RTS2__UART2_RTS,
151 MX35_PAD_TXD2__UART2_TXD_MUX,
152 MX35_PAD_RXD2__UART2_RXD_MUX,
153 /* FEC */
154 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
155 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
156 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
157 MX35_PAD_FEC_COL__FEC_COL,
158 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
159 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
160 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
161 MX35_PAD_FEC_MDC__FEC_MDC,
162 MX35_PAD_FEC_MDIO__FEC_MDIO,
163 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
164 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
165 MX35_PAD_FEC_CRS__FEC_CRS,
166 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
167 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
168 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
169 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
170 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
171 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
172 /* I2C1 */
173 MX35_PAD_I2C1_CLK__I2C1_SCL,
174 MX35_PAD_I2C1_DAT__I2C1_SDA,
175 /* Display */
176 MX35_PAD_LD0__IPU_DISPB_DAT_0,
177 MX35_PAD_LD1__IPU_DISPB_DAT_1,
178 MX35_PAD_LD2__IPU_DISPB_DAT_2,
179 MX35_PAD_LD3__IPU_DISPB_DAT_3,
180 MX35_PAD_LD4__IPU_DISPB_DAT_4,
181 MX35_PAD_LD5__IPU_DISPB_DAT_5,
182 MX35_PAD_LD6__IPU_DISPB_DAT_6,
183 MX35_PAD_LD7__IPU_DISPB_DAT_7,
184 MX35_PAD_LD8__IPU_DISPB_DAT_8,
185 MX35_PAD_LD9__IPU_DISPB_DAT_9,
186 MX35_PAD_LD10__IPU_DISPB_DAT_10,
187 MX35_PAD_LD11__IPU_DISPB_DAT_11,
188 MX35_PAD_LD12__IPU_DISPB_DAT_12,
189 MX35_PAD_LD13__IPU_DISPB_DAT_13,
190 MX35_PAD_LD14__IPU_DISPB_DAT_14,
191 MX35_PAD_LD15__IPU_DISPB_DAT_15,
192 MX35_PAD_LD16__IPU_DISPB_DAT_16,
193 MX35_PAD_LD17__IPU_DISPB_DAT_17,
194 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
195 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
196 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
197 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
198 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
199 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
200 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
201 /* gpio */
202 MX35_PAD_ATA_CS0__GPIO2_6,
203 /* USB host */
204 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
205 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
206 /* SSI */
207 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
208 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
209 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
210 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
211 /* CAN2 */
212 MX35_PAD_TX5_RX0__CAN2_TXCAN,
213 MX35_PAD_TX4_RX1__CAN2_RXCAN,
214 /* esdhc */
215 MX35_PAD_SD1_CMD__ESDHC1_CMD,
216 MX35_PAD_SD1_CLK__ESDHC1_CLK,
217 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
218 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
219 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
220 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
221 MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
222 MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
223};
224
225#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
226#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
227#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
228#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
229#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
230
231static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
232{
233 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
234 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
235 int ret;
236
237 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
238 if (ret) {
239 printk("failed to get GPIO_TXFS: %d\n", ret);
240 return;
241 }
242
243 mxc_iomux_v3_setup_pad(txfs_gpio);
244
245 /* warm reset */
246 gpio_direction_output(AC97_GPIO_TXFS, 1);
247 udelay(2);
248 gpio_set_value(AC97_GPIO_TXFS, 0);
249
250 gpio_free(AC97_GPIO_TXFS);
251 mxc_iomux_v3_setup_pad(txfs);
252}
253
254static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
255{
256 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
257 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
258 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
259 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
260 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
261 int ret;
262
263 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
264 if (ret)
265 goto err1;
266
267 ret = gpio_request(AC97_GPIO_TXD, "SSI");
268 if (ret)
269 goto err2;
270
271 ret = gpio_request(AC97_GPIO_RESET, "SSI");
272 if (ret)
273 goto err3;
274
275 mxc_iomux_v3_setup_pad(txfs_gpio);
276 mxc_iomux_v3_setup_pad(txd_gpio);
277 mxc_iomux_v3_setup_pad(reset_gpio);
278
279 gpio_direction_output(AC97_GPIO_TXFS, 0);
280 gpio_direction_output(AC97_GPIO_TXD, 0);
281
282 /* cold reset */
283 gpio_direction_output(AC97_GPIO_RESET, 0);
284 udelay(10);
285 gpio_direction_output(AC97_GPIO_RESET, 1);
286
287 mxc_iomux_v3_setup_pad(txd);
288 mxc_iomux_v3_setup_pad(txfs);
289
290 gpio_free(AC97_GPIO_RESET);
291err3:
292 gpio_free(AC97_GPIO_TXD);
293err2:
294 gpio_free(AC97_GPIO_TXFS);
295err1:
296 if (ret)
297 printk("%s failed with %d\n", __func__, ret);
298 mdelay(1);
299}
300
301static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
302 .ac97_reset = pcm043_ac97_cold_reset,
303 .ac97_warm_reset = pcm043_ac97_warm_reset,
304 .flags = IMX_SSI_USE_AC97,
305};
306
307static const struct mxc_nand_platform_data
308pcm037_nand_board_info __initconst = {
309 .width = 1,
310 .hw_ecc = 1,
311};
312
313static int pcm043_otg_init(struct platform_device *pdev)
314{
315 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
316}
317
318static struct mxc_usbh_platform_data otg_pdata __initdata = {
319 .init = pcm043_otg_init,
320 .portsc = MXC_EHCI_MODE_UTMI,
321};
322
323static int pcm043_usbh1_init(struct platform_device *pdev)
324{
325 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
326 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
327}
328
329static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
330 .init = pcm043_usbh1_init,
331 .portsc = MXC_EHCI_MODE_SERIAL,
332};
333
334static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
335 .operating_mode = FSL_USB2_DR_DEVICE,
336 .phy_mode = FSL_USB2_PHY_UTMI,
337};
338
339static int otg_mode_host;
340
341static int __init pcm043_otg_mode(char *options)
342{
343 if (!strcmp(options, "host"))
344 otg_mode_host = 1;
345 else if (!strcmp(options, "device"))
346 otg_mode_host = 0;
347 else
348 pr_info("otg_mode neither \"host\" nor \"device\". "
349 "Defaulting to device\n");
350 return 0;
351}
352__setup("otg_mode=", pcm043_otg_mode);
353
354static struct esdhc_platform_data sd1_pdata = {
355 .wp_gpio = SD1_GPIO_WP,
356 .cd_gpio = SD1_GPIO_CD,
357};
358
359/*
360 * Board specific initialization.
361 */
362static void __init pcm043_init(void)
363{
364 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
365
366 mxc_audmux_v2_configure_port(3,
367 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
368 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
369 MXC_AUDMUX_V2_PTCR_TFSDIR,
370 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
371
372 mxc_audmux_v2_configure_port(0,
373 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
374 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
375 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
376 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
377
378 imx35_add_fec(NULL);
379 platform_add_devices(devices, ARRAY_SIZE(devices));
380 imx35_add_imx2_wdt(NULL);
381
382 imx35_add_imx_uart0(&uart_pdata);
383 imx35_add_mxc_nand(&pcm037_nand_board_info);
384 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
385
386 imx35_add_imx_uart1(&uart_pdata);
387
388 i2c_register_board_info(0, pcm043_i2c_devices,
389 ARRAY_SIZE(pcm043_i2c_devices));
390
391 imx35_add_imx_i2c0(&pcm043_i2c0_data);
392
393 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
394 mxc_register_device(&mx3_fb, &mx3fb_pdata);
395
396 if (otg_mode_host) {
397 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
398 ULPI_OTG_DRVVBUS_EXT);
399 if (otg_pdata.otg)
400 imx35_add_mxc_ehci_otg(&otg_pdata);
401 }
402 imx35_add_mxc_ehci_hs(&usbh1_pdata);
403
404 if (!otg_mode_host)
405 imx35_add_fsl_usb2_udc(&otg_device_pdata);
406
407 imx35_add_flexcan1(NULL);
408 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
409}
410
411static void __init pcm043_timer_init(void)
412{
413 mx35_clocks_init();
414}
415
416struct sys_timer pcm043_timer = {
417 .init = pcm043_timer_init,
418};
419
420MACHINE_START(PCM043, "Phytec Phycore pcm043")
421 /* Maintainer: Pengutronix */
422 .boot_params = MX3x_PHYS_OFFSET + 0x100,
423 .map_io = mx35_map_io,
424 .init_early = imx35_init_early,
425 .init_irq = mx35_init_irq,
426 .timer = &pcm043_timer,
427 .init_machine = pcm043_init,
428MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
deleted file mode 100644
index 17f758b77623..000000000000
--- a/arch/arm/mach-mx3/mach-qong.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/*
2 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/memory.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21#include <linux/mtd/nand.h>
22#include <linux/gpio.h>
23
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/time.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <asm/page.h>
32#include <asm/setup.h>
33#include <mach/iomux-mx3.h>
34
35#include "devices-imx31.h"
36#include "devices.h"
37
38/* FPGA defines */
39#define QONG_FPGA_VERSION(major, minor, rev) \
40 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
41
42#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
43#define QONG_FPGA_PERIPH_SIZE (1 << 24)
44
45#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
46#define QONG_FPGA_CTRL_SIZE 0x10
47/* FPGA control registers */
48#define QONG_FPGA_CTRL_VERSION 0x00
49
50#define QONG_DNET_ID 1
51#define QONG_DNET_BASEADDR \
52 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
53#define QONG_DNET_SIZE 0x00001000
54
55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
56
57static const struct imxuart_platform_data uart_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS,
59};
60
61static int uart_pins[] = {
62 MX31_PIN_CTS1__CTS1,
63 MX31_PIN_RTS1__RTS1,
64 MX31_PIN_TXD1__TXD1,
65 MX31_PIN_RXD1__RXD1
66};
67
68static inline void __init mxc_init_imx_uart(void)
69{
70 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
71 "uart-0");
72 imx31_add_imx_uart0(&uart_pdata);
73}
74
75static struct resource dnet_resources[] = {
76 {
77 .name = "dnet-memory",
78 .start = QONG_DNET_BASEADDR,
79 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
80 .flags = IORESOURCE_MEM,
81 }, {
82 .start = QONG_FPGA_IRQ,
83 .end = QONG_FPGA_IRQ,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct platform_device dnet_device = {
89 .name = "dnet",
90 .id = -1,
91 .num_resources = ARRAY_SIZE(dnet_resources),
92 .resource = dnet_resources,
93};
94
95static int __init qong_init_dnet(void)
96{
97 int ret;
98
99 ret = platform_device_register(&dnet_device);
100 return ret;
101}
102
103/* MTD NOR flash */
104
105static struct physmap_flash_data qong_flash_data = {
106 .width = 2,
107};
108
109static struct resource qong_flash_resource = {
110 .start = MX31_CS0_BASE_ADDR,
111 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device qong_nor_mtd_device = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &qong_flash_data,
120 },
121 .resource = &qong_flash_resource,
122 .num_resources = 1,
123};
124
125static void qong_init_nor_mtd(void)
126{
127 (void)platform_device_register(&qong_nor_mtd_device);
128}
129
130/*
131 * Hardware specific access to control-lines
132 */
133static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
134{
135 struct nand_chip *nand_chip = mtd->priv;
136
137 if (cmd == NAND_CMD_NONE)
138 return;
139
140 if (ctrl & NAND_CLE)
141 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
142 else
143 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
144}
145
146/*
147 * Read the Device Ready pin.
148 */
149static int qong_nand_device_ready(struct mtd_info *mtd)
150{
151 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
152}
153
154static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
155{
156 if (chip >= 0)
157 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
158 else
159 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
160}
161
162static struct platform_nand_data qong_nand_data = {
163 .chip = {
164 .nr_chips = 1,
165 .chip_delay = 20,
166 .options = 0,
167 },
168 .ctrl = {
169 .cmd_ctrl = qong_nand_cmd_ctrl,
170 .dev_ready = qong_nand_device_ready,
171 .select_chip = qong_nand_select_chip,
172 }
173};
174
175static struct resource qong_nand_resource = {
176 .start = MX31_CS3_BASE_ADDR,
177 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
178 .flags = IORESOURCE_MEM,
179};
180
181static struct platform_device qong_nand_device = {
182 .name = "gen_nand",
183 .id = -1,
184 .dev = {
185 .platform_data = &qong_nand_data,
186 },
187 .num_resources = 1,
188 .resource = &qong_nand_resource,
189};
190
191static void __init qong_init_nand_mtd(void)
192{
193 /* init CS */
194 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
195 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
196
197 /* enable pin */
198 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
199 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
200 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
201
202 /* ready/busy pin */
203 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
204 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
205 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
206
207 /* write protect pin */
208 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
209 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
210 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
211
212 platform_device_register(&qong_nand_device);
213}
214
215static void __init qong_init_fpga(void)
216{
217 void __iomem *regs;
218 u32 fpga_ver;
219
220 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
221 if (!regs) {
222 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
223 __func__);
224 return;
225 }
226
227 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
228 iounmap(regs);
229 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
230 (fpga_ver & 0xF000) >> 12,
231 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
232 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
233 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
234 "devices won't be registered!\n");
235 return;
236 }
237
238 /* register FPGA-based devices */
239 qong_init_nand_mtd();
240 qong_init_dnet();
241}
242
243/*
244 * Board specific initialization.
245 */
246static void __init qong_init(void)
247{
248 mxc_init_imx_uart();
249 qong_init_nor_mtd();
250 qong_init_fpga();
251}
252
253static void __init qong_timer_init(void)
254{
255 mx31_clocks_init(26000000);
256}
257
258static struct sys_timer qong_timer = {
259 .init = qong_timer_init,
260};
261
262MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
263 /* Maintainer: DENX Software Engineering GmbH */
264 .boot_params = MX3x_PHYS_OFFSET + 0x100,
265 .map_io = mx31_map_io,
266 .init_early = imx31_init_early,
267 .init_irq = mx31_init_irq,
268 .timer = &qong_timer,
269 .init_machine = qong_init,
270MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
deleted file mode 100644
index 47a69cbc31a8..000000000000
--- a/arch/arm/mach-mx3/mach-vpr200.c
+++ /dev/null
@@ -1,333 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
4 * Copyright 2010 Creative Product Design
5 *
6 * Derived from mx35 3stack.
7 * Original author: Fabio Estevam <fabio.estevam@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/memory.h>
25#include <linux/gpio.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/iomux-mx35.h>
34#include <mach/irqs.h>
35#include <mach/ipu.h>
36#include <mach/mx3fb.h>
37
38#include <linux/i2c.h>
39#include <linux/i2c/at24.h>
40#include <linux/mfd/mc13xxx.h>
41#include <linux/gpio_keys.h>
42
43#include "devices-imx35.h"
44#include "devices.h"
45
46#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
47#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
48
49#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
50#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
51#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
52#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
53#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
54#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
55#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
56#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
57
58static const struct fb_videomode fb_modedb[] = {
59 {
60 /* 800x480 @ 60 Hz */
61 .name = "PT0708048",
62 .refresh = 60,
63 .xres = 800,
64 .yres = 480,
65 .pixclock = KHZ2PICOS(33260),
66 .left_margin = 50,
67 .right_margin = 156,
68 .upper_margin = 10,
69 .lower_margin = 10,
70 .hsync_len = 1, /* note: DE only display */
71 .vsync_len = 1, /* note: DE only display */
72 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
73 .vmode = FB_VMODE_NONINTERLACED,
74 .flag = 0,
75 }, {
76 /* 800x480 @ 60 Hz */
77 .name = "CTP-CLAA070LC0ACW",
78 .refresh = 60,
79 .xres = 800,
80 .yres = 480,
81 .pixclock = KHZ2PICOS(27000),
82 .left_margin = 50,
83 .right_margin = 50, /* whole line should have 900 clocks */
84 .upper_margin = 10,
85 .lower_margin = 10, /* whole frame should have 500 lines */
86 .hsync_len = 1, /* note: DE only display */
87 .vsync_len = 1, /* note: DE only display */
88 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
89 .vmode = FB_VMODE_NONINTERLACED,
90 .flag = 0,
91 }
92};
93
94static struct ipu_platform_data mx3_ipu_data = {
95 .irq_base = MXC_IPU_IRQ_START,
96};
97
98static struct mx3fb_platform_data mx3fb_pdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "PT0708048",
101 .mode = fb_modedb,
102 .num_modes = ARRAY_SIZE(fb_modedb),
103};
104
105static struct physmap_flash_data vpr200_flash_data = {
106 .width = 2,
107};
108
109static struct resource vpr200_flash_resource = {
110 .start = MX35_CS0_BASE_ADDR,
111 .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device vpr200_flash = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &vpr200_flash_data,
120 },
121 .resource = &vpr200_flash_resource,
122 .num_resources = 1,
123};
124
125static const struct mxc_nand_platform_data
126 vpr200_nand_board_info __initconst = {
127 .width = 1,
128 .hw_ecc = 1,
129 .flash_bbt = 1,
130};
131
132#define VPR_KEY_DEBOUNCE 500
133static struct gpio_keys_button vpr200_gpio_keys_table[] = {
134 {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
135 {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
136 {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
137 {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
138 {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
139 {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
140 {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
141 {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
142};
143
144static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
145 .buttons = vpr200_gpio_keys_table,
146 .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
147};
148
149static struct platform_device vpr200_device_gpiokeys = {
150 .name = "gpio-keys",
151 .dev = {
152 .platform_data = &vpr200_gpio_keys_data,
153 }
154};
155
156static struct mc13xxx_platform_data vpr200_pmic = {
157 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
158};
159
160static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
161 .bitrate = 50000,
162};
163
164static struct at24_platform_data vpr200_eeprom = {
165 .byte_len = 2048 / 8,
166 .page_size = 1,
167};
168
169static struct i2c_board_info vpr200_i2c_devices[] = {
170 {
171 I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
172 .platform_data = &vpr200_eeprom,
173 }, {
174 I2C_BOARD_INFO("mc13892", 0x08),
175 .platform_data = &vpr200_pmic,
176 .irq = gpio_to_irq(GPIO_PMIC_INT),
177 }
178};
179
180static iomux_v3_cfg_t vpr200_pads[] = {
181 /* UART1 */
182 MX35_PAD_TXD1__UART1_TXD_MUX,
183 MX35_PAD_RXD1__UART1_RXD_MUX,
184 /* UART3 */
185 MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
186 MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
187 /* FEC */
188 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
189 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
190 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
191 MX35_PAD_FEC_COL__FEC_COL,
192 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
193 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
194 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
195 MX35_PAD_FEC_MDC__FEC_MDC,
196 MX35_PAD_FEC_MDIO__FEC_MDIO,
197 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
198 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
199 MX35_PAD_FEC_CRS__FEC_CRS,
200 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
201 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
202 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
203 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
204 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
205 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
206 /* Display */
207 MX35_PAD_LD0__IPU_DISPB_DAT_0,
208 MX35_PAD_LD1__IPU_DISPB_DAT_1,
209 MX35_PAD_LD2__IPU_DISPB_DAT_2,
210 MX35_PAD_LD3__IPU_DISPB_DAT_3,
211 MX35_PAD_LD4__IPU_DISPB_DAT_4,
212 MX35_PAD_LD5__IPU_DISPB_DAT_5,
213 MX35_PAD_LD6__IPU_DISPB_DAT_6,
214 MX35_PAD_LD7__IPU_DISPB_DAT_7,
215 MX35_PAD_LD8__IPU_DISPB_DAT_8,
216 MX35_PAD_LD9__IPU_DISPB_DAT_9,
217 MX35_PAD_LD10__IPU_DISPB_DAT_10,
218 MX35_PAD_LD11__IPU_DISPB_DAT_11,
219 MX35_PAD_LD12__IPU_DISPB_DAT_12,
220 MX35_PAD_LD13__IPU_DISPB_DAT_13,
221 MX35_PAD_LD14__IPU_DISPB_DAT_14,
222 MX35_PAD_LD15__IPU_DISPB_DAT_15,
223 MX35_PAD_LD16__IPU_DISPB_DAT_16,
224 MX35_PAD_LD17__IPU_DISPB_DAT_17,
225 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
226 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
227 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
228 /* LCD Enable */
229 MX35_PAD_D3_VSYNC__GPIO1_2,
230 /* USBOTG */
231 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
232 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
233 /* SDCARD */
234 MX35_PAD_SD1_CMD__ESDHC1_CMD,
235 MX35_PAD_SD1_CLK__ESDHC1_CLK,
236 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
237 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
238 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
239 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
240 /* PMIC */
241 MX35_PAD_GPIO2_0__GPIO2_0,
242 /* GPIO keys */
243 MX35_PAD_SCKR__GPIO1_4,
244 MX35_PAD_COMPARE__GPIO1_5,
245 MX35_PAD_SCKT__GPIO1_7,
246 MX35_PAD_FST__GPIO1_8,
247 MX35_PAD_HCKT__GPIO1_9,
248 MX35_PAD_TX5_RX0__GPIO1_10,
249 MX35_PAD_TX4_RX1__GPIO1_11,
250 MX35_PAD_TX3_RX2__GPIO1_12,
251};
252
253/* USB Device config */
254static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
255 .operating_mode = FSL_USB2_DR_DEVICE,
256 .phy_mode = FSL_USB2_PHY_UTMI,
257 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
258};
259
260static int vpr200_usbh_init(struct platform_device *pdev)
261{
262 return mx35_initialize_usb_hw(pdev->id,
263 MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY);
264}
265
266/* USB HOST config */
267static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
268 .init = vpr200_usbh_init,
269 .portsc = MXC_EHCI_MODE_SERIAL,
270};
271
272static struct platform_device *devices[] __initdata = {
273 &vpr200_flash,
274 &vpr200_device_gpiokeys,
275};
276
277/*
278 * Board specific initialization.
279 */
280static void __init vpr200_board_init(void)
281{
282 mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
283
284 imx35_add_fec(NULL);
285 imx35_add_imx2_wdt(NULL);
286
287 platform_add_devices(devices, ARRAY_SIZE(devices));
288
289 if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
290 printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
291 else
292 gpio_direction_output(GPIO_LCDPWR, 0);
293
294 if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
295 printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
296 else
297 gpio_direction_input(GPIO_PMIC_INT);
298
299 imx35_add_imx_uart0(NULL);
300 imx35_add_imx_uart2(NULL);
301
302 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
303 mxc_register_device(&mx3_fb, &mx3fb_pdata);
304
305 imx35_add_fsl_usb2_udc(&otg_device_pdata);
306 imx35_add_mxc_ehci_hs(&usb_host_pdata);
307
308 imx35_add_mxc_nand(&vpr200_nand_board_info);
309 imx35_add_sdhci_esdhc_imx(0, NULL);
310
311 i2c_register_board_info(0, vpr200_i2c_devices,
312 ARRAY_SIZE(vpr200_i2c_devices));
313
314 imx35_add_imx_i2c0(&vpr200_i2c0_data);
315}
316
317static void __init vpr200_timer_init(void)
318{
319 mx35_clocks_init();
320}
321
322struct sys_timer vpr200_timer = {
323 .init = vpr200_timer_init,
324};
325
326MACHINE_START(VPR200, "VPR200")
327 /* Maintainer: Creative Product Design */
328 .map_io = mx35_map_io,
329 .init_early = imx35_init_early,
330 .init_irq = mx35_init_irq,
331 .timer = &vpr200_timer,
332 .init_machine = vpr200_board_init,
333MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
deleted file mode 100644
index 54d7174b4202..000000000000
--- a/arch/arm/mach-mx3/mm.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-v3.h>
30#include <mach/gpio.h>
31#include <mach/irqs.h>
32
33#ifdef CONFIG_SOC_IMX31
34static struct map_desc mx31_io_desc[] __initdata = {
35 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
36 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
38 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
39 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
40};
41
42/*
43 * This function initializes the memory map. It is called during the
44 * system startup to create static physical to virtual memory mappings
45 * for the IO modules.
46 */
47void __init mx31_map_io(void)
48{
49 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
50}
51
52void __init imx31_init_early(void)
53{
54 mxc_set_cpu_type(MXC_CPU_MX31);
55 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
56}
57
58static struct mxc_gpio_port imx31_gpio_ports[] = {
59 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
60 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
61 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
62};
63
64void __init mx31_init_irq(void)
65{
66 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
67 mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
68}
69#endif /* ifdef CONFIG_SOC_IMX31 */
70
71#ifdef CONFIG_SOC_IMX35
72static struct map_desc mx35_io_desc[] __initdata = {
73 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
74 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
75 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
76 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
77 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
78};
79
80void __init mx35_map_io(void)
81{
82 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
83}
84
85void __init imx35_init_early(void)
86{
87 mxc_set_cpu_type(MXC_CPU_MX35);
88 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
89 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
90}
91
92static struct mxc_gpio_port imx35_gpio_ports[] = {
93 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
94 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
95 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
96};
97
98void __init mx35_init_irq(void)
99{
100 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
101 mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
102}
103#endif /* ifdef CONFIG_SOC_IMX35 */
104
105#ifdef CONFIG_CACHE_L2X0
106static int mxc_init_l2x0(void)
107{
108 void __iomem *l2x0_base;
109 void __iomem *clkctl_base;
110/*
111 * First of all, we must repair broken chip settings. There are some
112 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
113 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
114 * Workaraound is to setup the correct register setting prior enabling the
115 * L2 cache. This should not hurt already working CPUs, as they are using the
116 * same value
117 */
118#define L2_MEM_VAL 0x10
119
120 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
121 if (clkctl_base != NULL) {
122 writel(0x00000515, clkctl_base + L2_MEM_VAL);
123 iounmap(clkctl_base);
124 } else {
125 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
126 }
127
128 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
129 if (IS_ERR(l2x0_base)) {
130 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
131 PTR_ERR(l2x0_base));
132 return 0;
133 }
134
135 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
136
137 return 0;
138}
139
140arch_initcall(mxc_init_l2x0);
141#endif
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
deleted file mode 100644
index 8f1a38ebf5c8..000000000000
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * LILLY-1131 development board support
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * based on code for other MX31 boards,
7 *
8 * Copyright 2005-2007 Freescale Semiconductor
9 * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
10 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include <mach/hardware.h>
34#include <mach/common.h>
35#include <mach/iomux-mx3.h>
36#include <mach/board-mx31lilly.h>
37#include <mach/mx3fb.h>
38#include <mach/ipu.h>
39
40#include "devices-imx31.h"
41#include "devices.h"
42
43/*
44 * This file contains board-specific initialization routines for the
45 * LILLY-1131 development board. If you design an own baseboard for the
46 * module, use this file as base for support code.
47 */
48
49static unsigned int lilly_db_board_pins[] __initdata = {
50 MX31_PIN_CTS1__CTS1,
51 MX31_PIN_RTS1__RTS1,
52 MX31_PIN_TXD1__TXD1,
53 MX31_PIN_RXD1__RXD1,
54 MX31_PIN_CTS2__CTS2,
55 MX31_PIN_RTS2__RTS2,
56 MX31_PIN_TXD2__TXD2,
57 MX31_PIN_RXD2__RXD2,
58 MX31_PIN_CSPI3_MOSI__RXD3,
59 MX31_PIN_CSPI3_MISO__TXD3,
60 MX31_PIN_CSPI3_SCLK__RTS3,
61 MX31_PIN_CSPI3_SPI_RDY__CTS3,
62 MX31_PIN_SD1_DATA3__SD1_DATA3,
63 MX31_PIN_SD1_DATA2__SD1_DATA2,
64 MX31_PIN_SD1_DATA1__SD1_DATA1,
65 MX31_PIN_SD1_DATA0__SD1_DATA0,
66 MX31_PIN_SD1_CLK__SD1_CLK,
67 MX31_PIN_SD1_CMD__SD1_CMD,
68 MX31_PIN_LD0__LD0,
69 MX31_PIN_LD1__LD1,
70 MX31_PIN_LD2__LD2,
71 MX31_PIN_LD3__LD3,
72 MX31_PIN_LD4__LD4,
73 MX31_PIN_LD5__LD5,
74 MX31_PIN_LD6__LD6,
75 MX31_PIN_LD7__LD7,
76 MX31_PIN_LD8__LD8,
77 MX31_PIN_LD9__LD9,
78 MX31_PIN_LD10__LD10,
79 MX31_PIN_LD11__LD11,
80 MX31_PIN_LD12__LD12,
81 MX31_PIN_LD13__LD13,
82 MX31_PIN_LD14__LD14,
83 MX31_PIN_LD15__LD15,
84 MX31_PIN_LD16__LD16,
85 MX31_PIN_LD17__LD17,
86 MX31_PIN_VSYNC3__VSYNC3,
87 MX31_PIN_HSYNC__HSYNC,
88 MX31_PIN_FPSHIFT__FPSHIFT,
89 MX31_PIN_DRDY0__DRDY0,
90 MX31_PIN_CONTRAST__CONTRAST,
91};
92
93/* UART */
94static const struct imxuart_platform_data uart_pdata __initconst = {
95 .flags = IMXUART_HAVE_RTSCTS,
96};
97
98/* MMC support */
99
100static int mxc_mmc1_get_ro(struct device *dev)
101{
102 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
103}
104
105static int gpio_det, gpio_wp;
106
107#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
108 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
109
110static int mxc_mmc1_init(struct device *dev,
111 irq_handler_t detect_irq, void *data)
112{
113 int ret;
114
115 gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
116 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
117
118 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
119 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
120 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
121 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
122 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
123 mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
124
125 ret = gpio_request(gpio_det, "MMC detect");
126 if (ret)
127 return ret;
128
129 ret = gpio_request(gpio_wp, "MMC w/p");
130 if (ret)
131 goto exit_free_det;
132
133 gpio_direction_input(gpio_det);
134 gpio_direction_input(gpio_wp);
135
136 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
137 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
138 "MMC detect", data);
139 if (ret)
140 goto exit_free_wp;
141
142 return 0;
143
144exit_free_wp:
145 gpio_free(gpio_wp);
146
147exit_free_det:
148 gpio_free(gpio_det);
149
150 return ret;
151}
152
153static void mxc_mmc1_exit(struct device *dev, void *data)
154{
155 gpio_free(gpio_det);
156 gpio_free(gpio_wp);
157 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
158}
159
160static const struct imxmmc_platform_data mmc_pdata __initconst = {
161 .get_ro = mxc_mmc1_get_ro,
162 .init = mxc_mmc1_init,
163 .exit = mxc_mmc1_exit,
164};
165
166/* Framebuffer support */
167static struct ipu_platform_data ipu_data __initdata = {
168 .irq_base = MXC_IPU_IRQ_START,
169};
170
171static const struct fb_videomode fb_modedb = {
172 /* 640x480 TFT panel (IPS-056T) */
173 .name = "CRT-VGA",
174 .refresh = 64,
175 .xres = 640,
176 .yres = 480,
177 .pixclock = 30000,
178 .left_margin = 200,
179 .right_margin = 2,
180 .upper_margin = 2,
181 .lower_margin = 2,
182 .hsync_len = 3,
183 .vsync_len = 1,
184 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
185 .vmode = FB_VMODE_NONINTERLACED,
186 .flag = 0,
187};
188
189static struct mx3fb_platform_data fb_pdata __initdata = {
190 .dma_dev = &mx3_ipu.dev,
191 .name = "CRT-VGA",
192 .mode = &fb_modedb,
193 .num_modes = 1,
194};
195
196#define LCD_VCC_EN_GPIO (7)
197
198static void __init mx31lilly_init_fb(void)
199{
200 if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
201 printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
202 return;
203 }
204
205 mxc_register_device(&mx3_ipu, &ipu_data);
206 mxc_register_device(&mx3_fb, &fb_pdata);
207 gpio_direction_output(LCD_VCC_EN_GPIO, 1);
208}
209
210void __init mx31lilly_db_init(void)
211{
212 mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
213 ARRAY_SIZE(lilly_db_board_pins),
214 "development board pins");
215 imx31_add_imx_uart0(&uart_pdata);
216 imx31_add_imx_uart1(&uart_pdata);
217 imx31_add_imx_uart2(&uart_pdata);
218 imx31_add_mxc_mmc(0, &mmc_pdata);
219 mx31lilly_init_fb();
220}
221
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
deleted file mode 100644
index 3124ea837ac7..000000000000
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * LogicPD i.MX31 SOM-LV development board support
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * based on code for other MX31 boards,
7 *
8 * Copyright 2005-2007 Freescale Semiconductor
9 * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
10 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33
34#include <mach/hardware.h>
35#include <mach/common.h>
36#include <mach/iomux-mx3.h>
37#include <mach/board-mx31lite.h>
38
39#include "devices-imx31.h"
40#include "devices.h"
41
42/*
43 * This file contains board-specific initialization routines for the
44 * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
45 * If you design an own baseboard for the module, use this file as base
46 * for support code.
47 */
48
49static unsigned int litekit_db_board_pins[] __initdata = {
50 /* UART1 */
51 MX31_PIN_CTS1__CTS1,
52 MX31_PIN_RTS1__RTS1,
53 MX31_PIN_TXD1__TXD1,
54 MX31_PIN_RXD1__RXD1,
55 /* SPI 0 */
56 MX31_PIN_CSPI1_SCLK__SCLK,
57 MX31_PIN_CSPI1_MOSI__MOSI,
58 MX31_PIN_CSPI1_MISO__MISO,
59 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
60 MX31_PIN_CSPI1_SS0__SS0,
61 MX31_PIN_CSPI1_SS1__SS1,
62 MX31_PIN_CSPI1_SS2__SS2,
63 /* SDHC1 */
64 MX31_PIN_SD1_DATA0__SD1_DATA0,
65 MX31_PIN_SD1_DATA1__SD1_DATA1,
66 MX31_PIN_SD1_DATA2__SD1_DATA2,
67 MX31_PIN_SD1_DATA3__SD1_DATA3,
68 MX31_PIN_SD1_CLK__SD1_CLK,
69 MX31_PIN_SD1_CMD__SD1_CMD,
70};
71
72/* UART */
73static const struct imxuart_platform_data uart_pdata __initconst = {
74 .flags = IMXUART_HAVE_RTSCTS,
75};
76
77/* MMC */
78
79static int gpio_det, gpio_wp;
80
81#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
82 PAD_CTL_ODE_CMOS)
83
84static int mxc_mmc1_get_ro(struct device *dev)
85{
86 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
87}
88
89static int mxc_mmc1_init(struct device *dev,
90 irq_handler_t detect_irq, void *data)
91{
92 int ret;
93
94 gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
95 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
96
97 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
98 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
99 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
100 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
101 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
102 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
103 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
104 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
105 mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
106 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
107 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
108
109 ret = gpio_request(gpio_det, "MMC detect");
110 if (ret)
111 return ret;
112
113 ret = gpio_request(gpio_wp, "MMC w/p");
114 if (ret)
115 goto exit_free_det;
116
117 gpio_direction_input(gpio_det);
118 gpio_direction_input(gpio_wp);
119
120 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
121 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
122 "MMC detect", data);
123 if (ret)
124 goto exit_free_wp;
125
126 return 0;
127
128exit_free_wp:
129 gpio_free(gpio_wp);
130
131exit_free_det:
132 gpio_free(gpio_det);
133
134 return ret;
135}
136
137static void mxc_mmc1_exit(struct device *dev, void *data)
138{
139 gpio_free(gpio_det);
140 gpio_free(gpio_wp);
141 free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
142}
143
144static const struct imxmmc_platform_data mmc_pdata __initconst = {
145 .get_ro = mxc_mmc1_get_ro,
146 .init = mxc_mmc1_init,
147 .exit = mxc_mmc1_exit,
148};
149
150/* SPI */
151
152static int spi_internal_chipselect[] = {
153 MXC_SPI_CS(0),
154 MXC_SPI_CS(1),
155 MXC_SPI_CS(2),
156};
157
158static const struct spi_imx_master spi0_pdata __initconst = {
159 .chipselect = spi_internal_chipselect,
160 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
161};
162
163/* GPIO LEDs */
164
165static struct gpio_led litekit_leds[] = {
166 {
167 .name = "GPIO0",
168 .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
169 .active_low = 1,
170 .default_state = LEDS_GPIO_DEFSTATE_OFF,
171 },
172 {
173 .name = "GPIO1",
174 .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
175 .active_low = 1,
176 .default_state = LEDS_GPIO_DEFSTATE_OFF,
177 }
178};
179
180static struct gpio_led_platform_data litekit_led_platform_data = {
181 .leds = litekit_leds,
182 .num_leds = ARRAY_SIZE(litekit_leds),
183};
184
185static struct platform_device litekit_led_device = {
186 .name = "leds-gpio",
187 .id = -1,
188 .dev = {
189 .platform_data = &litekit_led_platform_data,
190 },
191};
192
193void __init mx31lite_db_init(void)
194{
195 mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
196 ARRAY_SIZE(litekit_db_board_pins),
197 "development board pins");
198 imx31_add_imx_uart0(&uart_pdata);
199 imx31_add_mxc_mmc(0, &mmc_pdata);
200 imx31_add_spi_imx0(&spi0_pdata);
201 platform_device_register(&litekit_led_device);
202 imx31_add_imx2_wdt(NULL);
203 mxc_register_device(&imx_rtc_device0, NULL);
204}
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
deleted file mode 100644
index 6410b9c48a02..000000000000
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/gpio.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/types.h>
22
23#include <linux/usb/otg.h>
24
25#include <mach/common.h>
26#include <mach/iomux-mx3.h>
27#include <mach/hardware.h>
28#include <mach/ulpi.h>
29
30#include "devices-imx31.h"
31#include "devices.h"
32
33static unsigned int devboard_pins[] = {
34 /* UART1 */
35 MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
36 MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
37 /* SDHC2 */
38 MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
39 MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
40 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
41 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
42 /* USB H1 */
43 MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
44 MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
45 MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
46 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
47 MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
48 /* SEL */
49 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
50 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
51};
52
53static const struct imxuart_platform_data uart_pdata __initconst = {
54 .flags = IMXUART_HAVE_RTSCTS,
55};
56
57#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
58#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
59
60static int devboard_sdhc2_get_ro(struct device *dev)
61{
62 return !gpio_get_value(SDHC2_WP);
63}
64
65static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
66 void *data)
67{
68 int ret;
69
70 ret = gpio_request(SDHC2_CD, "sdhc-detect");
71 if (ret)
72 return ret;
73
74 gpio_direction_input(SDHC2_CD);
75
76 ret = gpio_request(SDHC2_WP, "sdhc-wp");
77 if (ret)
78 goto err_gpio_free;
79 gpio_direction_input(SDHC2_WP);
80
81 ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
82 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
83 "sdhc2-card-detect", data);
84 if (ret)
85 goto err_gpio_free_2;
86
87 return 0;
88
89err_gpio_free_2:
90 gpio_free(SDHC2_WP);
91err_gpio_free:
92 gpio_free(SDHC2_CD);
93
94 return ret;
95}
96
97static void devboard_sdhc2_exit(struct device *dev, void *data)
98{
99 free_irq(gpio_to_irq(SDHC2_CD), data);
100 gpio_free(SDHC2_WP);
101 gpio_free(SDHC2_CD);
102}
103
104static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
105 .get_ro = devboard_sdhc2_get_ro,
106 .init = devboard_sdhc2_init,
107 .exit = devboard_sdhc2_exit,
108};
109
110#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
111#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
112#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
113#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
114
115static void devboard_init_sel_gpios(void)
116{
117 if (!gpio_request(SEL0, "sel0")) {
118 gpio_direction_input(SEL0);
119 gpio_export(SEL0, true);
120 }
121
122 if (!gpio_request(SEL1, "sel1")) {
123 gpio_direction_input(SEL1);
124 gpio_export(SEL1, true);
125 }
126
127 if (!gpio_request(SEL2, "sel2")) {
128 gpio_direction_input(SEL2);
129 gpio_export(SEL2, true);
130 }
131
132 if (!gpio_request(SEL3, "sel3")) {
133 gpio_direction_input(SEL3);
134 gpio_export(SEL3, true);
135 }
136}
137#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
138 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
139
140static int devboard_usbh1_hw_init(struct platform_device *pdev)
141{
142 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
143
144 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
145 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
146 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
147 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
148 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
149 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
152
153 mdelay(10);
154
155 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
156 MXC_EHCI_INTERFACE_SINGLE_UNI);
157}
158
159#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
160#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
161
162static int devboard_isp1105_init(struct otg_transceiver *otg)
163{
164 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
165 if (ret)
166 return ret;
167 /* single ended */
168 gpio_direction_output(USBH1_MODE, 0);
169
170 ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
171 if (ret) {
172 gpio_free(USBH1_MODE);
173 return ret;
174 }
175 gpio_direction_output(USBH1_VBUSEN_B, 1);
176
177 return 0;
178}
179
180
181static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
182{
183 if (on)
184 gpio_set_value(USBH1_VBUSEN_B, 0);
185 else
186 gpio_set_value(USBH1_VBUSEN_B, 1);
187
188 return 0;
189}
190
191static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
192 .init = devboard_usbh1_hw_init,
193 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
194};
195
196static int __init devboard_usbh1_init(void)
197{
198 struct otg_transceiver *otg;
199 struct platform_device *pdev;
200
201 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
202 if (!otg)
203 return -ENOMEM;
204
205 otg->label = "ISP1105";
206 otg->init = devboard_isp1105_init;
207 otg->set_vbus = devboard_isp1105_set_vbus;
208
209 usbh1_pdata.otg = otg;
210
211 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
212 if (IS_ERR(pdev))
213 return PTR_ERR(pdev);
214
215 return 0;
216}
217
218
219static const struct fsl_usb2_platform_data usb_pdata __initconst = {
220 .operating_mode = FSL_USB2_DR_DEVICE,
221 .phy_mode = FSL_USB2_PHY_ULPI,
222};
223
224/*
225 * system init for baseboard usage. Will be called by mx31moboard init.
226 */
227void __init mx31moboard_devboard_init(void)
228{
229 printk(KERN_INFO "Initializing mx31devboard peripherals\n");
230
231 mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
232 "devboard");
233
234 imx31_add_imx_uart1(&uart_pdata);
235
236 imx31_add_mxc_mmc(1, &sdhc2_pdata);
237
238 devboard_init_sel_gpios();
239
240 imx31_add_fsl_usb2_udc(&usb_pdata);
241
242 devboard_usbh1_init();
243}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
deleted file mode 100644
index 57f7b00cb709..000000000000
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ /dev/null
@@ -1,368 +0,0 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/types.h>
24
25#include <linux/usb/otg.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx3.h>
31#include <mach/ulpi.h>
32
33#include <media/soc_camera.h>
34
35#include "devices-imx31.h"
36#include "devices.h"
37
38static unsigned int marxbot_pins[] = {
39 /* SDHC2 */
40 MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
41 MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
42 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
43 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
44 /* CSI */
45 MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
46 MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
47 MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
48 MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
49 MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
50 MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
51 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
52 MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
53 MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
54 MX31_PIN_TXD2__GPIO1_28,
55 /* dsPIC resets */
56 MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
57 /*battery detection */
58 MX31_PIN_LCS0__GPIO3_23,
59 /* USB H1 */
60 MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
61 MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
62 MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
63 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
64 MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
65 /* SEL */
66 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
67 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
68};
69
70#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
71#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
72
73static int marxbot_sdhc2_get_ro(struct device *dev)
74{
75 return !gpio_get_value(SDHC2_WP);
76}
77
78static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
79 void *data)
80{
81 int ret;
82
83 ret = gpio_request(SDHC2_CD, "sdhc-detect");
84 if (ret)
85 return ret;
86
87 gpio_direction_input(SDHC2_CD);
88
89 ret = gpio_request(SDHC2_WP, "sdhc-wp");
90 if (ret)
91 goto err_gpio_free;
92 gpio_direction_input(SDHC2_WP);
93
94 ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
95 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
96 "sdhc2-card-detect", data);
97 if (ret)
98 goto err_gpio_free_2;
99
100 return 0;
101
102err_gpio_free_2:
103 gpio_free(SDHC2_WP);
104err_gpio_free:
105 gpio_free(SDHC2_CD);
106
107 return ret;
108}
109
110static void marxbot_sdhc2_exit(struct device *dev, void *data)
111{
112 free_irq(gpio_to_irq(SDHC2_CD), data);
113 gpio_free(SDHC2_WP);
114 gpio_free(SDHC2_CD);
115}
116
117static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
118 .get_ro = marxbot_sdhc2_get_ro,
119 .init = marxbot_sdhc2_init,
120 .exit = marxbot_sdhc2_exit,
121};
122
123#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5)
124#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5)
125
126static void dspics_resets_init(void)
127{
128 if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
129 gpio_direction_output(TRSLAT_RST_B, 0);
130 gpio_export(TRSLAT_RST_B, false);
131 }
132
133 if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
134 gpio_direction_output(DSPICS_RST_B, 0);
135 gpio_export(DSPICS_RST_B, false);
136 }
137}
138
139static struct spi_board_info marxbot_spi_board_info[] __initdata = {
140 {
141 .modalias = "spidev",
142 .max_speed_hz = 300000,
143 .bus_num = 1,
144 .chip_select = 1, /* according spi1_cs[] ! */
145 },
146};
147
148#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
149#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
150#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
151#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
152#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
153
154static int marxbot_basecam_power(struct device *dev, int on)
155{
156 gpio_set_value(BASECAM_POWER, !on);
157 return 0;
158}
159
160static int marxbot_basecam_reset(struct device *dev)
161{
162 gpio_set_value(BASECAM_RST_B, 0);
163 udelay(100);
164 gpio_set_value(BASECAM_RST_B, 1);
165 return 0;
166}
167
168static struct i2c_board_info marxbot_i2c_devices[] = {
169 {
170 I2C_BOARD_INFO("mt9t031", 0x5d),
171 },
172};
173
174static struct soc_camera_link base_iclink = {
175 .bus_id = 0, /* Must match with the camera ID */
176 .power = marxbot_basecam_power,
177 .reset = marxbot_basecam_reset,
178 .board_info = &marxbot_i2c_devices[0],
179 .i2c_adapter_id = 0,
180};
181
182static struct platform_device marxbot_camera[] = {
183 {
184 .name = "soc-camera-pdrv",
185 .id = 0,
186 .dev = {
187 .platform_data = &base_iclink,
188 },
189 },
190};
191
192static struct platform_device *marxbot_cameras[] __initdata = {
193 &marxbot_camera[0],
194};
195
196static int __init marxbot_cam_init(void)
197{
198 int ret = gpio_request(CAM_CHOICE, "cam-choice");
199 if (ret)
200 return ret;
201 gpio_direction_output(CAM_CHOICE, 0);
202
203 ret = gpio_request(BASECAM_RST_B, "basecam-reset");
204 if (ret)
205 return ret;
206 gpio_direction_output(BASECAM_RST_B, 1);
207 ret = gpio_request(BASECAM_POWER, "basecam-standby");
208 if (ret)
209 return ret;
210 gpio_direction_output(BASECAM_POWER, 0);
211
212 ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
213 if (ret)
214 return ret;
215 gpio_direction_output(TURRETCAM_RST_B, 1);
216 ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
217 if (ret)
218 return ret;
219 gpio_direction_output(TURRETCAM_POWER, 0);
220
221 return 0;
222}
223
224#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
225#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
226#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
227#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
228
229static void marxbot_init_sel_gpios(void)
230{
231 if (!gpio_request(SEL0, "sel0")) {
232 gpio_direction_input(SEL0);
233 gpio_export(SEL0, true);
234 }
235
236 if (!gpio_request(SEL1, "sel1")) {
237 gpio_direction_input(SEL1);
238 gpio_export(SEL1, true);
239 }
240
241 if (!gpio_request(SEL2, "sel2")) {
242 gpio_direction_input(SEL2);
243 gpio_export(SEL2, true);
244 }
245
246 if (!gpio_request(SEL3, "sel3")) {
247 gpio_direction_input(SEL3);
248 gpio_export(SEL3, true);
249 }
250}
251
252#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
253 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
254
255static int marxbot_usbh1_hw_init(struct platform_device *pdev)
256{
257 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
258
259 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
260 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
261 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
262 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
263 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
264 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
265 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
267
268 mdelay(10);
269
270 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
271 MXC_EHCI_INTERFACE_SINGLE_UNI);
272}
273
274#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
275#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
276
277static int marxbot_isp1105_init(struct otg_transceiver *otg)
278{
279 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
280 if (ret)
281 return ret;
282 /* single ended */
283 gpio_direction_output(USBH1_MODE, 0);
284
285 ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
286 if (ret) {
287 gpio_free(USBH1_MODE);
288 return ret;
289 }
290 gpio_direction_output(USBH1_VBUSEN_B, 1);
291
292 return 0;
293}
294
295
296static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
297{
298 if (on)
299 gpio_set_value(USBH1_VBUSEN_B, 0);
300 else
301 gpio_set_value(USBH1_VBUSEN_B, 1);
302
303 return 0;
304}
305
306static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
307 .init = marxbot_usbh1_hw_init,
308 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
309};
310
311static int __init marxbot_usbh1_init(void)
312{
313 struct otg_transceiver *otg;
314 struct platform_device *pdev;
315
316 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
317 if (!otg)
318 return -ENOMEM;
319
320 otg->label = "ISP1105";
321 otg->init = marxbot_isp1105_init;
322 otg->set_vbus = marxbot_isp1105_set_vbus;
323
324 usbh1_pdata.otg = otg;
325
326 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
327 if (IS_ERR(pdev))
328 return PTR_ERR(pdev);
329
330 return 0;
331}
332
333static const struct fsl_usb2_platform_data usb_pdata __initconst = {
334 .operating_mode = FSL_USB2_DR_DEVICE,
335 .phy_mode = FSL_USB2_PHY_ULPI,
336};
337
338/*
339 * system init for baseboard usage. Will be called by mx31moboard init.
340 */
341void __init mx31moboard_marxbot_init(void)
342{
343 printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
344
345 mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
346 "marxbot");
347
348 marxbot_init_sel_gpios();
349
350 dspics_resets_init();
351
352 imx31_add_mxc_mmc(1, &sdhc2_pdata);
353
354 spi_register_board_info(marxbot_spi_board_info,
355 ARRAY_SIZE(marxbot_spi_board_info));
356
357 marxbot_cam_init();
358 platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
359
360 /* battery present pin */
361 gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
362 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
363 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
364
365 imx31_add_fsl_usb2_udc(&usb_pdata);
366
367 marxbot_usbh1_init();
368}
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
deleted file mode 100644
index 35f806e737c1..000000000000
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/types.h>
22
23#include <linux/usb/otg.h>
24#include <linux/usb/ulpi.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx3.h>
29#include <mach/board-mx31moboard.h>
30#include <mach/ulpi.h>
31
32#include <media/soc_camera.h>
33
34#include "devices-imx31.h"
35#include "devices.h"
36
37static unsigned int smartbot_pins[] = {
38 /* UART1 */
39 MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
40 MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
41 /* CSI */
42 MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
43 MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
44 MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
45 MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
46 MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
47 MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
48 MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
49 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
50 MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
51 /* ENABLES */
52 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
53 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
54};
55
56static const struct imxuart_platform_data uart_pdata __initconst = {
57 .flags = IMXUART_HAVE_RTSCTS,
58};
59
60#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
61#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
62
63static int smartbot_cam_power(struct device *dev, int on)
64{
65 gpio_set_value(CAM_POWER, !on);
66 return 0;
67}
68
69static int smartbot_cam_reset(struct device *dev)
70{
71 gpio_set_value(CAM_RST_B, 0);
72 udelay(100);
73 gpio_set_value(CAM_RST_B, 1);
74 return 0;
75}
76
77static struct i2c_board_info smartbot_i2c_devices[] = {
78 {
79 I2C_BOARD_INFO("mt9t031", 0x5d),
80 },
81};
82
83static struct soc_camera_link base_iclink = {
84 .bus_id = 0, /* Must match with the camera ID */
85 .power = smartbot_cam_power,
86 .reset = smartbot_cam_reset,
87 .board_info = &smartbot_i2c_devices[0],
88 .i2c_adapter_id = 0,
89};
90
91static struct platform_device smartbot_camera[] = {
92 {
93 .name = "soc-camera-pdrv",
94 .id = 0,
95 .dev = {
96 .platform_data = &base_iclink,
97 },
98 },
99};
100
101static struct platform_device *smartbot_cameras[] __initdata = {
102 &smartbot_camera[0],
103};
104
105static int __init smartbot_cam_init(void)
106{
107 int ret = gpio_request(CAM_RST_B, "cam-reset");
108 if (ret)
109 return ret;
110 gpio_direction_output(CAM_RST_B, 1);
111 ret = gpio_request(CAM_POWER, "cam-standby");
112 if (ret)
113 return ret;
114 gpio_direction_output(CAM_POWER, 0);
115
116 return 0;
117}
118
119static const struct fsl_usb2_platform_data usb_pdata __initconst = {
120 .operating_mode = FSL_USB2_DR_DEVICE,
121 .phy_mode = FSL_USB2_PHY_ULPI,
122};
123
124#if defined(CONFIG_USB_ULPI)
125
126static int smartbot_otg_init(struct platform_device *pdev)
127{
128 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
129}
130
131static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
132 .init = smartbot_otg_init,
133 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
134};
135
136static int __init smartbot_otg_host_init(void)
137{
138 struct platform_device *pdev;
139
140 otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
141 ULPI_OTG_DRVVBUS_EXT);
142 if (!otg_host_pdata.otg)
143 return -ENODEV;
144
145 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
146 if (IS_ERR(pdev))
147 return PTR_ERR(pdev);
148
149 return 0;
150}
151#else
152static inline int smartbot_otg_host_init(void) { return 0; }
153#endif
154
155#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
156#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
157#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
158#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
159
160static void smartbot_resets_init(void)
161{
162 if (!gpio_request(POWER_EN, "power-enable")) {
163 gpio_direction_output(POWER_EN, 0);
164 gpio_export(POWER_EN, false);
165 }
166
167 if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
168 gpio_direction_output(DSPIC_RST_B, 0);
169 gpio_export(DSPIC_RST_B, false);
170 }
171
172 if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
173 gpio_direction_output(TRSLAT_RST_B, 0);
174 gpio_export(TRSLAT_RST_B, false);
175 }
176
177 if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
178 gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
179 gpio_export(TRSLAT_SRC_CHOICE, false);
180 }
181}
182/*
183 * system init for baseboard usage. Will be called by mx31moboard init.
184 */
185void __init mx31moboard_smartbot_init(int board)
186{
187 printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
188
189 mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
190 "smartbot");
191
192 imx31_add_imx_uart1(&uart_pdata);
193
194 switch (board) {
195 case MX31SMARTBOT:
196 imx31_add_fsl_usb2_udc(&usb_pdata);
197 break;
198 case MX31EYEBOT:
199 smartbot_otg_host_init();
200 break;
201 default:
202 printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
203 board);
204 }
205
206 smartbot_resets_init();
207
208 smartbot_cam_init();
209 platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
210}
diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-mx3/pcm037.h
deleted file mode 100644
index d6929721a5fd..000000000000
--- a/arch/arm/mach-mx3/pcm037.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __PCM037_H__
2#define __PCM037_H__
3
4enum pcm037_board_variant {
5 PCM037_PCM970,
6 PCM037_EET,
7};
8
9extern enum pcm037_board_variant pcm037_variant(void);
10
11#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 12:02:09 -0500