diff options
Diffstat (limited to 'arch/arm/mach-mx3/mx31pdk.c')
-rw-r--r-- | arch/arm/mach-mx3/mx31pdk.c | 164 |
1 files changed, 154 insertions, 10 deletions
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c index bc63f1785691..32599e507534 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mx31pdk.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
23 | #include <linux/gpio.h> | ||
23 | 24 | ||
24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
25 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
@@ -41,21 +42,159 @@ | |||
41 | * @ingroup System | 42 | * @ingroup System |
42 | */ | 43 | */ |
43 | 44 | ||
45 | static int mx31pdk_pins[] = { | ||
46 | /* UART1 */ | ||
47 | MX31_PIN_CTS1__CTS1, | ||
48 | MX31_PIN_RTS1__RTS1, | ||
49 | MX31_PIN_TXD1__TXD1, | ||
50 | MX31_PIN_RXD1__RXD1, | ||
51 | IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), | ||
52 | }; | ||
53 | |||
44 | static struct imxuart_platform_data uart_pdata = { | 54 | static struct imxuart_platform_data uart_pdata = { |
45 | .flags = IMXUART_HAVE_RTSCTS, | 55 | .flags = IMXUART_HAVE_RTSCTS, |
46 | }; | 56 | }; |
47 | 57 | ||
48 | static int uart_pins[] = { | 58 | /* |
49 | MX31_PIN_CTS1__CTS1, | 59 | * Routines for the CPLD on the debug board. It contains a CPLD handling |
50 | MX31_PIN_RTS1__RTS1, | 60 | * LEDs, switches, interrupts for Ethernet. |
51 | MX31_PIN_TXD1__TXD1, | 61 | */ |
52 | MX31_PIN_RXD1__RXD1 | 62 | |
63 | static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc) | ||
64 | { | ||
65 | uint32_t imr_val; | ||
66 | uint32_t int_valid; | ||
67 | uint32_t expio_irq; | ||
68 | |||
69 | imr_val = __raw_readw(CPLD_INT_MASK_REG); | ||
70 | int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; | ||
71 | |||
72 | expio_irq = MXC_EXP_IO_BASE; | ||
73 | for (; int_valid != 0; int_valid >>= 1, expio_irq++) { | ||
74 | if ((int_valid & 1) == 0) | ||
75 | continue; | ||
76 | generic_handle_irq(expio_irq); | ||
77 | } | ||
78 | } | ||
79 | |||
80 | /* | ||
81 | * Disable an expio pin's interrupt by setting the bit in the imr. | ||
82 | * @param irq an expio virtual irq number | ||
83 | */ | ||
84 | static void expio_mask_irq(uint32_t irq) | ||
85 | { | ||
86 | uint16_t reg; | ||
87 | uint32_t expio = MXC_IRQ_TO_EXPIO(irq); | ||
88 | |||
89 | /* mask the interrupt */ | ||
90 | reg = __raw_readw(CPLD_INT_MASK_REG); | ||
91 | reg |= 1 << expio; | ||
92 | __raw_writew(reg, CPLD_INT_MASK_REG); | ||
93 | } | ||
94 | |||
95 | /* | ||
96 | * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. | ||
97 | * @param irq an expanded io virtual irq number | ||
98 | */ | ||
99 | static void expio_ack_irq(uint32_t irq) | ||
100 | { | ||
101 | uint32_t expio = MXC_IRQ_TO_EXPIO(irq); | ||
102 | |||
103 | /* clear the interrupt status */ | ||
104 | __raw_writew(1 << expio, CPLD_INT_RESET_REG); | ||
105 | __raw_writew(0, CPLD_INT_RESET_REG); | ||
106 | /* mask the interrupt */ | ||
107 | expio_mask_irq(irq); | ||
108 | } | ||
109 | |||
110 | /* | ||
111 | * Enable a expio pin's interrupt by clearing the bit in the imr. | ||
112 | * @param irq a expio virtual irq number | ||
113 | */ | ||
114 | static void expio_unmask_irq(uint32_t irq) | ||
115 | { | ||
116 | uint16_t reg; | ||
117 | uint32_t expio = MXC_IRQ_TO_EXPIO(irq); | ||
118 | |||
119 | /* unmask the interrupt */ | ||
120 | reg = __raw_readw(CPLD_INT_MASK_REG); | ||
121 | reg &= ~(1 << expio); | ||
122 | __raw_writew(reg, CPLD_INT_MASK_REG); | ||
123 | } | ||
124 | |||
125 | static struct irq_chip expio_irq_chip = { | ||
126 | .ack = expio_ack_irq, | ||
127 | .mask = expio_mask_irq, | ||
128 | .unmask = expio_unmask_irq, | ||
53 | }; | 129 | }; |
54 | 130 | ||
55 | static inline void mxc_init_imx_uart(void) | 131 | static int __init mx31pdk_init_expio(void) |
56 | { | 132 | { |
57 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); | 133 | int i; |
58 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 134 | int ret; |
135 | |||
136 | /* Check if there's a debug board connected */ | ||
137 | if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || | ||
138 | (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || | ||
139 | (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { | ||
140 | /* No Debug board found */ | ||
141 | return -ENODEV; | ||
142 | } | ||
143 | |||
144 | pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n", | ||
145 | __raw_readw(CPLD_CODE_VER_REG)); | ||
146 | |||
147 | /* | ||
148 | * Configure INT line as GPIO input | ||
149 | */ | ||
150 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); | ||
151 | if (ret) | ||
152 | pr_warning("could not get LAN irq gpio\n"); | ||
153 | else | ||
154 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); | ||
155 | |||
156 | /* Disable the interrupts and clear the status */ | ||
157 | __raw_writew(0, CPLD_INT_MASK_REG); | ||
158 | __raw_writew(0xFFFF, CPLD_INT_RESET_REG); | ||
159 | __raw_writew(0, CPLD_INT_RESET_REG); | ||
160 | __raw_writew(0x1F, CPLD_INT_MASK_REG); | ||
161 | for (i = MXC_EXP_IO_BASE; | ||
162 | i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); | ||
163 | i++) { | ||
164 | set_irq_chip(i, &expio_irq_chip); | ||
165 | set_irq_handler(i, handle_level_irq); | ||
166 | set_irq_flags(i, IRQF_VALID); | ||
167 | } | ||
168 | set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); | ||
169 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler); | ||
170 | |||
171 | return 0; | ||
172 | } | ||
173 | |||
174 | /* | ||
175 | * This structure defines the MX31 memory map. | ||
176 | */ | ||
177 | static struct map_desc mx31pdk_io_desc[] __initdata = { | ||
178 | { | ||
179 | .virtual = SPBA0_BASE_ADDR_VIRT, | ||
180 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | ||
181 | .length = SPBA0_SIZE, | ||
182 | .type = MT_DEVICE_NONSHARED, | ||
183 | }, { | ||
184 | .virtual = CS5_BASE_ADDR_VIRT, | ||
185 | .pfn = __phys_to_pfn(CS5_BASE_ADDR), | ||
186 | .length = CS5_SIZE, | ||
187 | .type = MT_DEVICE, | ||
188 | }, | ||
189 | }; | ||
190 | |||
191 | /* | ||
192 | * Set up static virtual mappings. | ||
193 | */ | ||
194 | static void __init mx31pdk_map_io(void) | ||
195 | { | ||
196 | mx31_map_io(); | ||
197 | iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); | ||
59 | } | 198 | } |
60 | 199 | ||
61 | /*! | 200 | /*! |
@@ -63,7 +202,12 @@ static inline void mxc_init_imx_uart(void) | |||
63 | */ | 202 | */ |
64 | static void __init mxc_board_init(void) | 203 | static void __init mxc_board_init(void) |
65 | { | 204 | { |
66 | mxc_init_imx_uart(); | 205 | mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins), |
206 | "mx31pdk"); | ||
207 | |||
208 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
209 | |||
210 | mx31pdk_init_expio(); | ||
67 | } | 211 | } |
68 | 212 | ||
69 | static void __init mx31pdk_timer_init(void) | 213 | static void __init mx31pdk_timer_init(void) |
@@ -84,7 +228,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") | |||
84 | .phys_io = AIPS1_BASE_ADDR, | 228 | .phys_io = AIPS1_BASE_ADDR, |
85 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 229 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
86 | .boot_params = PHYS_OFFSET + 0x100, | 230 | .boot_params = PHYS_OFFSET + 0x100, |
87 | .map_io = mxc_map_io, | 231 | .map_io = mx31pdk_map_io, |
88 | .init_irq = mxc_init_irq, | 232 | .init_irq = mxc_init_irq, |
89 | .init_machine = mxc_board_init, | 233 | .init_machine = mxc_board_init, |
90 | .timer = &mx31pdk_timer, | 234 | .timer = &mx31pdk_timer, |