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-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c413
1 files changed, 413 insertions, 0 deletions
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
new file mode 100644
index 000000000000..1bf1ec2eef5e
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -0,0 +1,413 @@
1/*
2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/mtd/plat-ram.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/smc911x.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/i2c/at24.h>
32#include <linux/usb/otg.h>
33#include <linux/usb/ulpi.h>
34#include <linux/fsl_devices.h>
35
36#include <asm/mach-types.h>
37#include <asm/mach/arch.h>
38#include <asm/mach/time.h>
39#include <asm/mach/map.h>
40
41#include <mach/hardware.h>
42#include <mach/common.h>
43#include <mach/imx-uart.h>
44#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
45#include <mach/i2c.h>
46#endif
47#include <mach/iomux-mx35.h>
48#include <mach/ipu.h>
49#include <mach/mx3fb.h>
50#include <mach/mxc_nand.h>
51#include <mach/mxc_ehci.h>
52#include <mach/ulpi.h>
53#include <mach/audmux.h>
54#include <mach/ssi.h>
55
56#include "devices.h"
57
58static const struct fb_videomode fb_modedb[] = {
59 {
60 /* 240x320 @ 60 Hz */
61 .name = "Sharp-LQ035Q7",
62 .refresh = 60,
63 .xres = 240,
64 .yres = 320,
65 .pixclock = 185925,
66 .left_margin = 9,
67 .right_margin = 16,
68 .upper_margin = 7,
69 .lower_margin = 9,
70 .hsync_len = 1,
71 .vsync_len = 1,
72 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
73 .vmode = FB_VMODE_NONINTERLACED,
74 .flag = 0,
75 }, {
76 /* 240x320 @ 60 Hz */
77 .name = "TX090",
78 .refresh = 60,
79 .xres = 240,
80 .yres = 320,
81 .pixclock = 38255,
82 .left_margin = 144,
83 .right_margin = 0,
84 .upper_margin = 7,
85 .lower_margin = 40,
86 .hsync_len = 96,
87 .vsync_len = 1,
88 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
89 .vmode = FB_VMODE_NONINTERLACED,
90 .flag = 0,
91 },
92};
93
94static struct ipu_platform_data mx3_ipu_data = {
95 .irq_base = MXC_IPU_IRQ_START,
96};
97
98static struct mx3fb_platform_data mx3fb_pdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "Sharp-LQ035Q7",
101 .mode = fb_modedb,
102 .num_modes = ARRAY_SIZE(fb_modedb),
103};
104
105static struct physmap_flash_data pcm043_flash_data = {
106 .width = 2,
107};
108
109static struct resource pcm043_flash_resource = {
110 .start = 0xa0000000,
111 .end = 0xa1ffffff,
112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device pcm043_flash = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &pcm043_flash_data,
120 },
121 .resource = &pcm043_flash_resource,
122 .num_resources = 1,
123};
124
125static struct imxuart_platform_data uart_pdata = {
126 .flags = IMXUART_HAVE_RTSCTS,
127};
128
129#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
130static struct imxi2c_platform_data pcm043_i2c_1_data = {
131 .bitrate = 50000,
132};
133
134static struct at24_platform_data board_eeprom = {
135 .byte_len = 4096,
136 .page_size = 32,
137 .flags = AT24_FLAG_ADDR16,
138};
139
140static struct i2c_board_info pcm043_i2c_devices[] = {
141 {
142 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
143 .platform_data = &board_eeprom,
144 }, {
145 I2C_BOARD_INFO("pcf8563", 0x51),
146 }
147};
148#endif
149
150static struct platform_device *devices[] __initdata = {
151 &pcm043_flash,
152 &mxc_fec_device,
153};
154
155static struct pad_desc pcm043_pads[] = {
156 /* UART1 */
157 MX35_PAD_CTS1__UART1_CTS,
158 MX35_PAD_RTS1__UART1_RTS,
159 MX35_PAD_TXD1__UART1_TXD_MUX,
160 MX35_PAD_RXD1__UART1_RXD_MUX,
161 /* UART2 */
162 MX35_PAD_CTS2__UART2_CTS,
163 MX35_PAD_RTS2__UART2_RTS,
164 MX35_PAD_TXD2__UART2_TXD_MUX,
165 MX35_PAD_RXD2__UART2_RXD_MUX,
166 /* FEC */
167 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
168 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
169 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
170 MX35_PAD_FEC_COL__FEC_COL,
171 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
172 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
173 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
174 MX35_PAD_FEC_MDC__FEC_MDC,
175 MX35_PAD_FEC_MDIO__FEC_MDIO,
176 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
177 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
178 MX35_PAD_FEC_CRS__FEC_CRS,
179 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
180 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
181 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
182 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
183 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
184 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
185 /* I2C1 */
186 MX35_PAD_I2C1_CLK__I2C1_SCL,
187 MX35_PAD_I2C1_DAT__I2C1_SDA,
188 /* Display */
189 MX35_PAD_LD0__IPU_DISPB_DAT_0,
190 MX35_PAD_LD1__IPU_DISPB_DAT_1,
191 MX35_PAD_LD2__IPU_DISPB_DAT_2,
192 MX35_PAD_LD3__IPU_DISPB_DAT_3,
193 MX35_PAD_LD4__IPU_DISPB_DAT_4,
194 MX35_PAD_LD5__IPU_DISPB_DAT_5,
195 MX35_PAD_LD6__IPU_DISPB_DAT_6,
196 MX35_PAD_LD7__IPU_DISPB_DAT_7,
197 MX35_PAD_LD8__IPU_DISPB_DAT_8,
198 MX35_PAD_LD9__IPU_DISPB_DAT_9,
199 MX35_PAD_LD10__IPU_DISPB_DAT_10,
200 MX35_PAD_LD11__IPU_DISPB_DAT_11,
201 MX35_PAD_LD12__IPU_DISPB_DAT_12,
202 MX35_PAD_LD13__IPU_DISPB_DAT_13,
203 MX35_PAD_LD14__IPU_DISPB_DAT_14,
204 MX35_PAD_LD15__IPU_DISPB_DAT_15,
205 MX35_PAD_LD16__IPU_DISPB_DAT_16,
206 MX35_PAD_LD17__IPU_DISPB_DAT_17,
207 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
208 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
209 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
210 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
211 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
212 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
213 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
214 /* gpio */
215 MX35_PAD_ATA_CS0__GPIO2_6,
216 /* USB host */
217 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
218 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
219 /* SSI */
220 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
221 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
222 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
223 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
224};
225
226#define AC97_GPIO_TXFS (1 * 32 + 31)
227#define AC97_GPIO_TXD (1 * 32 + 28)
228#define AC97_GPIO_RESET (1 * 32 + 0)
229
230static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
231{
232 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
233 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
234 int ret;
235
236 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
237 if (ret) {
238 printk("failed to get GPIO_TXFS: %d\n", ret);
239 return;
240 }
241
242 mxc_iomux_v3_setup_pad(&txfs_gpio);
243
244 /* warm reset */
245 gpio_direction_output(AC97_GPIO_TXFS, 1);
246 udelay(2);
247 gpio_set_value(AC97_GPIO_TXFS, 0);
248
249 gpio_free(AC97_GPIO_TXFS);
250 mxc_iomux_v3_setup_pad(&txfs);
251}
252
253static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
254{
255 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
256 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
257 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
258 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
259 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
260 int ret;
261
262 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
263 if (ret)
264 goto err1;
265
266 ret = gpio_request(AC97_GPIO_TXD, "SSI");
267 if (ret)
268 goto err2;
269
270 ret = gpio_request(AC97_GPIO_RESET, "SSI");
271 if (ret)
272 goto err3;
273
274 mxc_iomux_v3_setup_pad(&txfs_gpio);
275 mxc_iomux_v3_setup_pad(&txd_gpio);
276 mxc_iomux_v3_setup_pad(&reset_gpio);
277
278 gpio_direction_output(AC97_GPIO_TXFS, 0);
279 gpio_direction_output(AC97_GPIO_TXD, 0);
280
281 /* cold reset */
282 gpio_direction_output(AC97_GPIO_RESET, 0);
283 udelay(10);
284 gpio_direction_output(AC97_GPIO_RESET, 1);
285
286 mxc_iomux_v3_setup_pad(&txd);
287 mxc_iomux_v3_setup_pad(&txfs);
288
289 gpio_free(AC97_GPIO_RESET);
290err3:
291 gpio_free(AC97_GPIO_TXD);
292err2:
293 gpio_free(AC97_GPIO_TXFS);
294err1:
295 if (ret)
296 printk("%s failed with %d\n", __func__, ret);
297 mdelay(1);
298}
299
300static struct imx_ssi_platform_data pcm043_ssi_pdata = {
301 .ac97_reset = pcm043_ac97_cold_reset,
302 .ac97_warm_reset = pcm043_ac97_warm_reset,
303 .flags = IMX_SSI_USE_AC97,
304};
305
306static struct mxc_nand_platform_data pcm037_nand_board_info = {
307 .width = 1,
308 .hw_ecc = 1,
309};
310
311static struct mxc_usbh_platform_data otg_pdata = {
312 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
314};
315
316static struct mxc_usbh_platform_data usbh1_pdata = {
317 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
319 MXC_EHCI_IPPUE_DOWN,
320};
321
322static struct fsl_usb2_platform_data otg_device_pdata = {
323 .operating_mode = FSL_USB2_DR_DEVICE,
324 .phy_mode = FSL_USB2_PHY_UTMI,
325};
326
327static int otg_mode_host;
328
329static int __init pcm043_otg_mode(char *options)
330{
331 if (!strcmp(options, "host"))
332 otg_mode_host = 1;
333 else if (!strcmp(options, "device"))
334 otg_mode_host = 0;
335 else
336 pr_info("otg_mode neither \"host\" nor \"device\". "
337 "Defaulting to device\n");
338 return 0;
339}
340__setup("otg_mode=", pcm043_otg_mode);
341
342/*
343 * Board specific initialization.
344 */
345static void __init mxc_board_init(void)
346{
347 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
348
349 mxc_audmux_v2_configure_port(3,
350 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
351 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
352 MXC_AUDMUX_V2_PTCR_TFSDIR,
353 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
354
355 mxc_audmux_v2_configure_port(0,
356 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
357 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
358 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
359 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
360
361 platform_add_devices(devices, ARRAY_SIZE(devices));
362
363 mxc_register_device(&mxc_uart_device0, &uart_pdata);
364 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
365 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
366
367 mxc_register_device(&mxc_uart_device1, &uart_pdata);
368
369#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
370 i2c_register_board_info(0, pcm043_i2c_devices,
371 ARRAY_SIZE(pcm043_i2c_devices));
372
373 mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
374#endif
375
376 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
377 mxc_register_device(&mx3_fb, &mx3fb_pdata);
378
379#if defined(CONFIG_USB_ULPI)
380 if (otg_mode_host) {
381 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
382 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
383
384 mxc_register_device(&mxc_otg_host, &otg_pdata);
385 }
386
387 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
388#endif
389 if (!otg_mode_host)
390 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
391
392}
393
394static void __init pcm043_timer_init(void)
395{
396 mx35_clocks_init();
397}
398
399struct sys_timer pcm043_timer = {
400 .init = pcm043_timer_init,
401};
402
403MACHINE_START(PCM043, "Phytec Phycore pcm043")
404 /* Maintainer: Pengutronix */
405 .phys_io = MX35_AIPS1_BASE_ADDR,
406 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
407 .boot_params = MX3x_PHYS_OFFSET + 0x100,
408 .map_io = mx35_map_io,
409 .init_irq = mx35_init_irq,
410 .init_machine = mxc_board_init,
411 .timer = &pcm043_timer,
412MACHINE_END
413
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