diff options
Diffstat (limited to 'arch/arm/mach-mx3/mach-mx31ads.c')
-rw-r--r-- | arch/arm/mach-mx3/mach-mx31ads.c | 55 |
1 files changed, 40 insertions, 15 deletions
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index b3d1a1895c20..94b3e7c42404 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c | |||
@@ -12,10 +12,6 @@ | |||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. | 14 | * GNU General Public License for more details. |
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | 15 | */ |
20 | 16 | ||
21 | #include <linux/types.h> | 17 | #include <linux/types.h> |
@@ -33,8 +29,6 @@ | |||
33 | #include <asm/memory.h> | 29 | #include <asm/memory.h> |
34 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
35 | #include <mach/common.h> | 31 | #include <mach/common.h> |
36 | #include <mach/board-mx31ads.h> | ||
37 | #include <mach/imx-uart.h> | ||
38 | #include <mach/iomux-mx3.h> | 32 | #include <mach/iomux-mx3.h> |
39 | 33 | ||
40 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | 34 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
@@ -43,14 +37,45 @@ | |||
43 | #include <linux/mfd/wm8350/pmic.h> | 37 | #include <linux/mfd/wm8350/pmic.h> |
44 | #endif | 38 | #endif |
45 | 39 | ||
40 | #include "devices-imx31.h" | ||
46 | #include "devices.h" | 41 | #include "devices.h" |
47 | 42 | ||
48 | /*! | 43 | /* Base address of PBC controller */ |
49 | * @file mx31ads.c | 44 | #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT |
50 | * | 45 | /* Offsets for the PBC Controller register */ |
51 | * @brief This file contains the board-specific initialization routines. | 46 | |
52 | * | 47 | /* PBC Board interrupt status register */ |
53 | * @ingroup System | 48 | #define PBC_INTSTATUS 0x000016 |
49 | |||
50 | /* PBC Board interrupt current status register */ | ||
51 | #define PBC_INTCURR_STATUS 0x000018 | ||
52 | |||
53 | /* PBC Interrupt mask register set address */ | ||
54 | #define PBC_INTMASK_SET 0x00001A | ||
55 | |||
56 | /* PBC Interrupt mask register clear address */ | ||
57 | #define PBC_INTMASK_CLEAR 0x00001C | ||
58 | |||
59 | /* External UART A */ | ||
60 | #define PBC_SC16C652_UARTA 0x010000 | ||
61 | |||
62 | /* External UART B */ | ||
63 | #define PBC_SC16C652_UARTB 0x010010 | ||
64 | |||
65 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) | ||
66 | #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) | ||
67 | #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) | ||
68 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) | ||
69 | |||
70 | #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) | ||
71 | #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) | ||
72 | |||
73 | #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) | ||
74 | #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) | ||
75 | |||
76 | #define MXC_MAX_EXP_IO_LINES 16 | ||
77 | /* | ||
78 | * This file contains the board-specific initialization routines. | ||
54 | */ | 79 | */ |
55 | 80 | ||
56 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | 81 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
@@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void) | |||
98 | #endif | 123 | #endif |
99 | 124 | ||
100 | #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) | 125 | #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) |
101 | static struct imxuart_platform_data uart_pdata = { | 126 | static const struct imxuart_platform_data uart_pdata __initconst = { |
102 | .flags = IMXUART_HAVE_RTSCTS, | 127 | .flags = IMXUART_HAVE_RTSCTS, |
103 | }; | 128 | }; |
104 | 129 | ||
@@ -112,7 +137,7 @@ static unsigned int uart_pins[] = { | |||
112 | static inline void mxc_init_imx_uart(void) | 137 | static inline void mxc_init_imx_uart(void) |
113 | { | 138 | { |
114 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); | 139 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
115 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 140 | imx31_add_imx_uart0(&uart_pdata); |
116 | } | 141 | } |
117 | #else /* !SERIAL_IMX */ | 142 | #else /* !SERIAL_IMX */ |
118 | static inline void mxc_init_imx_uart(void) | 143 | static inline void mxc_init_imx_uart(void) |
@@ -475,7 +500,7 @@ static void mxc_init_i2c(void) | |||
475 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); | 500 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); |
476 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); | 501 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); |
477 | 502 | ||
478 | mxc_register_device(&mxc_i2c_device1, NULL); | 503 | imx31_add_imx_i2c1(NULL); |
479 | } | 504 | } |
480 | #else | 505 | #else |
481 | static void mxc_init_i2c(void) | 506 | static void mxc_init_i2c(void) |