1 files changed, 111 insertions, 0 deletions

diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
new file mode 100644
index 000000000000..adc51feefc1d
--- /dev/null
+++ b/arch/arm/mach-mx3/iomux.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <asm/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux-mx3.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+#define IOMUXINT_OBS1   (IOMUX_BASE + 0x000)
+#define IOMUXINT_OBS2   (IOMUX_BASE + 0x004)
+#define IOMUXGPR        (IOMUX_BASE + 0x008)
+#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
+#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
+
+static DEFINE_SPINLOCK(gpio_mux_lock);
+
+#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int pin_mode)
+{
+        u32 reg, field, l, mode, ret = 0;
+
+        reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
+        field = pin_mode & 0x3;
+        mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
+
+        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
+                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 reg, field, l;
+
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
+        field = (pin + 2) % 3;
+
+        pr_debug("%s: reg offset = 0x%x field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 9));
+        l |= config << (field * 9);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
+{
+        u32 l;
+
+        spin_lock(&gpio_mux_lock);
+        l = __raw_readl(IOMUXGPR);
+        if (en)
+                l |= gp;
+        else
+                l &= ~gp;
+
+        __raw_writel(l, IOMUXGPR);
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_gpr);
+