diff options
Diffstat (limited to 'arch/arm/mach-mx3/devices.c')
-rw-r--r-- | arch/arm/mach-mx3/devices.c | 163 |
1 files changed, 146 insertions, 17 deletions
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index 9e87e08fb121..8a577f367250 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = { | |||
129 | 129 | ||
130 | /* GPIO port description */ | 130 | /* GPIO port description */ |
131 | static struct mxc_gpio_port imx_gpio_ports[] = { | 131 | static struct mxc_gpio_port imx_gpio_ports[] = { |
132 | [0] = { | 132 | { |
133 | .chip.label = "gpio-0", | 133 | .chip.label = "gpio-0", |
134 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | 134 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), |
135 | .irq = MXC_INT_GPIO1, | 135 | .irq = MXC_INT_GPIO1, |
136 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 136 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
137 | }, | 137 | }, { |
138 | [1] = { | ||
139 | .chip.label = "gpio-1", | 138 | .chip.label = "gpio-1", |
140 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | 139 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), |
141 | .irq = MXC_INT_GPIO2, | 140 | .irq = MXC_INT_GPIO2, |
142 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 141 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
143 | }, | 142 | }, { |
144 | [2] = { | ||
145 | .chip.label = "gpio-2", | 143 | .chip.label = "gpio-2", |
146 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | 144 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), |
147 | .irq = MXC_INT_GPIO3, | 145 | .irq = MXC_INT_GPIO3, |
@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = { | |||
173 | { | 171 | { |
174 | .start = 0, /* runtime dependent */ | 172 | .start = 0, /* runtime dependent */ |
175 | .end = 0, | 173 | .end = 0, |
176 | .flags = IORESOURCE_MEM | 174 | .flags = IORESOURCE_MEM, |
177 | }, { | 175 | }, { |
178 | .start = MXC_INT_NANDFC, | 176 | .start = MXC_INT_NANDFC, |
179 | .end = MXC_INT_NANDFC, | 177 | .end = MXC_INT_NANDFC, |
180 | .flags = IORESOURCE_IRQ | 178 | .flags = IORESOURCE_IRQ, |
181 | }, | 179 | }, |
182 | }; | 180 | }; |
183 | 181 | ||
@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = { | |||
193 | .start = I2C_BASE_ADDR, | 191 | .start = I2C_BASE_ADDR, |
194 | .end = I2C_BASE_ADDR + SZ_4K - 1, | 192 | .end = I2C_BASE_ADDR + SZ_4K - 1, |
195 | .flags = IORESOURCE_MEM, | 193 | .flags = IORESOURCE_MEM, |
196 | }, | 194 | }, { |
197 | { | ||
198 | .start = MXC_INT_I2C, | 195 | .start = MXC_INT_I2C, |
199 | .end = MXC_INT_I2C, | 196 | .end = MXC_INT_I2C, |
200 | .flags = IORESOURCE_IRQ, | 197 | .flags = IORESOURCE_IRQ, |
@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = { | |||
213 | .start = I2C2_BASE_ADDR, | 210 | .start = I2C2_BASE_ADDR, |
214 | .end = I2C2_BASE_ADDR + SZ_4K - 1, | 211 | .end = I2C2_BASE_ADDR + SZ_4K - 1, |
215 | .flags = IORESOURCE_MEM, | 212 | .flags = IORESOURCE_MEM, |
216 | }, | 213 | }, { |
217 | { | ||
218 | .start = MXC_INT_I2C2, | 214 | .start = MXC_INT_I2C2, |
219 | .end = MXC_INT_I2C2, | 215 | .end = MXC_INT_I2C2, |
220 | .flags = IORESOURCE_IRQ, | 216 | .flags = IORESOURCE_IRQ, |
@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = { | |||
233 | .start = I2C3_BASE_ADDR, | 229 | .start = I2C3_BASE_ADDR, |
234 | .end = I2C3_BASE_ADDR + SZ_4K - 1, | 230 | .end = I2C3_BASE_ADDR + SZ_4K - 1, |
235 | .flags = IORESOURCE_MEM, | 231 | .flags = IORESOURCE_MEM, |
236 | }, | 232 | }, { |
237 | { | ||
238 | .start = MXC_INT_I2C3, | 233 | .start = MXC_INT_I2C3, |
239 | .end = MXC_INT_I2C3, | 234 | .end = MXC_INT_I2C3, |
240 | .flags = IORESOURCE_IRQ, | 235 | .flags = IORESOURCE_IRQ, |
@@ -371,8 +366,8 @@ struct platform_device mx3_camera = { | |||
371 | 366 | ||
372 | static struct resource otg_resources[] = { | 367 | static struct resource otg_resources[] = { |
373 | { | 368 | { |
374 | .start = OTG_BASE_ADDR, | 369 | .start = MX31_OTG_BASE_ADDR, |
375 | .end = OTG_BASE_ADDR + 0x1ff, | 370 | .end = MX31_OTG_BASE_ADDR + 0x1ff, |
376 | .flags = IORESOURCE_MEM, | 371 | .flags = IORESOURCE_MEM, |
377 | }, { | 372 | }, { |
378 | .start = MXC_INT_USB3, | 373 | .start = MXC_INT_USB3, |
@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = { | |||
395 | .num_resources = ARRAY_SIZE(otg_resources), | 390 | .num_resources = ARRAY_SIZE(otg_resources), |
396 | }; | 391 | }; |
397 | 392 | ||
393 | /* OTG host */ | ||
394 | struct platform_device mxc_otg_host = { | ||
395 | .name = "mxc-ehci", | ||
396 | .id = 0, | ||
397 | .dev = { | ||
398 | .coherent_dma_mask = 0xffffffff, | ||
399 | .dma_mask = &otg_dmamask, | ||
400 | }, | ||
401 | .resource = otg_resources, | ||
402 | .num_resources = ARRAY_SIZE(otg_resources), | ||
403 | }; | ||
404 | |||
405 | /* USB host 1 */ | ||
406 | |||
407 | static u64 usbh1_dmamask = ~(u32)0; | ||
408 | |||
409 | static struct resource mxc_usbh1_resources[] = { | ||
410 | { | ||
411 | .start = MX31_OTG_BASE_ADDR + 0x200, | ||
412 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | ||
413 | .flags = IORESOURCE_MEM, | ||
414 | }, { | ||
415 | .start = MXC_INT_USB1, | ||
416 | .end = MXC_INT_USB1, | ||
417 | .flags = IORESOURCE_IRQ, | ||
418 | }, | ||
419 | }; | ||
420 | |||
421 | struct platform_device mxc_usbh1 = { | ||
422 | .name = "mxc-ehci", | ||
423 | .id = 1, | ||
424 | .dev = { | ||
425 | .coherent_dma_mask = 0xffffffff, | ||
426 | .dma_mask = &usbh1_dmamask, | ||
427 | }, | ||
428 | .resource = mxc_usbh1_resources, | ||
429 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | ||
430 | }; | ||
431 | |||
432 | /* USB host 2 */ | ||
433 | static u64 usbh2_dmamask = ~(u32)0; | ||
434 | |||
435 | static struct resource mxc_usbh2_resources[] = { | ||
436 | { | ||
437 | .start = MX31_OTG_BASE_ADDR + 0x400, | ||
438 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | ||
439 | .flags = IORESOURCE_MEM, | ||
440 | }, { | ||
441 | .start = MXC_INT_USB2, | ||
442 | .end = MXC_INT_USB2, | ||
443 | .flags = IORESOURCE_IRQ, | ||
444 | }, | ||
445 | }; | ||
446 | |||
447 | struct platform_device mxc_usbh2 = { | ||
448 | .name = "mxc-ehci", | ||
449 | .id = 2, | ||
450 | .dev = { | ||
451 | .coherent_dma_mask = 0xffffffff, | ||
452 | .dma_mask = &usbh2_dmamask, | ||
453 | }, | ||
454 | .resource = mxc_usbh2_resources, | ||
455 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | ||
456 | }; | ||
457 | |||
458 | /* | ||
459 | * SPI master controller | ||
460 | * 3 channels | ||
461 | */ | ||
462 | static struct resource imx_spi_0_resources[] = { | ||
463 | { | ||
464 | .start = CSPI1_BASE_ADDR, | ||
465 | .end = CSPI1_BASE_ADDR + SZ_4K - 1, | ||
466 | .flags = IORESOURCE_MEM, | ||
467 | }, { | ||
468 | .start = MXC_INT_CSPI1, | ||
469 | .end = MXC_INT_CSPI1, | ||
470 | .flags = IORESOURCE_IRQ, | ||
471 | }, | ||
472 | }; | ||
473 | |||
474 | static struct resource imx_spi_1_resources[] = { | ||
475 | { | ||
476 | .start = CSPI2_BASE_ADDR, | ||
477 | .end = CSPI2_BASE_ADDR + SZ_4K - 1, | ||
478 | .flags = IORESOURCE_MEM, | ||
479 | }, { | ||
480 | .start = MXC_INT_CSPI2, | ||
481 | .end = MXC_INT_CSPI2, | ||
482 | .flags = IORESOURCE_IRQ, | ||
483 | }, | ||
484 | }; | ||
485 | |||
486 | static struct resource imx_spi_2_resources[] = { | ||
487 | { | ||
488 | .start = CSPI3_BASE_ADDR, | ||
489 | .end = CSPI3_BASE_ADDR + SZ_4K - 1, | ||
490 | .flags = IORESOURCE_MEM, | ||
491 | }, { | ||
492 | .start = MXC_INT_CSPI3, | ||
493 | .end = MXC_INT_CSPI3, | ||
494 | .flags = IORESOURCE_IRQ, | ||
495 | }, | ||
496 | }; | ||
497 | |||
498 | struct platform_device imx_spi_device0 = { | ||
499 | .name = "spi_imx", | ||
500 | .id = 0, | ||
501 | .num_resources = ARRAY_SIZE(imx_spi_0_resources), | ||
502 | .resource = imx_spi_0_resources, | ||
503 | }; | ||
504 | |||
505 | struct platform_device imx_spi_device1 = { | ||
506 | .name = "spi_imx", | ||
507 | .id = 1, | ||
508 | .num_resources = ARRAY_SIZE(imx_spi_1_resources), | ||
509 | .resource = imx_spi_1_resources, | ||
510 | }; | ||
511 | |||
512 | struct platform_device imx_spi_device2 = { | ||
513 | .name = "spi_imx", | ||
514 | .id = 2, | ||
515 | .num_resources = ARRAY_SIZE(imx_spi_2_resources), | ||
516 | .resource = imx_spi_2_resources, | ||
517 | }; | ||
518 | |||
398 | #ifdef CONFIG_ARCH_MX35 | 519 | #ifdef CONFIG_ARCH_MX35 |
399 | static struct resource mxc_fec_resources[] = { | 520 | static struct resource mxc_fec_resources[] = { |
400 | { | 521 | { |
401 | .start = MXC_FEC_BASE_ADDR, | 522 | .start = MXC_FEC_BASE_ADDR, |
402 | .end = MXC_FEC_BASE_ADDR + 0xfff, | 523 | .end = MXC_FEC_BASE_ADDR + 0xfff, |
403 | .flags = IORESOURCE_MEM | 524 | .flags = IORESOURCE_MEM, |
404 | }, { | 525 | }, { |
405 | .start = MXC_INT_FEC, | 526 | .start = MXC_INT_FEC, |
406 | .end = MXC_INT_FEC, | 527 | .end = MXC_INT_FEC, |
407 | .flags = IORESOURCE_IRQ | 528 | .flags = IORESOURCE_IRQ, |
408 | }, | 529 | }, |
409 | }; | 530 | }; |
410 | 531 | ||
@@ -426,6 +547,14 @@ static int mx3_devices_init(void) | |||
426 | if (cpu_is_mx35()) { | 547 | if (cpu_is_mx35()) { |
427 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; | 548 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; |
428 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; | 549 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; |
550 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | ||
551 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | ||
552 | otg_resources[1].start = MXC_INT_USBOTG; | ||
553 | otg_resources[1].end = MXC_INT_USBOTG; | ||
554 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | ||
555 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | ||
556 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | ||
557 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | ||
429 | } | 558 | } |
430 | 559 | ||
431 | return 0; | 560 | return 0; |