diff options
Diffstat (limited to 'arch/arm/mach-mx3/crm_regs.h')
-rw-r--r-- | arch/arm/mach-mx3/crm_regs.h | 401 |
1 files changed, 401 insertions, 0 deletions
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h new file mode 100644 index 000000000000..4a0e0ede23bb --- /dev/null +++ b/arch/arm/mach-mx3/crm_regs.h | |||
@@ -0,0 +1,401 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version 2 | ||
8 | * of the License, or (at your option) any later version. | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
17 | * MA 02110-1301, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ | ||
21 | #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ | ||
22 | |||
23 | #define CKIH_CLK_FREQ 26000000 | ||
24 | #define CKIH_CLK_FREQ_27MHZ 27000000 | ||
25 | #define CKIL_CLK_FREQ 32768 | ||
26 | |||
27 | #define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) | ||
28 | |||
29 | /* Register addresses */ | ||
30 | #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) | ||
31 | #define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) | ||
32 | #define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) | ||
33 | #define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) | ||
34 | #define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) | ||
35 | #define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) | ||
36 | #define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) | ||
37 | #define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) | ||
38 | #define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) | ||
39 | #define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) | ||
40 | #define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) | ||
41 | #define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) | ||
42 | #define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) | ||
43 | #define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) | ||
44 | #define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) | ||
45 | #define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) | ||
46 | #define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) | ||
47 | #define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44) | ||
48 | #define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48) | ||
49 | #define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C) | ||
50 | #define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50) | ||
51 | #define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54) | ||
52 | #define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58) | ||
53 | #define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C) | ||
54 | #define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60) | ||
55 | #define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) | ||
56 | |||
57 | /* Register bit definitions */ | ||
58 | #define MXC_CCM_CCMR_WBEN (1 << 27) | ||
59 | #define MXC_CCM_CCMR_CSCS (1 << 25) | ||
60 | #define MXC_CCM_CCMR_PERCS (1 << 24) | ||
61 | #define MXC_CCM_CCMR_SSI1S_OFFSET 18 | ||
62 | #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) | ||
63 | #define MXC_CCM_CCMR_SSI2S_OFFSET 21 | ||
64 | #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) | ||
65 | #define MXC_CCM_CCMR_LPM_OFFSET 14 | ||
66 | #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) | ||
67 | #define MXC_CCM_CCMR_FIRS_OFFSET 11 | ||
68 | #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) | ||
69 | #define MXC_CCM_CCMR_UPE (1 << 9) | ||
70 | #define MXC_CCM_CCMR_SPE (1 << 8) | ||
71 | #define MXC_CCM_CCMR_MDS (1 << 7) | ||
72 | #define MXC_CCM_CCMR_SBYCS (1 << 4) | ||
73 | #define MXC_CCM_CCMR_MPE (1 << 3) | ||
74 | #define MXC_CCM_CCMR_PRCS_OFFSET 1 | ||
75 | #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) | ||
76 | |||
77 | #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 | ||
78 | #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) | ||
79 | #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 | ||
80 | #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) | ||
81 | #define MXC_CCM_PDR0_PER_PODF_OFFSET 16 | ||
82 | #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) | ||
83 | #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 | ||
84 | #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) | ||
85 | #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 | ||
86 | #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) | ||
87 | #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 | ||
88 | #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) | ||
89 | #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 | ||
90 | #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) | ||
91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 | ||
92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 | ||
93 | |||
94 | #define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) | ||
95 | #define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) | ||
96 | #define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) | ||
97 | #define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) | ||
98 | #define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) | ||
99 | #define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) | ||
100 | #define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) | ||
101 | #define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) | ||
102 | |||
103 | #define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) | ||
104 | #define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) | ||
105 | #define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) | ||
106 | #define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) | ||
107 | |||
108 | #define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) | ||
109 | #define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) | ||
110 | #define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) | ||
111 | #define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) | ||
112 | #define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) | ||
113 | #define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) | ||
114 | #define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) | ||
115 | #define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) | ||
116 | |||
117 | #define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) | ||
118 | #define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) | ||
119 | #define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) | ||
120 | #define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) | ||
121 | #define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) | ||
122 | #define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) | ||
123 | #define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) | ||
124 | #define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) | ||
125 | |||
126 | #define MXC_CCM_PDR0_MCU_DIV_1 0x0 | ||
127 | #define MXC_CCM_PDR0_MCU_DIV_2 0x1 | ||
128 | #define MXC_CCM_PDR0_MCU_DIV_3 0x2 | ||
129 | #define MXC_CCM_PDR0_MCU_DIV_4 0x3 | ||
130 | #define MXC_CCM_PDR0_MCU_DIV_5 0x4 | ||
131 | #define MXC_CCM_PDR0_MCU_DIV_6 0x5 | ||
132 | #define MXC_CCM_PDR0_MCU_DIV_7 0x6 | ||
133 | #define MXC_CCM_PDR0_MCU_DIV_8 0x7 | ||
134 | |||
135 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 | ||
136 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) | ||
137 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 | ||
138 | #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) | ||
139 | #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 | ||
140 | #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) | ||
141 | #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 | ||
142 | #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) | ||
143 | #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 | ||
144 | #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) | ||
145 | #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 | ||
146 | #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) | ||
147 | #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 | ||
148 | #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) | ||
149 | #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 | ||
150 | #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F | ||
151 | |||
152 | /* Bit definitions for RCSR */ | ||
153 | #define MXC_CCM_RCSR_NF16B 0x80000000 | ||
154 | |||
155 | /* Bit definitions for both MCU, USB and SR PLL control registers */ | ||
156 | #define MXC_CCM_PCTL_BRM 0x80000000 | ||
157 | #define MXC_CCM_PCTL_PD_OFFSET 26 | ||
158 | #define MXC_CCM_PCTL_PD_MASK (0xF << 26) | ||
159 | #define MXC_CCM_PCTL_MFD_OFFSET 16 | ||
160 | #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) | ||
161 | #define MXC_CCM_PCTL_MFI_OFFSET 10 | ||
162 | #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) | ||
163 | #define MXC_CCM_PCTL_MFN_OFFSET 0 | ||
164 | #define MXC_CCM_PCTL_MFN_MASK 0x3FF | ||
165 | |||
166 | #define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 | ||
167 | #define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) | ||
168 | #define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 | ||
169 | #define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) | ||
170 | #define MXC_CCM_CGR0_GPT_OFFSET 4 | ||
171 | #define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) | ||
172 | #define MXC_CCM_CGR0_EPIT1_OFFSET 6 | ||
173 | #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) | ||
174 | #define MXC_CCM_CGR0_EPIT2_OFFSET 8 | ||
175 | #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) | ||
176 | #define MXC_CCM_CGR0_IIM_OFFSET 10 | ||
177 | #define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) | ||
178 | #define MXC_CCM_CGR0_ATA_OFFSET 12 | ||
179 | #define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) | ||
180 | #define MXC_CCM_CGR0_SDMA_OFFSET 14 | ||
181 | #define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) | ||
182 | #define MXC_CCM_CGR0_CSPI3_OFFSET 16 | ||
183 | #define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) | ||
184 | #define MXC_CCM_CGR0_RNG_OFFSET 18 | ||
185 | #define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) | ||
186 | #define MXC_CCM_CGR0_UART1_OFFSET 20 | ||
187 | #define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) | ||
188 | #define MXC_CCM_CGR0_UART2_OFFSET 22 | ||
189 | #define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) | ||
190 | #define MXC_CCM_CGR0_SSI1_OFFSET 24 | ||
191 | #define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) | ||
192 | #define MXC_CCM_CGR0_I2C1_OFFSET 26 | ||
193 | #define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) | ||
194 | #define MXC_CCM_CGR0_I2C2_OFFSET 28 | ||
195 | #define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) | ||
196 | #define MXC_CCM_CGR0_I2C3_OFFSET 30 | ||
197 | #define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) | ||
198 | |||
199 | #define MXC_CCM_CGR1_HANTRO_OFFSET 0 | ||
200 | #define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) | ||
201 | #define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 | ||
202 | #define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) | ||
203 | #define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 | ||
204 | #define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) | ||
205 | #define MXC_CCM_CGR1_CSI_OFFSET 6 | ||
206 | #define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) | ||
207 | #define MXC_CCM_CGR1_RTC_OFFSET 8 | ||
208 | #define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) | ||
209 | #define MXC_CCM_CGR1_WDOG_OFFSET 10 | ||
210 | #define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) | ||
211 | #define MXC_CCM_CGR1_PWM_OFFSET 12 | ||
212 | #define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) | ||
213 | #define MXC_CCM_CGR1_SIM_OFFSET 14 | ||
214 | #define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) | ||
215 | #define MXC_CCM_CGR1_ECT_OFFSET 16 | ||
216 | #define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) | ||
217 | #define MXC_CCM_CGR1_USBOTG_OFFSET 18 | ||
218 | #define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) | ||
219 | #define MXC_CCM_CGR1_KPP_OFFSET 20 | ||
220 | #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) | ||
221 | #define MXC_CCM_CGR1_IPU_OFFSET 22 | ||
222 | #define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) | ||
223 | #define MXC_CCM_CGR1_UART3_OFFSET 24 | ||
224 | #define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) | ||
225 | #define MXC_CCM_CGR1_UART4_OFFSET 26 | ||
226 | #define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) | ||
227 | #define MXC_CCM_CGR1_UART5_OFFSET 28 | ||
228 | #define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) | ||
229 | #define MXC_CCM_CGR1_OWIRE_OFFSET 30 | ||
230 | #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) | ||
231 | |||
232 | #define MXC_CCM_CGR2_SSI2_OFFSET 0 | ||
233 | #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) | ||
234 | #define MXC_CCM_CGR2_CSPI1_OFFSET 2 | ||
235 | #define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) | ||
236 | #define MXC_CCM_CGR2_CSPI2_OFFSET 4 | ||
237 | #define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) | ||
238 | #define MXC_CCM_CGR2_GACC_OFFSET 6 | ||
239 | #define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) | ||
240 | #define MXC_CCM_CGR2_EMI_OFFSET 8 | ||
241 | #define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) | ||
242 | #define MXC_CCM_CGR2_RTIC_OFFSET 10 | ||
243 | #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) | ||
244 | #define MXC_CCM_CGR2_FIRI_OFFSET 12 | ||
245 | #define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) | ||
246 | #define MXC_CCM_CGR2_IPMUX1_OFFSET 14 | ||
247 | #define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) | ||
248 | #define MXC_CCM_CGR2_IPMUX2_OFFSET 16 | ||
249 | #define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) | ||
250 | |||
251 | /* These new CGR2 bits are added in MX32 */ | ||
252 | #define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 | ||
253 | #define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) | ||
254 | #define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 | ||
255 | #define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) | ||
256 | #define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 | ||
257 | #define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) | ||
258 | #define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 | ||
259 | #define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) | ||
260 | #define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 | ||
261 | #define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) | ||
262 | #define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 | ||
263 | #define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) | ||
264 | #define MXC_CCM_CGR2_APMENA_OFFSET 30 | ||
265 | #define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) | ||
266 | |||
267 | /* | ||
268 | * LTR0 register offsets | ||
269 | */ | ||
270 | #define MXC_CCM_LTR0_DIV3CK_OFFSET 1 | ||
271 | #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) | ||
272 | #define MXC_CCM_LTR0_DNTHR_OFFSET 16 | ||
273 | #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) | ||
274 | #define MXC_CCM_LTR0_UPTHR_OFFSET 22 | ||
275 | #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) | ||
276 | |||
277 | /* | ||
278 | * LTR1 register offsets | ||
279 | */ | ||
280 | #define MXC_CCM_LTR1_PNCTHR_OFFSET 0 | ||
281 | #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F | ||
282 | #define MXC_CCM_LTR1_UPCNT_OFFSET 6 | ||
283 | #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) | ||
284 | #define MXC_CCM_LTR1_DNCNT_OFFSET 14 | ||
285 | #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) | ||
286 | #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 | ||
287 | #define MXC_CCM_LTR1_LTBRSR_OFFSET 22 | ||
288 | #define MXC_CCM_LTR1_LTBRSR 0x400000 | ||
289 | #define MXC_CCM_LTR1_LTBRSH 0x800000 | ||
290 | |||
291 | /* | ||
292 | * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 | ||
293 | */ | ||
294 | #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) | ||
295 | #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ | ||
296 | MXC_CCM_LTR2_WSW_OFFSET((x))) | ||
297 | #define MXC_CCM_LTR2_EMAC_OFFSET 0 | ||
298 | #define MXC_CCM_LTR2_EMAC_MASK 0x1FF | ||
299 | |||
300 | /* | ||
301 | * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 | ||
302 | */ | ||
303 | #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) | ||
304 | #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ | ||
305 | MXC_CCM_LTR3_WSW_OFFSET((x))) | ||
306 | |||
307 | #define MXC_CCM_PMCR0_DFSUP1 0x80000000 | ||
308 | #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) | ||
309 | #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) | ||
310 | #define MXC_CCM_PMCR0_DFSUP0 0x40000000 | ||
311 | #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) | ||
312 | #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) | ||
313 | #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) | ||
314 | |||
315 | #define DVSUP_TURBO 0 | ||
316 | #define DVSUP_HIGH 1 | ||
317 | #define DVSUP_MEDIUM 2 | ||
318 | #define DVSUP_LOW 3 | ||
319 | #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) | ||
320 | #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) | ||
321 | #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) | ||
322 | #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) | ||
323 | #define MXC_CCM_PMCR0_DVSUP_OFFSET 28 | ||
324 | #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) | ||
325 | #define MXC_CCM_PMCR0_UDSC 0x08000000 | ||
326 | #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) | ||
327 | #define MXC_CCM_PMCR0_UDSC_UP (1 << 27) | ||
328 | #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) | ||
329 | |||
330 | #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) | ||
331 | #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) | ||
332 | #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) | ||
333 | #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) | ||
334 | #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) | ||
335 | #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) | ||
336 | #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) | ||
337 | #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) | ||
338 | #define MXC_CCM_PMCR0_VSCNT_OFFSET 24 | ||
339 | #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) | ||
340 | #define MXC_CCM_PMCR0_DVFEV 0x00800000 | ||
341 | #define MXC_CCM_PMCR0_DVFIS 0x00400000 | ||
342 | #define MXC_CCM_PMCR0_LBMI 0x00200000 | ||
343 | #define MXC_CCM_PMCR0_LBFL 0x00100000 | ||
344 | #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) | ||
345 | #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) | ||
346 | #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) | ||
347 | #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) | ||
348 | #define MXC_CCM_PMCR0_LBCF_OFFSET 18 | ||
349 | #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) | ||
350 | #define MXC_CCM_PMCR0_PTVIS 0x00020000 | ||
351 | #define MXC_CCM_PMCR0_UPDTEN 0x00010000 | ||
352 | #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) | ||
353 | #define MXC_CCM_PMCR0_FSVAIM 0x00008000 | ||
354 | #define MXC_CCM_PMCR0_FSVAI_OFFSET 13 | ||
355 | #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) | ||
356 | #define MXC_CCM_PMCR0_DPVCR 0x00001000 | ||
357 | #define MXC_CCM_PMCR0_DPVV 0x00000800 | ||
358 | #define MXC_CCM_PMCR0_WFIM 0x00000400 | ||
359 | #define MXC_CCM_PMCR0_DRCE3 0x00000200 | ||
360 | #define MXC_CCM_PMCR0_DRCE2 0x00000100 | ||
361 | #define MXC_CCM_PMCR0_DRCE1 0x00000080 | ||
362 | #define MXC_CCM_PMCR0_DRCE0 0x00000040 | ||
363 | #define MXC_CCM_PMCR0_DCR 0x00000020 | ||
364 | #define MXC_CCM_PMCR0_DVFEN 0x00000010 | ||
365 | #define MXC_CCM_PMCR0_PTVAIM 0x00000008 | ||
366 | #define MXC_CCM_PMCR0_PTVAI_OFFSET 1 | ||
367 | #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) | ||
368 | #define MXC_CCM_PMCR0_DPTEN 0x00000001 | ||
369 | |||
370 | #define MXC_CCM_PMCR1_DVGP_OFFSET 0 | ||
371 | #define MXC_CCM_PMCR1_DVGP_MASK (0xF) | ||
372 | |||
373 | #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) | ||
374 | #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) | ||
375 | |||
376 | #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) | ||
377 | #define MXC_CCM_DCVR_ULV_OFFSET 22 | ||
378 | #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) | ||
379 | #define MXC_CCM_DCVR_LLV_OFFSET 12 | ||
380 | #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) | ||
381 | #define MXC_CCM_DCVR_ELV_OFFSET 2 | ||
382 | |||
383 | #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) | ||
384 | #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 | ||
385 | #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F | ||
386 | #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 | ||
387 | |||
388 | #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F | ||
389 | #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 | ||
390 | #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) | ||
391 | #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 | ||
392 | #define MXC_CCM_COSR_CLKOEN (1 << 9) | ||
393 | |||
394 | /* | ||
395 | * PMCR0 register offsets | ||
396 | */ | ||
397 | #define MXC_CCM_PMCR0_LBFL_OFFSET 20 | ||
398 | #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 | ||
399 | #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 | ||
400 | |||
401 | #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ | ||