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Diffstat (limited to 'arch/arm/mach-mx3/clock-imx35.c')
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c46
1 files changed, 39 insertions, 7 deletions
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index c595260ec1f9..7584b4c6c556 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk)
335 335
336DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); 336DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
337DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); 337DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
338DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); 338/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
339DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); 339DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
340DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); 340DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
341DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); 341DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
@@ -381,12 +381,43 @@ DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
381DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); 381DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
382DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); 382DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
383DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); 383DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
384DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); 384DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
385 385
386DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); 386DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
387DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); 387DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
388DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); 388DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
389 389
390DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
391
392static int clk_dummy_enable(struct clk *clk)
393{
394 return 0;
395}
396
397static void clk_dummy_disable(struct clk *clk)
398{
399}
400
401static unsigned long get_rate_nfc(struct clk *clk)
402{
403 unsigned long div1;
404
405 div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
406
407 return get_rate_ahb(NULL) / div1;
408}
409
410/* NAND Controller: It seems it can't be disabled */
411static struct clk nfc_clk = {
412 .id = 0,
413 .enable_reg = 0,
414 .enable_shift = 0,
415 .get_rate = get_rate_nfc,
416 .set_rate = NULL, /* set_rate_nfc, */
417 .enable = clk_dummy_enable,
418 .disable = clk_dummy_disable
419};
420
390#define _REGISTER_CLOCK(d, n, c) \ 421#define _REGISTER_CLOCK(d, n, c) \
391 { \ 422 { \
392 .dev_id = d, \ 423 .dev_id = d, \
@@ -397,7 +428,6 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
397static struct clk_lookup lookups[] = { 428static struct clk_lookup lookups[] = {
398 _REGISTER_CLOCK(NULL, "asrc", asrc_clk) 429 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
399 _REGISTER_CLOCK(NULL, "ata", ata_clk) 430 _REGISTER_CLOCK(NULL, "ata", ata_clk)
400 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
401 _REGISTER_CLOCK(NULL, "can", can1_clk) 431 _REGISTER_CLOCK(NULL, "can", can1_clk)
402 _REGISTER_CLOCK(NULL, "can", can2_clk) 432 _REGISTER_CLOCK(NULL, "can", can2_clk)
403 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 433 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
@@ -434,8 +464,8 @@ static struct clk_lookup lookups[] = {
434 _REGISTER_CLOCK(NULL, "sdma", sdma_clk) 464 _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
435 _REGISTER_CLOCK(NULL, "spba", spba_clk) 465 _REGISTER_CLOCK(NULL, "spba", spba_clk)
436 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 466 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
437 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) 467 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
438 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) 468 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
439 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) 469 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
440 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) 470 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
441 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 471 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -443,12 +473,14 @@ static struct clk_lookup lookups[] = {
443 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) 473 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
444 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 474 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
445 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) 475 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
476 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
446 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 477 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
447 _REGISTER_CLOCK(NULL, "max", max_clk) 478 _REGISTER_CLOCK(NULL, "max", max_clk)
448 _REGISTER_CLOCK(NULL, "admux", admux_clk) 479 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
449 _REGISTER_CLOCK(NULL, "csi", csi_clk) 480 _REGISTER_CLOCK(NULL, "csi", csi_clk)
450 _REGISTER_CLOCK(NULL, "iim", iim_clk) 481 _REGISTER_CLOCK(NULL, "iim", iim_clk)
451 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) 482 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
483 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
452}; 484};
453 485
454int __init mx35_clocks_init() 486int __init mx35_clocks_init()
@@ -456,7 +488,7 @@ int __init mx35_clocks_init()
456 int i; 488 int i;
457 unsigned int ll = 0; 489 unsigned int ll = 0;
458 490
459#ifdef CONFIG_DEBUG_LL_CONSOLE 491#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
460 ll = (3 << 16); 492 ll = (3 << 16);
461#endif 493#endif
462 494