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-rw-r--r--arch/arm/mach-mx2/Kconfig10
-rw-r--r--arch/arm/mach-mx2/Makefile23
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c236
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c33
-rw-r--r--arch/arm/mach-mx2/cpu_imx27.c3
-rw-r--r--arch/arm/mach-mx2/crm_regs.h258
-rw-r--r--arch/arm/mach-mx2/devices.c640
-rw-r--r--arch/arm/mach-mx2/devices.h13
-rw-r--r--arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c2
-rw-r--r--arch/arm/mach-mx2/mach-cpuimx27.c (renamed from arch/arm/mach-mx2/eukrea_cpuimx27.c)19
-rw-r--r--arch/arm/mach-mx2/mach-imx27lite.c (renamed from arch/arm/mach-mx2/mx27lite.c)8
-rw-r--r--arch/arm/mach-mx2/mach-mx21ads.c (renamed from arch/arm/mach-mx2/mx21ads.c)16
-rw-r--r--arch/arm/mach-mx2/mach-mx27_3ds.c (renamed from arch/arm/mach-mx2/mx27pdk.c)8
-rw-r--r--arch/arm/mach-mx2/mach-mx27ads.c (renamed from arch/arm/mach-mx2/mx27ads.c)12
-rw-r--r--arch/arm/mach-mx2/mach-mxt_td60.c (renamed from arch/arm/mach-mx2/mxt_td60.c)10
-rw-r--r--arch/arm/mach-mx2/mach-pca100.c (renamed from arch/arm/mach-mx2/pca100.c)161
-rw-r--r--arch/arm/mach-mx2/mach-pcm038.c (renamed from arch/arm/mach-mx2/pcm038.c)40
-rw-r--r--arch/arm/mach-mx2/mm-imx21.c83
-rw-r--r--arch/arm/mach-mx2/mm-imx27.c (renamed from arch/arm/mach-mx2/generic.c)44
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c6
-rw-r--r--arch/arm/mach-mx2/serial.c48
21 files changed, 870 insertions, 803 deletions
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index b96c6a389363..742fd4e6dcb9 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -37,6 +37,7 @@ config MACH_MX27ADS
37config MACH_PCM038 37config MACH_PCM038
38 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" 38 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
39 depends on MACH_MX27 39 depends on MACH_MX27
40 select MXC_ULPI if USB_ULPI
40 help 41 help
41 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 42 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
42 includes specific configurations for the module and its peripherals. 43 includes specific configurations for the module and its peripherals.
@@ -55,7 +56,7 @@ config MACH_PCM970_BASEBOARD
55 56
56endchoice 57endchoice
57 58
58config MACH_EUKREA_CPUIMX27 59config MACH_CPUIMX27
59 bool "Eukrea CPUIMX27 module" 60 bool "Eukrea CPUIMX27 module"
60 depends on MACH_MX27 61 depends on MACH_MX27
61 help 62 help
@@ -64,14 +65,14 @@ config MACH_EUKREA_CPUIMX27
64 65
65config MACH_EUKREA_CPUIMX27_USESDHC2 66config MACH_EUKREA_CPUIMX27_USESDHC2
66 bool "CPUIMX27 integrates SDHC2 module" 67 bool "CPUIMX27 integrates SDHC2 module"
67 depends on MACH_EUKREA_CPUIMX27 68 depends on MACH_CPUIMX27
68 help 69 help
69 This adds support for the internal SDHC2 used on CPUIMX27 used 70 This adds support for the internal SDHC2 used on CPUIMX27 used
70 for wifi or eMMC. 71 for wifi or eMMC.
71 72
72choice 73choice
73 prompt "Baseboard" 74 prompt "Baseboard"
74 depends on MACH_EUKREA_CPUIMX27 75 depends on MACH_CPUIMX27
75 default MACH_EUKREA_MBIMX27_BASEBOARD 76 default MACH_EUKREA_MBIMX27_BASEBOARD
76 77
77config MACH_EUKREA_MBIMX27_BASEBOARD 78config MACH_EUKREA_MBIMX27_BASEBOARD
@@ -90,7 +91,7 @@ config MACH_MX27_3DS
90 Include support for MX27PDK platform. This includes specific 91 Include support for MX27PDK platform. This includes specific
91 configurations for the board and its peripherals. 92 configurations for the board and its peripherals.
92 93
93config MACH_MX27LITE 94config MACH_IMX27LITE
94 bool "LogicPD MX27 LITEKIT platform" 95 bool "LogicPD MX27 LITEKIT platform"
95 depends on MACH_MX27 96 depends on MACH_MX27
96 help 97 help
@@ -100,6 +101,7 @@ config MACH_MX27LITE
100config MACH_PCA100 101config MACH_PCA100
101 bool "Phytec phyCARD-s (pca100)" 102 bool "Phytec phyCARD-s (pca100)"
102 depends on MACH_MX27 103 depends on MACH_MX27
104 select MXC_ULPI if USB_ULPI
103 help 105 help
104 Include support for phyCARD-s (aka pca100) platform. This 106 Include support for phyCARD-s (aka pca100) platform. This
105 includes specific configurations for the module and its peripherals. 107 includes specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 52aca0aaf9b5..e3254faac828 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -4,21 +4,20 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := generic.o devices.o serial.o 7obj-y := devices.o serial.o
8 8
9obj-$(CONFIG_MACH_MX21) += clock_imx21.o 9obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
10 10
11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
12obj-$(CONFIG_MACH_MX27) += clock_imx27.o 12obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
13 13
14obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o 14obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
15obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o 15obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
16obj-$(CONFIG_MACH_PCM038) += pcm038.o 16obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
18obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o 18obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
19obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o 19obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
20obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o 20obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
21obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o 21obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
22obj-$(CONFIG_MACH_PCA100) += pca100.o 22obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
23obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o 23obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
24
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index e82b489d1215..bb419ef4d133 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -23,11 +23,242 @@
23#include <linux/module.h> 23#include <linux/module.h>
24 24
25#include <mach/clock.h> 25#include <mach/clock.h>
26#include <mach/hardware.h>
26#include <mach/common.h> 27#include <mach/common.h>
27#include <asm/clkdev.h> 28#include <asm/clkdev.h>
28#include <asm/div64.h> 29#include <asm/div64.h>
29 30
30#include "crm_regs.h" 31#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
32
33/* Register offsets */
34#define CCM_CSCR IO_ADDR_CCM(0x0)
35#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
36#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
37#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
38#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
39#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
40#define CCM_PCDR0 IO_ADDR_CCM(0x18)
41#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
42#define CCM_PCCR0 IO_ADDR_CCM(0x20)
43#define CCM_PCCR1 IO_ADDR_CCM(0x24)
44#define CCM_CCSR IO_ADDR_CCM(0x28)
45#define CCM_PMCTL IO_ADDR_CCM(0x2c)
46#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
47#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
48
49#define CCM_CSCR_PRESC_OFFSET 29
50#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
51
52#define CCM_CSCR_USB_OFFSET 26
53#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
54#define CCM_CSCR_SD_OFFSET 24
55#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
56#define CCM_CSCR_SPLLRES (1 << 22)
57#define CCM_CSCR_MPLLRES (1 << 21)
58#define CCM_CSCR_SSI2_OFFSET 20
59#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
60#define CCM_CSCR_SSI1_OFFSET 19
61#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
62#define CCM_CSCR_FIR_OFFSET 18
63#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
64#define CCM_CSCR_SP (1 << 17)
65#define CCM_CSCR_MCU (1 << 16)
66#define CCM_CSCR_BCLK_OFFSET 10
67#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
68#define CCM_CSCR_IPDIV_OFFSET 9
69#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
70
71#define CCM_CSCR_OSC26MDIV (1 << 4)
72#define CCM_CSCR_OSC26M (1 << 3)
73#define CCM_CSCR_FPM (1 << 2)
74#define CCM_CSCR_SPEN (1 << 1)
75#define CCM_CSCR_MPEN 1
76
77#define CCM_MPCTL0_CPLM (1 << 31)
78#define CCM_MPCTL0_PD_OFFSET 26
79#define CCM_MPCTL0_PD_MASK (0xf << 26)
80#define CCM_MPCTL0_MFD_OFFSET 16
81#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
82#define CCM_MPCTL0_MFI_OFFSET 10
83#define CCM_MPCTL0_MFI_MASK (0xf << 10)
84#define CCM_MPCTL0_MFN_OFFSET 0
85#define CCM_MPCTL0_MFN_MASK 0x3ff
86
87#define CCM_MPCTL1_LF (1 << 15)
88#define CCM_MPCTL1_BRMO (1 << 6)
89
90#define CCM_SPCTL0_CPLM (1 << 31)
91#define CCM_SPCTL0_PD_OFFSET 26
92#define CCM_SPCTL0_PD_MASK (0xf << 26)
93#define CCM_SPCTL0_MFD_OFFSET 16
94#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
95#define CCM_SPCTL0_MFI_OFFSET 10
96#define CCM_SPCTL0_MFI_MASK (0xf << 10)
97#define CCM_SPCTL0_MFN_OFFSET 0
98#define CCM_SPCTL0_MFN_MASK 0x3ff
99
100#define CCM_SPCTL1_LF (1 << 15)
101#define CCM_SPCTL1_BRMO (1 << 6)
102
103#define CCM_OSC26MCTL_PEAK_OFFSET 16
104#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
105#define CCM_OSC26MCTL_AGC_OFFSET 8
106#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
107#define CCM_OSC26MCTL_ANATEST_OFFSET 0
108#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
109
110#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
111#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
112#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
113#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
114#define CCM_PCDR0_NFCDIV_OFFSET 12
115#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
116#define CCM_PCDR0_48MDIV_OFFSET 5
117#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
118#define CCM_PCDR0_FIRIDIV_OFFSET 0
119#define CCM_PCDR0_FIRIDIV_MASK 0x1f
120#define CCM_PCDR1_PERDIV4_OFFSET 24
121#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
122#define CCM_PCDR1_PERDIV3_OFFSET 16
123#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
124#define CCM_PCDR1_PERDIV2_OFFSET 8
125#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
126#define CCM_PCDR1_PERDIV1_OFFSET 0
127#define CCM_PCDR1_PERDIV1_MASK 0x3f
128
129#define CCM_PCCR_HCLK_CSI_OFFSET 31
130#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
131#define CCM_PCCR_HCLK_DMA_OFFSET 30
132#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
133#define CCM_PCCR_HCLK_BROM_OFFSET 28
134#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
135#define CCM_PCCR_HCLK_EMMA_OFFSET 27
136#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
137#define CCM_PCCR_HCLK_LCDC_OFFSET 26
138#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
139#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
140#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
141#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
142#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
143#define CCM_PCCR_HCLK_BMI_OFFSET 23
144#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
145#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
146#define CCM_PCCR_PERCLK4_OFFSET 22
147#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
148#define CCM_PCCR_SLCDC_OFFSET 21
149#define CCM_PCCR_SLCDC_REG CCM_PCCR0
150#define CCM_PCCR_FIRI_BAUD_OFFSET 20
151#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
152#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
153#define CCM_PCCR_NFC_OFFSET 19
154#define CCM_PCCR_NFC_REG CCM_PCCR0
155#define CCM_PCCR_LCDC_OFFSET 18
156#define CCM_PCCR_LCDC_REG CCM_PCCR0
157#define CCM_PCCR_SSI1_BAUD_OFFSET 17
158#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
159#define CCM_PCCR_SSI2_BAUD_OFFSET 16
160#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
161#define CCM_PCCR_EMMA_OFFSET 15
162#define CCM_PCCR_EMMA_REG CCM_PCCR0
163#define CCM_PCCR_USBOTG_OFFSET 14
164#define CCM_PCCR_USBOTG_REG CCM_PCCR0
165#define CCM_PCCR_DMA_OFFSET 13
166#define CCM_PCCR_DMA_REG CCM_PCCR0
167#define CCM_PCCR_I2C1_OFFSET 12
168#define CCM_PCCR_I2C1_REG CCM_PCCR0
169#define CCM_PCCR_GPIO_OFFSET 11
170#define CCM_PCCR_GPIO_REG CCM_PCCR0
171#define CCM_PCCR_SDHC2_OFFSET 10
172#define CCM_PCCR_SDHC2_REG CCM_PCCR0
173#define CCM_PCCR_SDHC1_OFFSET 9
174#define CCM_PCCR_SDHC1_REG CCM_PCCR0
175#define CCM_PCCR_FIRI_OFFSET 8
176#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
177#define CCM_PCCR_FIRI_REG CCM_PCCR0
178#define CCM_PCCR_SSI2_IPG_OFFSET 7
179#define CCM_PCCR_SSI2_REG CCM_PCCR0
180#define CCM_PCCR_SSI1_IPG_OFFSET 6
181#define CCM_PCCR_SSI1_REG CCM_PCCR0
182#define CCM_PCCR_CSPI2_OFFSET 5
183#define CCM_PCCR_CSPI2_REG CCM_PCCR0
184#define CCM_PCCR_CSPI1_OFFSET 4
185#define CCM_PCCR_CSPI1_REG CCM_PCCR0
186#define CCM_PCCR_UART4_OFFSET 3
187#define CCM_PCCR_UART4_REG CCM_PCCR0
188#define CCM_PCCR_UART3_OFFSET 2
189#define CCM_PCCR_UART3_REG CCM_PCCR0
190#define CCM_PCCR_UART2_OFFSET 1
191#define CCM_PCCR_UART2_REG CCM_PCCR0
192#define CCM_PCCR_UART1_OFFSET 0
193#define CCM_PCCR_UART1_REG CCM_PCCR0
194
195#define CCM_PCCR_OWIRE_OFFSET 31
196#define CCM_PCCR_OWIRE_REG CCM_PCCR1
197#define CCM_PCCR_KPP_OFFSET 30
198#define CCM_PCCR_KPP_REG CCM_PCCR1
199#define CCM_PCCR_RTC_OFFSET 29
200#define CCM_PCCR_RTC_REG CCM_PCCR1
201#define CCM_PCCR_PWM_OFFSET 28
202#define CCM_PCCR_PWM_REG CCM_PCCR1
203#define CCM_PCCR_GPT3_OFFSET 27
204#define CCM_PCCR_GPT3_REG CCM_PCCR1
205#define CCM_PCCR_GPT2_OFFSET 26
206#define CCM_PCCR_GPT2_REG CCM_PCCR1
207#define CCM_PCCR_GPT1_OFFSET 25
208#define CCM_PCCR_GPT1_REG CCM_PCCR1
209#define CCM_PCCR_WDT_OFFSET 24
210#define CCM_PCCR_WDT_REG CCM_PCCR1
211#define CCM_PCCR_CSPI3_OFFSET 23
212#define CCM_PCCR_CSPI3_REG CCM_PCCR1
213
214#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
215#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
216#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
217#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
218#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
219#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
220#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
221#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
222#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
223#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
224#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
225#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
226#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
227#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
228#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
229#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
230#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
231#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
232#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
233#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
234#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
235#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
236#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
237#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
238#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
239#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
240#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
241#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
242#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
243#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
244#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
245#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
246#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
247#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
248#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
249#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
250#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
251
252#define CCM_CCSR_32KSR (1 << 15)
253
254#define CCM_CCSR_CLKMODE1 (1 << 9)
255#define CCM_CCSR_CLKMODE0 (1 << 8)
256
257#define CCM_CCSR_CLKOSEL_OFFSET 0
258#define CCM_CCSR_CLKOSEL_MASK 0x1f
259
260#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
261#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
31 262
32static int _clk_enable(struct clk *clk) 263static int _clk_enable(struct clk *clk)
33{ 264{
@@ -1002,6 +1233,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
1002 clk_enable(&uart_clk[0]); 1233 clk_enable(&uart_clk[0]);
1003#endif 1234#endif
1004 1235
1005 mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); 1236 mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
1237 MX21_INT_GPT1);
1006 return 0; 1238 return 0;
1007} 1239}
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 18c53a6487fa..0f0823c8b170 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -29,21 +29,23 @@
29#include <mach/common.h> 29#include <mach/common.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31 31
32#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
33
32/* Register offsets */ 34/* Register offsets */
33#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) 35#define CCM_CSCR IO_ADDR_CCM(0x0)
34#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) 36#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
35#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) 37#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
36#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) 38#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
37#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) 39#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
38#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) 40#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
39#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) 41#define CCM_PCDR0 IO_ADDR_CCM(0x18)
40#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) 42#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
41#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) 43#define CCM_PCCR0 IO_ADDR_CCM(0x20)
42#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) 44#define CCM_PCCR1 IO_ADDR_CCM(0x24)
43#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) 45#define CCM_CCSR IO_ADDR_CCM(0x28)
44#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) 46#define CCM_PMCTL IO_ADDR_CCM(0x2c)
45#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) 47#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
46#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) 48#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
47 49
48#define CCM_CSCR_UPDATE_DIS (1 << 31) 50#define CCM_CSCR_UPDATE_DIS (1 << 31)
49#define CCM_CSCR_SSI2 (1 << 23) 51#define CCM_CSCR_SSI2 (1 << 23)
@@ -753,7 +755,8 @@ int __init mx27_clocks_init(unsigned long fref)
753 clk_enable(&uart1_clk); 755 clk_enable(&uart1_clk);
754#endif 756#endif
755 757
756 mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); 758 mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
759 MX27_INT_GPT1);
757 760
758 return 0; 761 return 0;
759} 762}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
index d9e3bf9644c9..d8d3b2d84dc5 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -39,7 +39,8 @@ static void query_silicon_parameter(void)
39 * the silicon revision very early we read it here to 39 * the silicon revision very early we read it here to
40 * avoid any further hooks 40 * avoid any further hooks
41 */ 41 */
42 val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); 42 val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
43 + SYS_CHIP_ID));
43 44
44 cpu_silicon_rev = (int)(val >> 28); 45 cpu_silicon_rev = (int)(val >> 28);
45 cpu_partnumber = (int)((val >> 12) & 0xFFFF); 46 cpu_partnumber = (int)((val >> 12) & 0xFFFF);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
deleted file mode 100644
index 749de76b3f95..000000000000
--- a/arch/arm/mach-mx2/crm_regs.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
21#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
22
23#include <mach/hardware.h>
24
25/* Register offsets */
26#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
27#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
28#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
29#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
30#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
31#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
32#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
33#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
34#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
35#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
36#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
37#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
38#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
39#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
40
41#define CCM_CSCR_PRESC_OFFSET 29
42#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
43
44#define CCM_CSCR_USB_OFFSET 26
45#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
46#define CCM_CSCR_SD_OFFSET 24
47#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
48#define CCM_CSCR_SPLLRES (1 << 22)
49#define CCM_CSCR_MPLLRES (1 << 21)
50#define CCM_CSCR_SSI2_OFFSET 20
51#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
52#define CCM_CSCR_SSI1_OFFSET 19
53#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
54#define CCM_CSCR_FIR_OFFSET 18
55#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
56#define CCM_CSCR_SP (1 << 17)
57#define CCM_CSCR_MCU (1 << 16)
58#define CCM_CSCR_BCLK_OFFSET 10
59#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
60#define CCM_CSCR_IPDIV_OFFSET 9
61#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
62
63#define CCM_CSCR_OSC26MDIV (1 << 4)
64#define CCM_CSCR_OSC26M (1 << 3)
65#define CCM_CSCR_FPM (1 << 2)
66#define CCM_CSCR_SPEN (1 << 1)
67#define CCM_CSCR_MPEN 1
68
69
70
71#define CCM_MPCTL0_CPLM (1 << 31)
72#define CCM_MPCTL0_PD_OFFSET 26
73#define CCM_MPCTL0_PD_MASK (0xf << 26)
74#define CCM_MPCTL0_MFD_OFFSET 16
75#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
76#define CCM_MPCTL0_MFI_OFFSET 10
77#define CCM_MPCTL0_MFI_MASK (0xf << 10)
78#define CCM_MPCTL0_MFN_OFFSET 0
79#define CCM_MPCTL0_MFN_MASK 0x3ff
80
81#define CCM_MPCTL1_LF (1 << 15)
82#define CCM_MPCTL1_BRMO (1 << 6)
83
84#define CCM_SPCTL0_CPLM (1 << 31)
85#define CCM_SPCTL0_PD_OFFSET 26
86#define CCM_SPCTL0_PD_MASK (0xf << 26)
87#define CCM_SPCTL0_MFD_OFFSET 16
88#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
89#define CCM_SPCTL0_MFI_OFFSET 10
90#define CCM_SPCTL0_MFI_MASK (0xf << 10)
91#define CCM_SPCTL0_MFN_OFFSET 0
92#define CCM_SPCTL0_MFN_MASK 0x3ff
93
94#define CCM_SPCTL1_LF (1 << 15)
95#define CCM_SPCTL1_BRMO (1 << 6)
96
97#define CCM_OSC26MCTL_PEAK_OFFSET 16
98#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
99#define CCM_OSC26MCTL_AGC_OFFSET 8
100#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
101#define CCM_OSC26MCTL_ANATEST_OFFSET 0
102#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
103
104#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
105#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
106#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
107#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
108#define CCM_PCDR0_NFCDIV_OFFSET 12
109#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
110#define CCM_PCDR0_48MDIV_OFFSET 5
111#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
112#define CCM_PCDR0_FIRIDIV_OFFSET 0
113#define CCM_PCDR0_FIRIDIV_MASK 0x1f
114#define CCM_PCDR1_PERDIV4_OFFSET 24
115#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
116#define CCM_PCDR1_PERDIV3_OFFSET 16
117#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
118#define CCM_PCDR1_PERDIV2_OFFSET 8
119#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
120#define CCM_PCDR1_PERDIV1_OFFSET 0
121#define CCM_PCDR1_PERDIV1_MASK 0x3f
122
123#define CCM_PCCR_HCLK_CSI_OFFSET 31
124#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
125#define CCM_PCCR_HCLK_DMA_OFFSET 30
126#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
127#define CCM_PCCR_HCLK_BROM_OFFSET 28
128#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
129#define CCM_PCCR_HCLK_EMMA_OFFSET 27
130#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
131#define CCM_PCCR_HCLK_LCDC_OFFSET 26
132#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
133#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
134#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
135#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
136#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
137#define CCM_PCCR_HCLK_BMI_OFFSET 23
138#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
139#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
140#define CCM_PCCR_PERCLK4_OFFSET 22
141#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
142#define CCM_PCCR_SLCDC_OFFSET 21
143#define CCM_PCCR_SLCDC_REG CCM_PCCR0
144#define CCM_PCCR_FIRI_BAUD_OFFSET 20
145#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
146#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
147#define CCM_PCCR_NFC_OFFSET 19
148#define CCM_PCCR_NFC_REG CCM_PCCR0
149#define CCM_PCCR_LCDC_OFFSET 18
150#define CCM_PCCR_LCDC_REG CCM_PCCR0
151#define CCM_PCCR_SSI1_BAUD_OFFSET 17
152#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
153#define CCM_PCCR_SSI2_BAUD_OFFSET 16
154#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
155#define CCM_PCCR_EMMA_OFFSET 15
156#define CCM_PCCR_EMMA_REG CCM_PCCR0
157#define CCM_PCCR_USBOTG_OFFSET 14
158#define CCM_PCCR_USBOTG_REG CCM_PCCR0
159#define CCM_PCCR_DMA_OFFSET 13
160#define CCM_PCCR_DMA_REG CCM_PCCR0
161#define CCM_PCCR_I2C1_OFFSET 12
162#define CCM_PCCR_I2C1_REG CCM_PCCR0
163#define CCM_PCCR_GPIO_OFFSET 11
164#define CCM_PCCR_GPIO_REG CCM_PCCR0
165#define CCM_PCCR_SDHC2_OFFSET 10
166#define CCM_PCCR_SDHC2_REG CCM_PCCR0
167#define CCM_PCCR_SDHC1_OFFSET 9
168#define CCM_PCCR_SDHC1_REG CCM_PCCR0
169#define CCM_PCCR_FIRI_OFFSET 8
170#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
171#define CCM_PCCR_FIRI_REG CCM_PCCR0
172#define CCM_PCCR_SSI2_IPG_OFFSET 7
173#define CCM_PCCR_SSI2_REG CCM_PCCR0
174#define CCM_PCCR_SSI1_IPG_OFFSET 6
175#define CCM_PCCR_SSI1_REG CCM_PCCR0
176#define CCM_PCCR_CSPI2_OFFSET 5
177#define CCM_PCCR_CSPI2_REG CCM_PCCR0
178#define CCM_PCCR_CSPI1_OFFSET 4
179#define CCM_PCCR_CSPI1_REG CCM_PCCR0
180#define CCM_PCCR_UART4_OFFSET 3
181#define CCM_PCCR_UART4_REG CCM_PCCR0
182#define CCM_PCCR_UART3_OFFSET 2
183#define CCM_PCCR_UART3_REG CCM_PCCR0
184#define CCM_PCCR_UART2_OFFSET 1
185#define CCM_PCCR_UART2_REG CCM_PCCR0
186#define CCM_PCCR_UART1_OFFSET 0
187#define CCM_PCCR_UART1_REG CCM_PCCR0
188
189#define CCM_PCCR_OWIRE_OFFSET 31
190#define CCM_PCCR_OWIRE_REG CCM_PCCR1
191#define CCM_PCCR_KPP_OFFSET 30
192#define CCM_PCCR_KPP_REG CCM_PCCR1
193#define CCM_PCCR_RTC_OFFSET 29
194#define CCM_PCCR_RTC_REG CCM_PCCR1
195#define CCM_PCCR_PWM_OFFSET 28
196#define CCM_PCCR_PWM_REG CCM_PCCR1
197#define CCM_PCCR_GPT3_OFFSET 27
198#define CCM_PCCR_GPT3_REG CCM_PCCR1
199#define CCM_PCCR_GPT2_OFFSET 26
200#define CCM_PCCR_GPT2_REG CCM_PCCR1
201#define CCM_PCCR_GPT1_OFFSET 25
202#define CCM_PCCR_GPT1_REG CCM_PCCR1
203#define CCM_PCCR_WDT_OFFSET 24
204#define CCM_PCCR_WDT_REG CCM_PCCR1
205#define CCM_PCCR_CSPI3_OFFSET 23
206#define CCM_PCCR_CSPI3_REG CCM_PCCR1
207
208#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
209#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
210#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
211#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
212#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
213#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
214#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
215#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
216#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
217#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
218#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
219#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
220#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
221#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
222#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
223#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
224#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
225#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
226#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
227#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
228#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
229#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
230#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
231#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
232#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
233#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
234#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
235#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
236#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
237#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
238#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
239#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
240#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
241#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
242#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
243#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
244#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
245
246
247#define CCM_CCSR_32KSR (1 << 15)
248
249#define CCM_CCSR_CLKMODE1 (1 << 9)
250#define CCM_CCSR_CLKMODE0 (1 << 8)
251
252#define CCM_CCSR_CLKOSEL_OFFSET 0
253#define CCM_CCSR_CLKOSEL_MASK 0x1f
254
255#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
256#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
257
258#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 3956d82b7c4e..b91e412f7b3e 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -47,65 +47,31 @@
47 * - i.MX21: 2 channel 47 * - i.MX21: 2 channel
48 * - i.MX27: 3 channel 48 * - i.MX27: 3 channel
49 */ 49 */
50static struct resource mxc_spi_resources0[] = { 50#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
51 { 51 static struct resource mxc_spi_resources ## n[] = { \
52 .start = CSPI1_BASE_ADDR, 52 { \
53 .end = CSPI1_BASE_ADDR + SZ_4K - 1, 53 .start = baseaddr, \
54 .flags = IORESOURCE_MEM, 54 .end = baseaddr + SZ_4K - 1, \
55 }, { 55 .flags = IORESOURCE_MEM, \
56 .start = MXC_INT_CSPI1, 56 }, { \
57 .end = MXC_INT_CSPI1, 57 .start = irq, \
58 .flags = IORESOURCE_IRQ, 58 .end = irq, \
59 }, 59 .flags = IORESOURCE_IRQ, \
60}; 60 }, \
61 61 }; \
62static struct resource mxc_spi_resources1[] = { 62 \
63 { 63 struct platform_device mxc_spi_device ## n = { \
64 .start = CSPI2_BASE_ADDR, 64 .name = "spi_imx", \
65 .end = CSPI2_BASE_ADDR + SZ_4K - 1, 65 .id = n, \
66 .flags = IORESOURCE_MEM, 66 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
67 }, { 67 .resource = mxc_spi_resources ## n, \
68 .start = MXC_INT_CSPI2, 68 }
69 .end = MXC_INT_CSPI2,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74#ifdef CONFIG_MACH_MX27
75static struct resource mxc_spi_resources2[] = {
76 {
77 .start = CSPI3_BASE_ADDR,
78 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
79 .flags = IORESOURCE_MEM,
80 }, {
81 .start = MXC_INT_CSPI3,
82 .end = MXC_INT_CSPI3,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86#endif
87
88struct platform_device mxc_spi_device0 = {
89 .name = "spi_imx",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
92 .resource = mxc_spi_resources0,
93};
94 69
95struct platform_device mxc_spi_device1 = { 70DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
96 .name = "spi_imx", 71DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
97 .id = 1,
98 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
99 .resource = mxc_spi_resources1,
100};
101 72
102#ifdef CONFIG_MACH_MX27 73#ifdef CONFIG_MACH_MX27
103struct platform_device mxc_spi_device2 = { 74DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
104 .name = "spi_imx",
105 .id = 2,
106 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
107 .resource = mxc_spi_resources2,
108};
109#endif 75#endif
110 76
111/* 77/*
@@ -113,104 +79,34 @@ struct platform_device mxc_spi_device2 = {
113 * - i.MX21: 3 timers 79 * - i.MX21: 3 timers
114 * - i.MX27: 6 timers 80 * - i.MX27: 6 timers
115 */ 81 */
116 82#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
117/* We use gpt0 as system timer, so do not add a device for this one */ 83 static struct resource timer ## n ##_resources[] = { \
118 84 { \
119static struct resource timer1_resources[] = { 85 .start = baseaddr, \
120 { 86 .end = baseaddr + SZ_4K - 1, \
121 .start = GPT2_BASE_ADDR, 87 .flags = IORESOURCE_MEM, \
122 .end = GPT2_BASE_ADDR + 0x17, 88 }, { \
123 .flags = IORESOURCE_MEM, 89 .start = irq, \
124 }, { 90 .end = irq, \
125 .start = MXC_INT_GPT2, 91 .flags = IORESOURCE_IRQ, \
126 .end = MXC_INT_GPT2, 92 } \
127 .flags = IORESOURCE_IRQ, 93 }; \
128 } 94 \
129}; 95 struct platform_device mxc_gpt ## n = { \
130 96 .name = "imx_gpt", \
131struct platform_device mxc_gpt1 = { 97 .id = n, \
132 .name = "imx_gpt", 98 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
133 .id = 1, 99 .resource = timer ## n ## _resources, \
134 .num_resources = ARRAY_SIZE(timer1_resources),
135 .resource = timer1_resources,
136};
137
138static struct resource timer2_resources[] = {
139 {
140 .start = GPT3_BASE_ADDR,
141 .end = GPT3_BASE_ADDR + 0x17,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = MXC_INT_GPT3,
145 .end = MXC_INT_GPT3,
146 .flags = IORESOURCE_IRQ,
147 } 100 }
148};
149 101
150struct platform_device mxc_gpt2 = { 102/* We use gpt1 as system timer, so do not add a device for this one */
151 .name = "imx_gpt", 103DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
152 .id = 2, 104DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
153 .num_resources = ARRAY_SIZE(timer2_resources),
154 .resource = timer2_resources,
155};
156 105
157#ifdef CONFIG_MACH_MX27 106#ifdef CONFIG_MACH_MX27
158static struct resource timer3_resources[] = { 107DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
159 { 108DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
160 .start = GPT4_BASE_ADDR, 109DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
161 .end = GPT4_BASE_ADDR + 0x17,
162 .flags = IORESOURCE_MEM,
163 }, {
164 .start = MXC_INT_GPT4,
165 .end = MXC_INT_GPT4,
166 .flags = IORESOURCE_IRQ,
167 }
168};
169
170struct platform_device mxc_gpt3 = {
171 .name = "imx_gpt",
172 .id = 3,
173 .num_resources = ARRAY_SIZE(timer3_resources),
174 .resource = timer3_resources,
175};
176
177static struct resource timer4_resources[] = {
178 {
179 .start = GPT5_BASE_ADDR,
180 .end = GPT5_BASE_ADDR + 0x17,
181 .flags = IORESOURCE_MEM,
182 }, {
183 .start = MXC_INT_GPT5,
184 .end = MXC_INT_GPT5,
185 .flags = IORESOURCE_IRQ,
186 }
187};
188
189struct platform_device mxc_gpt4 = {
190 .name = "imx_gpt",
191 .id = 4,
192 .num_resources = ARRAY_SIZE(timer4_resources),
193 .resource = timer4_resources,
194};
195
196static struct resource timer5_resources[] = {
197 {
198 .start = GPT6_BASE_ADDR,
199 .end = GPT6_BASE_ADDR + 0x17,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = MXC_INT_GPT6,
203 .end = MXC_INT_GPT6,
204 .flags = IORESOURCE_IRQ,
205 }
206};
207
208struct platform_device mxc_gpt5 = {
209 .name = "imx_gpt",
210 .id = 5,
211 .num_resources = ARRAY_SIZE(timer5_resources),
212 .resource = timer5_resources,
213};
214#endif 110#endif
215 111
216/* 112/*
@@ -221,9 +117,9 @@ struct platform_device mxc_gpt5 = {
221 */ 117 */
222static struct resource mxc_wdt_resources[] = { 118static struct resource mxc_wdt_resources[] = {
223 { 119 {
224 .start = WDOG_BASE_ADDR, 120 .start = MX2x_WDOG_BASE_ADDR,
225 .end = WDOG_BASE_ADDR + 0x30, 121 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
226 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
227 }, 123 },
228}; 124};
229 125
@@ -236,8 +132,8 @@ struct platform_device mxc_wdt = {
236 132
237static struct resource mxc_w1_master_resources[] = { 133static struct resource mxc_w1_master_resources[] = {
238 { 134 {
239 .start = OWIRE_BASE_ADDR, 135 .start = MX2x_OWIRE_BASE_ADDR,
240 .end = OWIRE_BASE_ADDR + SZ_4K - 1, 136 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
241 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
242 }, 138 },
243}; 139};
@@ -249,24 +145,33 @@ struct platform_device mxc_w1_master_device = {
249 .resource = mxc_w1_master_resources, 145 .resource = mxc_w1_master_resources,
250}; 146};
251 147
252static struct resource mxc_nand_resources[] = { 148#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
253 { 149 static struct resource pfx ## _nand_resources[] = { \
254 .start = NFC_BASE_ADDR, 150 { \
255 .end = NFC_BASE_ADDR + 0xfff, 151 .start = baseaddr, \
256 .flags = IORESOURCE_MEM, 152 .end = baseaddr + SZ_4K - 1, \
257 }, { 153 .flags = IORESOURCE_MEM, \
258 .start = MXC_INT_NANDFC, 154 }, { \
259 .end = MXC_INT_NANDFC, 155 .start = irq, \
260 .flags = IORESOURCE_IRQ, 156 .end = irq, \
261 }, 157 .flags = IORESOURCE_IRQ, \
262}; 158 }, \
159 }; \
160 \
161 struct platform_device pfx ## _nand_device = { \
162 .name = "mxc_nand", \
163 .id = 0, \
164 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
165 .resource = pfx ## _nand_resources, \
166 }
263 167
264struct platform_device mxc_nand_device = { 168#ifdef CONFIG_MACH_MX21
265 .name = "mxc_nand", 169DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
266 .id = 0, 170#endif
267 .num_resources = ARRAY_SIZE(mxc_nand_resources), 171
268 .resource = mxc_nand_resources, 172#ifdef CONFIG_MACH_MX27
269}; 173DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
174#endif
270 175
271/* 176/*
272 * lcdc: 177 * lcdc:
@@ -276,12 +181,12 @@ struct platform_device mxc_nand_device = {
276 */ 181 */
277static struct resource mxc_fb[] = { 182static struct resource mxc_fb[] = {
278 { 183 {
279 .start = LCDC_BASE_ADDR, 184 .start = MX2x_LCDC_BASE_ADDR,
280 .end = LCDC_BASE_ADDR + 0xFFF, 185 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
281 .flags = IORESOURCE_MEM, 186 .flags = IORESOURCE_MEM,
282 }, { 187 }, {
283 .start = MXC_INT_LCDC, 188 .start = MX2x_INT_LCDC,
284 .end = MXC_INT_LCDC, 189 .end = MX2x_INT_LCDC,
285 .flags = IORESOURCE_IRQ, 190 .flags = IORESOURCE_IRQ,
286 } 191 }
287}; 192};
@@ -300,13 +205,13 @@ struct platform_device mxc_fb_device = {
300#ifdef CONFIG_MACH_MX27 205#ifdef CONFIG_MACH_MX27
301static struct resource mxc_fec_resources[] = { 206static struct resource mxc_fec_resources[] = {
302 { 207 {
303 .start = FEC_BASE_ADDR, 208 .start = MX27_FEC_BASE_ADDR,
304 .end = FEC_BASE_ADDR + 0xfff, 209 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
305 .flags = IORESOURCE_MEM, 210 .flags = IORESOURCE_MEM,
306 }, { 211 }, {
307 .start = MXC_INT_FEC, 212 .start = MX27_INT_FEC,
308 .end = MXC_INT_FEC, 213 .end = MX27_INT_FEC,
309 .flags = IORESOURCE_IRQ, 214 .flags = IORESOURCE_IRQ,
310 }, 215 },
311}; 216};
312 217
@@ -318,55 +223,41 @@ struct platform_device mxc_fec_device = {
318}; 223};
319#endif 224#endif
320 225
321static struct resource mxc_i2c_1_resources[] = { 226#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
322 { 227 static struct resource mxc_i2c_resources ## n[] = { \
323 .start = I2C_BASE_ADDR, 228 { \
324 .end = I2C_BASE_ADDR + 0x0fff, 229 .start = baseaddr, \
325 .flags = IORESOURCE_MEM, 230 .end = baseaddr + SZ_4K - 1, \
326 }, { 231 .flags = IORESOURCE_MEM, \
327 .start = MXC_INT_I2C, 232 }, { \
328 .end = MXC_INT_I2C, 233 .start = irq, \
329 .flags = IORESOURCE_IRQ, 234 .end = irq, \
235 .flags = IORESOURCE_IRQ, \
236 } \
237 }; \
238 \
239 struct platform_device mxc_i2c_device ## n = { \
240 .name = "imx-i2c", \
241 .id = n, \
242 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
243 .resource = mxc_i2c_resources ## n, \
330 } 244 }
331};
332 245
333struct platform_device mxc_i2c_device0 = { 246DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
334 .name = "imx-i2c",
335 .id = 0,
336 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
337 .resource = mxc_i2c_1_resources,
338};
339 247
340#ifdef CONFIG_MACH_MX27 248#ifdef CONFIG_MACH_MX27
341static struct resource mxc_i2c_2_resources[] = { 249DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
342 {
343 .start = I2C2_BASE_ADDR,
344 .end = I2C2_BASE_ADDR + 0x0fff,
345 .flags = IORESOURCE_MEM,
346 }, {
347 .start = MXC_INT_I2C2,
348 .end = MXC_INT_I2C2,
349 .flags = IORESOURCE_IRQ,
350 }
351};
352
353struct platform_device mxc_i2c_device1 = {
354 .name = "imx-i2c",
355 .id = 1,
356 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
357 .resource = mxc_i2c_2_resources,
358};
359#endif 250#endif
360 251
361static struct resource mxc_pwm_resources[] = { 252static struct resource mxc_pwm_resources[] = {
362 { 253 {
363 .start = PWM_BASE_ADDR, 254 .start = MX2x_PWM_BASE_ADDR,
364 .end = PWM_BASE_ADDR + 0x0fff, 255 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
365 .flags = IORESOURCE_MEM, 256 .flags = IORESOURCE_MEM,
366 }, { 257 }, {
367 .start = MXC_INT_PWM, 258 .start = MX2x_INT_PWM,
368 .end = MXC_INT_PWM, 259 .end = MX2x_INT_PWM,
369 .flags = IORESOURCE_IRQ, 260 .flags = IORESOURCE_IRQ,
370 } 261 }
371}; 262};
372 263
@@ -377,77 +268,49 @@ struct platform_device mxc_pwm_device = {
377 .resource = mxc_pwm_resources, 268 .resource = mxc_pwm_resources,
378}; 269};
379 270
380/* 271#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
381 * Resource definition for the MXC SDHC 272 static struct resource mxc_sdhc_resources ## n[] = { \
382 */ 273 { \
383static struct resource mxc_sdhc1_resources[] = { 274 .start = baseaddr, \
384 { 275 .end = baseaddr + SZ_4K - 1, \
385 .start = SDHC1_BASE_ADDR, 276 .flags = IORESOURCE_MEM, \
386 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 277 }, { \
387 .flags = IORESOURCE_MEM, 278 .start = irq, \
388 }, { 279 .end = irq, \
389 .start = MXC_INT_SDHC1, 280 .flags = IORESOURCE_IRQ, \
390 .end = MXC_INT_SDHC1, 281 }, { \
391 .flags = IORESOURCE_IRQ, 282 .start = dmareq, \
392 }, { 283 .end = dmareq, \
393 .start = DMA_REQ_SDHC1, 284 .flags = IORESOURCE_DMA, \
394 .end = DMA_REQ_SDHC1, 285 }, \
395 .flags = IORESOURCE_DMA, 286 }; \
396 }, 287 \
397}; 288 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
398 289 \
399static u64 mxc_sdhc1_dmamask = DMA_BIT_MASK(32); 290 struct platform_device mxc_sdhc_device ## n = { \
400 291 .name = "mxc-mmc", \
401struct platform_device mxc_sdhc_device0 = { 292 .id = n, \
402 .name = "mxc-mmc", 293 .dev = { \
403 .id = 0, 294 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
404 .dev = { 295 .coherent_dma_mask = DMA_BIT_MASK(32), \
405 .dma_mask = &mxc_sdhc1_dmamask, 296 }, \
406 .coherent_dma_mask = DMA_BIT_MASK(32), 297 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
407 }, 298 .resource = mxc_sdhc_resources ## n, \
408 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), 299 }
409 .resource = mxc_sdhc1_resources,
410};
411
412static struct resource mxc_sdhc2_resources[] = {
413 {
414 .start = SDHC2_BASE_ADDR,
415 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
416 .flags = IORESOURCE_MEM,
417 }, {
418 .start = MXC_INT_SDHC2,
419 .end = MXC_INT_SDHC2,
420 .flags = IORESOURCE_IRQ,
421 }, {
422 .start = DMA_REQ_SDHC2,
423 .end = DMA_REQ_SDHC2,
424 .flags = IORESOURCE_DMA,
425 },
426};
427
428static u64 mxc_sdhc2_dmamask = DMA_BIT_MASK(32);
429 300
430struct platform_device mxc_sdhc_device1 = { 301DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
431 .name = "mxc-mmc", 302DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
432 .id = 1,
433 .dev = {
434 .dma_mask = &mxc_sdhc2_dmamask,
435 .coherent_dma_mask = DMA_BIT_MASK(32),
436 },
437 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
438 .resource = mxc_sdhc2_resources,
439};
440 303
441#ifdef CONFIG_MACH_MX27 304#ifdef CONFIG_MACH_MX27
442static struct resource otg_resources[] = { 305static struct resource otg_resources[] = {
443 { 306 {
444 .start = OTG_BASE_ADDR, 307 .start = MX27_USBOTG_BASE_ADDR,
445 .end = OTG_BASE_ADDR + 0x1ff, 308 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
446 .flags = IORESOURCE_MEM, 309 .flags = IORESOURCE_MEM,
447 }, { 310 }, {
448 .start = MXC_INT_USB3, 311 .start = MX27_INT_USB3,
449 .end = MXC_INT_USB3, 312 .end = MX27_INT_USB3,
450 .flags = IORESOURCE_IRQ, 313 .flags = IORESOURCE_IRQ,
451 }, 314 },
452}; 315};
453 316
@@ -483,12 +346,12 @@ static u64 usbh1_dmamask = DMA_BIT_MASK(32);
483 346
484static struct resource mxc_usbh1_resources[] = { 347static struct resource mxc_usbh1_resources[] = {
485 { 348 {
486 .start = OTG_BASE_ADDR + 0x200, 349 .start = MX27_USBOTG_BASE_ADDR + 0x200,
487 .end = OTG_BASE_ADDR + 0x3ff, 350 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
488 .flags = IORESOURCE_MEM, 351 .flags = IORESOURCE_MEM,
489 }, { 352 }, {
490 .start = MXC_INT_USB1, 353 .start = MX27_INT_USB1,
491 .end = MXC_INT_USB1, 354 .end = MX27_INT_USB1,
492 .flags = IORESOURCE_IRQ, 355 .flags = IORESOURCE_IRQ,
493 }, 356 },
494}; 357};
@@ -509,12 +372,12 @@ static u64 usbh2_dmamask = DMA_BIT_MASK(32);
509 372
510static struct resource mxc_usbh2_resources[] = { 373static struct resource mxc_usbh2_resources[] = {
511 { 374 {
512 .start = OTG_BASE_ADDR + 0x400, 375 .start = MX27_USBOTG_BASE_ADDR + 0x400,
513 .end = OTG_BASE_ADDR + 0x5ff, 376 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
514 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
515 }, { 378 }, {
516 .start = MXC_INT_USB2, 379 .start = MX27_INT_USB2,
517 .end = MXC_INT_USB2, 380 .end = MX27_INT_USB2,
518 .flags = IORESOURCE_IRQ, 381 .flags = IORESOURCE_IRQ,
519 }, 382 },
520}; 383};
@@ -531,129 +394,102 @@ struct platform_device mxc_usbh2 = {
531}; 394};
532#endif 395#endif
533 396
534static struct resource imx_ssi_resources0[] = { 397#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
535 { 398 { \
536 .start = SSI1_BASE_ADDR, 399 .name = _name, \
537 .end = SSI1_BASE_ADDR + 0x6F, 400 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
538 .flags = IORESOURCE_MEM, 401 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
539 }, { 402 .flags = IORESOURCE_DMA, \
540 .start = MXC_INT_SSI1, 403 }
541 .end = MXC_INT_SSI1,
542 .flags = IORESOURCE_IRQ,
543 }, {
544 .name = "tx0",
545 .start = DMA_REQ_SSI1_TX0,
546 .end = DMA_REQ_SSI1_TX0,
547 .flags = IORESOURCE_DMA,
548 }, {
549 .name = "rx0",
550 .start = DMA_REQ_SSI1_RX0,
551 .end = DMA_REQ_SSI1_RX0,
552 .flags = IORESOURCE_DMA,
553 }, {
554 .name = "tx1",
555 .start = DMA_REQ_SSI1_TX1,
556 .end = DMA_REQ_SSI1_TX1,
557 .flags = IORESOURCE_DMA,
558 }, {
559 .name = "rx1",
560 .start = DMA_REQ_SSI1_RX1,
561 .end = DMA_REQ_SSI1_RX1,
562 .flags = IORESOURCE_DMA,
563 },
564};
565
566static struct resource imx_ssi_resources1[] = {
567 {
568 .start = SSI2_BASE_ADDR,
569 .end = SSI2_BASE_ADDR + 0x6F,
570 .flags = IORESOURCE_MEM,
571 }, {
572 .start = MXC_INT_SSI2,
573 .end = MXC_INT_SSI2,
574 .flags = IORESOURCE_IRQ,
575 }, {
576 .name = "tx0",
577 .start = DMA_REQ_SSI2_TX0,
578 .end = DMA_REQ_SSI2_TX0,
579 .flags = IORESOURCE_DMA,
580 }, {
581 .name = "rx0",
582 .start = DMA_REQ_SSI2_RX0,
583 .end = DMA_REQ_SSI2_RX0,
584 .flags = IORESOURCE_DMA,
585 }, {
586 .name = "tx1",
587 .start = DMA_REQ_SSI2_TX1,
588 .end = DMA_REQ_SSI2_TX1,
589 .flags = IORESOURCE_DMA,
590 }, {
591 .name = "rx1",
592 .start = DMA_REQ_SSI2_RX1,
593 .end = DMA_REQ_SSI2_RX1,
594 .flags = IORESOURCE_DMA,
595 },
596};
597 404
598struct platform_device imx_ssi_device0 = { 405#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
599 .name = "imx-ssi", 406 static struct resource imx_ssi_resources ## n[] = { \
600 .id = 0, 407 { \
601 .num_resources = ARRAY_SIZE(imx_ssi_resources0), 408 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
602 .resource = imx_ssi_resources0, 409 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
603}; 410 .flags = IORESOURCE_MEM, \
411 }, { \
412 .start = MX2x_INT_SSI1, \
413 .end = MX2x_INT_SSI1, \
414 .flags = IORESOURCE_IRQ, \
415 }, \
416 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
417 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
418 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
419 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
420 }; \
421 \
422 struct platform_device imx_ssi_device ## n = { \
423 .name = "imx-ssi", \
424 .id = n, \
425 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
426 .resource = imx_ssi_resources ## n, \
427 }
604 428
605struct platform_device imx_ssi_device1 = { 429DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
606 .name = "imx-ssi", 430DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
607 .id = 1,
608 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
609 .resource = imx_ssi_resources1,
610};
611 431
612/* GPIO port description */ 432/* GPIO port description */
613static struct mxc_gpio_port imx_gpio_ports[] = { 433#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
614 { 434 { \
615 .chip.label = "gpio-0", 435 .chip.label = "gpio-" #n, \
616 .irq = MXC_INT_GPIO, 436 .irq = _irq, \
617 .base = IO_ADDRESS(GPIO_BASE_ADDR), 437 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
618 .virtual_irq_start = MXC_GPIO_IRQ_START, 438 n * 0x100), \
619 }, { 439 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
620 .chip.label = "gpio-1",
621 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
622 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
623 }, {
624 .chip.label = "gpio-2",
625 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
626 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
627 }, {
628 .chip.label = "gpio-3",
629 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
630 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
631 }, {
632 .chip.label = "gpio-4",
633 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
634 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
635 }, {
636 .chip.label = "gpio-5",
637 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
638 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
639 } 440 }
640}; 441
442#define DEFINE_MXC_GPIO_PORT(SOC, n) \
443 { \
444 .chip.label = "gpio-" #n, \
445 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
446 n * 0x100), \
447 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
448 }
449
450#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
451 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
452 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
453 DEFINE_MXC_GPIO_PORT(SOC, 1), \
454 DEFINE_MXC_GPIO_PORT(SOC, 2), \
455 DEFINE_MXC_GPIO_PORT(SOC, 3), \
456 DEFINE_MXC_GPIO_PORT(SOC, 4), \
457 DEFINE_MXC_GPIO_PORT(SOC, 5), \
458 }
459
460#ifdef CONFIG_MACH_MX21
461DEFINE_MXC_GPIO_PORTS(MX21, imx21);
462#endif
463
464#ifdef CONFIG_MACH_MX27
465DEFINE_MXC_GPIO_PORTS(MX27, imx27);
466#endif
641 467
642int __init mxc_register_gpios(void) 468int __init mxc_register_gpios(void)
643{ 469{
644 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 470#ifdef CONFIG_MACH_MX21
471 if (cpu_is_mx21())
472 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
473 else
474#endif
475#ifdef CONFIG_MACH_MX27
476 if (cpu_is_mx27())
477 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
478 else
479#endif
480 return 0;
645} 481}
646 482
647#ifdef CONFIG_MACH_MX21 483#ifdef CONFIG_MACH_MX21
648static struct resource mx21_usbhc_resources[] = { 484static struct resource mx21_usbhc_resources[] = {
649 { 485 {
650 .start = USBOTG_BASE_ADDR, 486 .start = MX21_BASE_ADDR,
651 .end = USBOTG_BASE_ADDR + 0x1FFF, 487 .end = MX21_BASE_ADDR + 0x1FFF,
652 .flags = IORESOURCE_MEM, 488 .flags = IORESOURCE_MEM,
653 }, 489 },
654 { 490 {
655 .start = MXC_INT_USBHOST, 491 .start = MX21_INT_USBHOST,
656 .end = MXC_INT_USBHOST, 492 .end = MX21_INT_USBHOST,
657 .flags = IORESOURCE_IRQ, 493 .flags = IORESOURCE_IRQ,
658 }, 494 },
659}; 495};
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index f12694b07369..84ed51380174 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -1,8 +1,10 @@
1extern struct platform_device mxc_gpt1; 1extern struct platform_device mxc_gpt1;
2extern struct platform_device mxc_gpt2; 2extern struct platform_device mxc_gpt2;
3#ifdef CONFIG_MACH_MX27
3extern struct platform_device mxc_gpt3; 4extern struct platform_device mxc_gpt3;
4extern struct platform_device mxc_gpt4; 5extern struct platform_device mxc_gpt4;
5extern struct platform_device mxc_gpt5; 6extern struct platform_device mxc_gpt5;
7#endif
6extern struct platform_device mxc_wdt; 8extern struct platform_device mxc_wdt;
7extern struct platform_device mxc_uart_device0; 9extern struct platform_device mxc_uart_device0;
8extern struct platform_device mxc_uart_device1; 10extern struct platform_device mxc_uart_device1;
@@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3;
11extern struct platform_device mxc_uart_device4; 13extern struct platform_device mxc_uart_device4;
12extern struct platform_device mxc_uart_device5; 14extern struct platform_device mxc_uart_device5;
13extern struct platform_device mxc_w1_master_device; 15extern struct platform_device mxc_w1_master_device;
14extern struct platform_device mxc_nand_device; 16#ifdef CONFIG_MACH_MX21
17extern struct platform_device imx21_nand_device;
18#endif
19#ifdef CONFIG_MACH_MX27
20extern struct platform_device imx27_nand_device;
21#endif
15extern struct platform_device mxc_fb_device; 22extern struct platform_device mxc_fb_device;
16extern struct platform_device mxc_fec_device; 23extern struct platform_device mxc_fec_device;
17extern struct platform_device mxc_pwm_device; 24extern struct platform_device mxc_pwm_device;
18extern struct platform_device mxc_i2c_device0; 25extern struct platform_device mxc_i2c_device0;
26#ifdef CONFIG_MACH_MX27
19extern struct platform_device mxc_i2c_device1; 27extern struct platform_device mxc_i2c_device1;
28#endif
20extern struct platform_device mxc_sdhc_device0; 29extern struct platform_device mxc_sdhc_device0;
21extern struct platform_device mxc_sdhc_device1; 30extern struct platform_device mxc_sdhc_device1;
22extern struct platform_device mxc_otg_udc_device; 31extern struct platform_device mxc_otg_udc_device;
@@ -25,7 +34,9 @@ extern struct platform_device mxc_usbh1;
25extern struct platform_device mxc_usbh2; 34extern struct platform_device mxc_usbh2;
26extern struct platform_device mxc_spi_device0; 35extern struct platform_device mxc_spi_device0;
27extern struct platform_device mxc_spi_device1; 36extern struct platform_device mxc_spi_device1;
37#ifdef CONFIG_MACH_MX27
28extern struct platform_device mxc_spi_device2; 38extern struct platform_device mxc_spi_device2;
39#endif
29extern struct platform_device mx21_usbhc_device; 40extern struct platform_device mx21_usbhc_device;
30extern struct platform_device imx_ssi_device0; 41extern struct platform_device imx_ssi_device0;
31extern struct platform_device imx_ssi_device1; 42extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
index 7382b6d27ee1..f3b169d5245f 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -28,7 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29 29
30#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/iomux.h> 31#include <mach/iomux-mx27.h>
32#include <mach/imxfb.h> 32#include <mach/imxfb.h>
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/mmc.h> 34#include <mach/mmc.h>
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
index 7b187606682c..1f616dcaabc9 100644
--- a/arch/arm/mach-mx2/eukrea_cpuimx27.c
+++ b/arch/arm/mach-mx2/mach-cpuimx27.c
@@ -36,7 +36,7 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <mach/iomux.h> 39#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h> 40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
42 42
@@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
142#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 142#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
143static struct plat_serial8250_port serial_platform_data[] = { 143static struct plat_serial8250_port serial_platform_data[] = {
144 { 144 {
145 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000), 145 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
146 .irq = IRQ_GPIOB(23), 146 .irq = IRQ_GPIOB(23),
147 .uartclk = 14745600, 147 .uartclk = 14745600,
148 .regshift = 1, 148 .regshift = 1,
149 .iotype = UPIO_MEM, 149 .iotype = UPIO_MEM,
150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
151 }, { 151 }, {
152 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000), 152 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
153 .irq = IRQ_GPIOB(22), 153 .irq = IRQ_GPIOB(22),
154 .uartclk = 14745600, 154 .uartclk = 14745600,
155 .regshift = 1, 155 .regshift = 1,
156 .iotype = UPIO_MEM, 156 .iotype = UPIO_MEM,
157 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 157 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
158 }, { 158 }, {
159 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000), 159 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
160 .irq = IRQ_GPIOB(27), 160 .irq = IRQ_GPIOB(27),
161 .uartclk = 14745600, 161 .uartclk = 14745600,
162 .regshift = 1, 162 .regshift = 1,
163 .iotype = UPIO_MEM, 163 .iotype = UPIO_MEM,
164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
165 }, { 165 }, {
166 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000), 166 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
167 .irq = IRQ_GPIOB(30), 167 .irq = IRQ_GPIOB(30),
168 .uartclk = 14745600, 168 .uartclk = 14745600,
169 .regshift = 1, 169 .regshift = 1,
@@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void)
189 189
190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
191 191
192 mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info); 192 mxc_register_device(&imx27_nand_device,
193 &eukrea_cpuimx27_nand_board_info);
193 194
194 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, 195 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
195 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); 196 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
@@ -224,9 +225,9 @@ static struct sys_timer eukrea_cpuimx27_timer = {
224}; 225};
225 226
226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 227MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
227 .phys_io = AIPI_BASE_ADDR, 228 .phys_io = MX27_AIPI_BASE_ADDR,
228 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 229 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
229 .boot_params = PHYS_OFFSET + 0x100, 230 .boot_params = MX27_PHYS_OFFSET + 0x100,
230 .map_io = mx27_map_io, 231 .map_io = mx27_map_io,
231 .init_irq = mx27_init_irq, 232 .init_irq = mx27_init_irq,
232 .init_machine = eukrea_cpuimx27_init, 233 .init_machine = eukrea_cpuimx27_init,
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c
index 82ea227ea0cf..b5710bf18b96 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mach-imx27lite.c
@@ -27,7 +27,7 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/common.h> 28#include <mach/common.h>
29#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
30#include <mach/iomux.h> 30#include <mach/iomux-mx27.h>
31#include <mach/board-mx27lite.h> 31#include <mach/board-mx27lite.h>
32 32
33#include "devices.h" 33#include "devices.h"
@@ -85,9 +85,9 @@ static struct sys_timer mx27lite_timer = {
85}; 85};
86 86
87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
88 .phys_io = AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = MX27_PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27lite_init, 93 .init_machine = mx27lite_init,
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c
index cf5f77cbc2f1..113e58d7cb40 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mach-mx21ads.c
@@ -30,7 +30,7 @@
30#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31#include <mach/imx-uart.h> 31#include <mach/imx-uart.h>
32#include <mach/imxfb.h> 32#include <mach/imxfb.h>
33#include <mach/iomux.h> 33#include <mach/iomux-mx21.h>
34#include <mach/mxc_nand.h> 34#include <mach/mxc_nand.h>
35#include <mach/mmc.h> 35#include <mach/mmc.h>
36#include <mach/board-mx21ads.h> 36#include <mach/board-mx21ads.h>
@@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
118}; 118};
119 119
120static struct resource mx21ads_flash_resource = { 120static struct resource mx21ads_flash_resource = {
121 .start = CS0_BASE_ADDR, 121 .start = MX21_CS0_BASE_ADDR,
122 .end = CS0_BASE_ADDR + 0x02000000 - 1, 122 .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
123 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
124}; 124};
125 125
@@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = {
242 */ 242 */
243 { 243 {
244 .virtual = MX21ADS_MMIO_BASE_ADDR, 244 .virtual = MX21ADS_MMIO_BASE_ADDR,
245 .pfn = __phys_to_pfn(CS1_BASE_ADDR), 245 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
246 .length = MX21ADS_MMIO_SIZE, 246 .length = MX21ADS_MMIO_SIZE,
247 .type = MT_DEVICE, 247 .type = MT_DEVICE,
248 }, 248 },
@@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void)
268 mxc_register_device(&mxc_uart_device3, &uart_pdata); 268 mxc_register_device(&mxc_uart_device3, &uart_pdata);
269 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); 269 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
270 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); 270 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
271 mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); 271 mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
272 272
273 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 273 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
274} 274}
@@ -284,9 +284,9 @@ static struct sys_timer mx21ads_timer = {
284 284
285MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 285MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
286 /* maintainer: Freescale Semiconductor, Inc. */ 286 /* maintainer: Freescale Semiconductor, Inc. */
287 .phys_io = AIPI_BASE_ADDR, 287 .phys_io = MX21_AIPI_BASE_ADDR,
288 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
289 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = MX21_PHYS_OFFSET + 0x100,
290 .map_io = mx21ads_map_io, 290 .map_io = mx21ads_map_io,
291 .init_irq = mx21_init_irq, 291 .init_irq = mx21_init_irq,
292 .init_machine = mx21ads_board_init, 292 .init_machine = mx21ads_board_init,
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mach-mx27_3ds.c
index 6761d1b79e43..b2f4e0db3fb3 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -26,7 +26,7 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/imx-uart.h> 28#include <mach/imx-uart.h>
29#include <mach/iomux.h> 29#include <mach/iomux-mx27.h>
30#include <mach/board-mx27pdk.h> 30#include <mach/board-mx27pdk.h>
31 31
32#include "devices.h" 32#include "devices.h"
@@ -85,9 +85,9 @@ static struct sys_timer mx27pdk_timer = {
85 85
86MACHINE_START(MX27_3DS, "Freescale MX27PDK") 86MACHINE_START(MX27_3DS, "Freescale MX27PDK")
87 /* maintainer: Freescale Semiconductor, Inc. */ 87 /* maintainer: Freescale Semiconductor, Inc. */
88 .phys_io = AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = MX27_PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27pdk_init, 93 .init_machine = mx27pdk_init,
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c
index 83e412b713e6..6ce323669e58 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mach-mx27ads.c
@@ -33,7 +33,7 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <mach/gpio.h> 34#include <mach/gpio.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/iomux.h> 36#include <mach/iomux-mx27.h>
37#include <mach/board-mx27ads.h> 37#include <mach/board-mx27ads.h>
38#include <mach/mxc_nand.h> 38#include <mach/mxc_nand.h>
39#include <mach/i2c.h> 39#include <mach/i2c.h>
@@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void)
290 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); 290 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
291 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); 291 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
292 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); 292 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
293 mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); 293 mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
294 294
295 /* only the i2c master 1 is used on this CPU card */ 295 /* only the i2c master 1 is used on this CPU card */
296 i2c_register_board_info(1, mx27ads_i2c_devices, 296 i2c_register_board_info(1, mx27ads_i2c_devices,
@@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = {
320static struct map_desc mx27ads_io_desc[] __initdata = { 320static struct map_desc mx27ads_io_desc[] __initdata = {
321 { 321 {
322 .virtual = PBC_BASE_ADDRESS, 322 .virtual = PBC_BASE_ADDRESS,
323 .pfn = __phys_to_pfn(CS4_BASE_ADDR), 323 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
324 .length = SZ_1M, 324 .length = SZ_1M,
325 .type = MT_DEVICE, 325 .type = MT_DEVICE,
326 }, 326 },
@@ -334,9 +334,9 @@ static void __init mx27ads_map_io(void)
334 334
335MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 335MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
336 /* maintainer: Freescale Semiconductor, Inc. */ 336 /* maintainer: Freescale Semiconductor, Inc. */
337 .phys_io = AIPI_BASE_ADDR, 337 .phys_io = MX27_AIPI_BASE_ADDR,
338 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 338 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
339 .boot_params = PHYS_OFFSET + 0x100, 339 .boot_params = MX27_PHYS_OFFSET + 0x100,
340 .map_io = mx27ads_map_io, 340 .map_io = mx27ads_map_io,
341 .init_irq = mx27_init_irq, 341 .init_irq = mx27_init_irq,
342 .init_machine = mx27ads_board_init, 342 .init_machine = mx27ads_board_init,
diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c
index 8bcc1a5b8829..bc3855992677 100644
--- a/arch/arm/mach-mx2/mxt_td60.c
+++ b/arch/arm/mach-mx2/mach-mxt_td60.c
@@ -33,7 +33,7 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <linux/gpio.h> 34#include <linux/gpio.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/iomux.h> 36#include <mach/iomux-mx27.h>
37#include <mach/mxc_nand.h> 37#include <mach/mxc_nand.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <linux/i2c/pca953x.h> 39#include <linux/i2c/pca953x.h>
@@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void)
257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
260 mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); 260 mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
261 261
262 i2c_register_board_info(0, mxt_td60_i2c_devices, 262 i2c_register_board_info(0, mxt_td60_i2c_devices,
263 ARRAY_SIZE(mxt_td60_i2c_devices)); 263 ARRAY_SIZE(mxt_td60_i2c_devices));
@@ -284,9 +284,9 @@ static struct sys_timer mxt_td60_timer = {
284 284
285MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 285MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
286 /* maintainer: Maxtrack Industrial */ 286 /* maintainer: Maxtrack Industrial */
287 .phys_io = AIPI_BASE_ADDR, 287 .phys_io = MX27_AIPI_BASE_ADDR,
288 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
289 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = MX27_PHYS_OFFSET + 0x100,
290 .map_io = mx27_map_io, 290 .map_io = mx27_map_io,
291 .init_irq = mx27_init_irq, 291 .init_irq = mx27_init_irq,
292 .init_machine = mxt_td60_board_init, 292 .init_machine = mxt_td60_board_init,
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index aea3d340d2e1..778fff230918 100644
--- a/arch/arm/mach-mx2/pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -25,25 +25,36 @@
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/eeprom.h> 26#include <linux/spi/eeprom.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/delay.h>
28#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <linux/fsl_devices.h>
29 33
30#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
31#include <asm/mach-types.h> 35#include <asm/mach-types.h>
32#include <mach/common.h> 36#include <mach/common.h>
33#include <mach/hardware.h> 37#include <mach/hardware.h>
34#include <mach/iomux.h> 38#include <mach/iomux-mx27.h>
35#include <mach/i2c.h> 39#include <mach/i2c.h>
36#include <asm/mach/time.h> 40#include <asm/mach/time.h>
37#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 41#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
38#include <mach/spi.h> 42#include <mach/spi.h>
39#endif 43#endif
40#include <mach/imx-uart.h> 44#include <mach/imx-uart.h>
45#include <mach/audmux.h>
46#include <mach/ssi.h>
41#include <mach/mxc_nand.h> 47#include <mach/mxc_nand.h>
42#include <mach/irqs.h> 48#include <mach/irqs.h>
43#include <mach/mmc.h> 49#include <mach/mmc.h>
50#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h>
44 52
45#include "devices.h" 53#include "devices.h"
46 54
55#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
56#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
57
47static int pca100_pins[] = { 58static int pca100_pins[] = {
48 /* UART1 */ 59 /* UART1 */
49 PE12_PF_UART1_TXD, 60 PE12_PF_UART1_TXD,
@@ -92,6 +103,34 @@ static int pca100_pins[] = {
92 PD29_PF_CSPI1_SCLK, 103 PD29_PF_CSPI1_SCLK,
93 PD30_PF_CSPI1_MISO, 104 PD30_PF_CSPI1_MISO,
94 PD31_PF_CSPI1_MOSI, 105 PD31_PF_CSPI1_MOSI,
106 /* OTG */
107 OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
108 PC7_PF_USBOTG_DATA5,
109 PC8_PF_USBOTG_DATA6,
110 PC9_PF_USBOTG_DATA0,
111 PC10_PF_USBOTG_DATA2,
112 PC11_PF_USBOTG_DATA1,
113 PC12_PF_USBOTG_DATA4,
114 PC13_PF_USBOTG_DATA3,
115 PE0_PF_USBOTG_NXT,
116 PE1_PF_USBOTG_STP,
117 PE2_PF_USBOTG_DIR,
118 PE24_PF_USBOTG_CLK,
119 PE25_PF_USBOTG_DATA7,
120 /* USBH2 */
121 USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
122 PA0_PF_USBH2_CLK,
123 PA1_PF_USBH2_DIR,
124 PA2_PF_USBH2_DATA7,
125 PA3_PF_USBH2_NXT,
126 PA4_PF_USBH2_STP,
127 PD19_AF_USBH2_DATA4,
128 PD20_AF_USBH2_DATA3,
129 PD21_AF_USBH2_DATA6,
130 PD22_AF_USBH2_DATA0,
131 PD23_AF_USBH2_DATA2,
132 PD24_AF_USBH2_DATA1,
133 PD26_AF_USBH2_DATA5,
95}; 134};
96 135
97static struct imxuart_platform_data uart_pdata = { 136static struct imxuart_platform_data uart_pdata = {
@@ -157,6 +196,37 @@ static struct spi_imx_master pca100_spi_0_data = {
157}; 196};
158#endif 197#endif
159 198
199static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
200{
201 mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
202 gpio_set_value(GPIO_PORTC + 20, 1);
203 udelay(2);
204 gpio_set_value(GPIO_PORTC + 20, 0);
205 mxc_gpio_mode(PC20_PF_SSI1_FS);
206 msleep(2);
207}
208
209static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
210{
211 mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
212 gpio_set_value(GPIO_PORTC + 20, 0);
213 mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
214 gpio_set_value(GPIO_PORTC + 22, 0);
215 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
216 gpio_set_value(GPIO_PORTC + 28, 0);
217 udelay(10);
218 gpio_set_value(GPIO_PORTC + 28, 1);
219 mxc_gpio_mode(PC20_PF_SSI1_FS);
220 mxc_gpio_mode(PC22_PF_SSI1_TXD);
221 msleep(2);
222}
223
224static struct imx_ssi_platform_data pca100_ssi_pdata = {
225 .ac97_reset = pca100_ac97_cold_reset,
226 .ac97_warm_reset = pca100_ac97_warm_reset,
227 .flags = IMX_SSI_USE_AC97,
228};
229
160static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, 230static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
161 void *data) 231 void *data)
162{ 232{
@@ -182,21 +252,79 @@ static struct imxmmc_platform_data sdhc_pdata = {
182 .exit = pca100_sdhc2_exit, 252 .exit = pca100_sdhc2_exit,
183}; 253};
184 254
255static int otg_phy_init(struct platform_device *pdev)
256{
257 gpio_set_value(OTG_PHY_CS_GPIO, 0);
258 return 0;
259}
260
261static struct mxc_usbh_platform_data otg_pdata = {
262 .init = otg_phy_init,
263 .portsc = MXC_EHCI_MODE_ULPI,
264 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
265};
266
267static int usbh2_phy_init(struct platform_device *pdev)
268{
269 gpio_set_value(USBH2_PHY_CS_GPIO, 0);
270 return 0;
271}
272
273static struct mxc_usbh_platform_data usbh2_pdata = {
274 .init = usbh2_phy_init,
275 .portsc = MXC_EHCI_MODE_ULPI,
276 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
277};
278
279static struct fsl_usb2_platform_data otg_device_pdata = {
280 .operating_mode = FSL_USB2_DR_DEVICE,
281 .phy_mode = FSL_USB2_PHY_ULPI,
282};
283
284static int otg_mode_host;
285
286static int __init pca100_otg_mode(char *options)
287{
288 if (!strcmp(options, "host"))
289 otg_mode_host = 1;
290 else if (!strcmp(options, "device"))
291 otg_mode_host = 0;
292 else
293 pr_info("otg_mode neither \"host\" nor \"device\". "
294 "Defaulting to device\n");
295 return 0;
296}
297__setup("otg_mode=", pca100_otg_mode);
298
185static void __init pca100_init(void) 299static void __init pca100_init(void)
186{ 300{
187 int ret; 301 int ret;
188 302
303 /* SSI unit */
304 mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
305 MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
306 MXC_AUDMUX_V1_PCR_TFCSEL(3) |
307 MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
308 MXC_AUDMUX_V1_PCR_RXDSEL(3));
309 mxc_audmux_v1_configure_port(3,
310 MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
311 MXC_AUDMUX_V1_PCR_TFCSEL(0) |
312 MXC_AUDMUX_V1_PCR_TFSDIR |
313 MXC_AUDMUX_V1_PCR_RXDSEL(0));
314
189 ret = mxc_gpio_setup_multiple_pins(pca100_pins, 315 ret = mxc_gpio_setup_multiple_pins(pca100_pins,
190 ARRAY_SIZE(pca100_pins), "PCA100"); 316 ARRAY_SIZE(pca100_pins), "PCA100");
191 if (ret) 317 if (ret)
192 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); 318 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
193 319
320 mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
321
194 mxc_register_device(&mxc_uart_device0, &uart_pdata); 322 mxc_register_device(&mxc_uart_device0, &uart_pdata);
195 323
196 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); 324 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
197 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 325 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
198 326
199 mxc_register_device(&mxc_nand_device, &pca100_nand_board_info); 327 mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
200 328
201 /* only the i2c master 1 is used on this CPU card */ 329 /* only the i2c master 1 is used on this CPU card */
202 i2c_register_board_info(1, pca100_i2c_devices, 330 i2c_register_board_info(1, pca100_i2c_devices,
@@ -220,6 +348,29 @@ static void __init pca100_init(void)
220 mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); 348 mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
221#endif 349#endif
222 350
351 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
352 gpio_direction_output(OTG_PHY_CS_GPIO, 1);
353 gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
354 gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
355
356#if defined(CONFIG_USB_ULPI)
357 if (otg_mode_host) {
358 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
359 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
360
361 mxc_register_device(&mxc_otg_host, &otg_pdata);
362 }
363
364 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
365 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
366
367 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
368#endif
369 if (!otg_mode_host) {
370 gpio_set_value(OTG_PHY_CS_GPIO, 0);
371 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
372 }
373
223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 374 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
224} 375}
225 376
@@ -233,9 +384,9 @@ static struct sys_timer pca100_timer = {
233}; 384};
234 385
235MACHINE_START(PCA100, "phyCARD-i.MX27") 386MACHINE_START(PCA100, "phyCARD-i.MX27")
236 .phys_io = AIPI_BASE_ADDR, 387 .phys_io = MX27_AIPI_BASE_ADDR,
237 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 388 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
238 .boot_params = PHYS_OFFSET + 0x100, 389 .boot_params = MX27_PHYS_OFFSET + 0x100,
239 .map_io = mx27_map_io, 390 .map_io = mx27_map_io,
240 .init_irq = mx27_init_irq, 391 .init_irq = mx27_init_irq,
241 .init_machine = pca100_init, 392 .init_machine = pca100_init,
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 906d59b0a7aa..035fbe046ec0 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -36,10 +36,12 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <mach/iomux.h> 39#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h> 40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
42#include <mach/spi.h> 42#include <mach/spi.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
43 45
44#include "devices.h" 46#include "devices.h"
45 47
@@ -96,6 +98,19 @@ static int pcm038_pins[] = {
96 PC17_PF_SSI4_RXD, 98 PC17_PF_SSI4_RXD,
97 PC18_PF_SSI4_TXD, 99 PC18_PF_SSI4_TXD,
98 PC19_PF_SSI4_CLK, 100 PC19_PF_SSI4_CLK,
101 /* USB host */
102 PA0_PF_USBH2_CLK,
103 PA1_PF_USBH2_DIR,
104 PA2_PF_USBH2_DATA7,
105 PA3_PF_USBH2_NXT,
106 PA4_PF_USBH2_STP,
107 PD19_AF_USBH2_DATA4,
108 PD20_AF_USBH2_DATA3,
109 PD21_AF_USBH2_DATA6,
110 PD22_AF_USBH2_DATA0,
111 PD23_AF_USBH2_DATA2,
112 PD24_AF_USBH2_DATA1,
113 PD26_AF_USBH2_DATA5,
99}; 114};
100 115
101/* 116/*
@@ -108,8 +123,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
108}; 123};
109 124
110static struct resource pcm038_sram_resource = { 125static struct resource pcm038_sram_resource = {
111 .start = CS1_BASE_ADDR, 126 .start = MX27_CS1_BASE_ADDR,
112 .end = CS1_BASE_ADDR + 512 * 1024 - 1, 127 .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
113 .flags = IORESOURCE_MEM, 128 .flags = IORESOURCE_MEM,
114}; 129};
115 130
@@ -173,9 +188,7 @@ static struct platform_device *platform_devices[] __initdata = {
173 * setup other stuffs to access the sram. */ 188 * setup other stuffs to access the sram. */
174static void __init pcm038_init_sram(void) 189static void __init pcm038_init_sram(void)
175{ 190{
176 __raw_writel(0x0000d843, CSCR_U(1)); 191 mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
177 __raw_writel(0x22252521, CSCR_L(1));
178 __raw_writel(0x22220a00, CSCR_A(1));
179} 192}
180 193
181static struct imxi2c_platform_data pcm038_i2c_1_data = { 194static struct imxi2c_platform_data pcm038_i2c_1_data = {
@@ -279,6 +292,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
279 } 292 }
280}; 293};
281 294
295static struct mxc_usbh_platform_data usbh2_pdata = {
296 .portsc = MXC_EHCI_MODE_ULPI,
297 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
298};
299
282static void __init pcm038_init(void) 300static void __init pcm038_init(void)
283{ 301{
284 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), 302 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
@@ -291,7 +309,7 @@ static void __init pcm038_init(void)
291 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 309 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
292 310
293 mxc_gpio_mode(PE16_AF_OWIRE); 311 mxc_gpio_mode(PE16_AF_OWIRE);
294 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); 312 mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
295 313
296 /* only the i2c master 1 is used on this CPU card */ 314 /* only the i2c master 1 is used on this CPU card */
297 i2c_register_board_info(1, pcm038_i2c_devices, 315 i2c_register_board_info(1, pcm038_i2c_devices,
@@ -311,6 +329,8 @@ static void __init pcm038_init(void)
311 spi_register_board_info(pcm038_spi_board_info, 329 spi_register_board_info(pcm038_spi_board_info,
312 ARRAY_SIZE(pcm038_spi_board_info)); 330 ARRAY_SIZE(pcm038_spi_board_info));
313 331
332 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
333
314 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 334 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
315 335
316#ifdef CONFIG_MACH_PCM970_BASEBOARD 336#ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -328,9 +348,9 @@ static struct sys_timer pcm038_timer = {
328}; 348};
329 349
330MACHINE_START(PCM038, "phyCORE-i.MX27") 350MACHINE_START(PCM038, "phyCORE-i.MX27")
331 .phys_io = AIPI_BASE_ADDR, 351 .phys_io = MX27_AIPI_BASE_ADDR,
332 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 352 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
333 .boot_params = PHYS_OFFSET + 0x100, 353 .boot_params = MX27_PHYS_OFFSET + 0x100,
334 .map_io = mx27_map_io, 354 .map_io = mx27_map_io,
335 .init_irq = mx27_init_irq, 355 .init_irq = mx27_init_irq,
336 .init_machine = pcm038_init, 356 .init_machine = pcm038_init,
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-mx2/mm-imx21.c
new file mode 100644
index 000000000000..64134314d012
--- /dev/null
+++ b/arch/arm/mach-mx2/mm-imx21.c
@@ -0,0 +1,83 @@
1/*
2 * arch/arm/mach-mx2/mm-imx21.c
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/mm.h>
22#include <linux/init.h>
23#include <mach/hardware.h>
24#include <mach/common.h>
25#include <asm/pgtable.h>
26#include <asm/mach/map.h>
27
28/* MX21 memory map definition */
29static struct map_desc imx21_io_desc[] __initdata = {
30 /*
31 * this fixed mapping covers:
32 * - AIPI1
33 * - AIPI2
34 * - AITC
35 * - ROM Patch
36 * - and some reserved space
37 */
38 {
39 .virtual = MX21_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
41 .length = MX21_AIPI_SIZE,
42 .type = MT_DEVICE
43 },
44 /*
45 * this fixed mapping covers:
46 * - CSI
47 * - ATA
48 */
49 {
50 .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
52 .length = MX21_SAHB1_SIZE,
53 .type = MT_DEVICE
54 },
55 /*
56 * this fixed mapping covers:
57 * - EMI
58 */
59 {
60 .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
62 .length = MX21_X_MEMC_SIZE,
63 .type = MT_DEVICE
64 },
65};
66
67/*
68 * Initialize the memory map. It is called during the
69 * system startup to create static physical to virtual
70 * memory map for the IO modules.
71 */
72void __init mx21_map_io(void)
73{
74 mxc_set_cpu_type(MXC_CPU_MX21);
75 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
76
77 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
78}
79
80void __init mx21_init_irq(void)
81{
82 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
83}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/mm-imx27.c
index ae8f759134d1..3366ed44cfd5 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/mm-imx27.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * generic.c 2 * arch/arm/mach-mx2/mm-imx27.c
3 * 3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * 5 *
@@ -26,7 +26,7 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28/* MX27 memory map definition */ 28/* MX27 memory map definition */
29static struct map_desc mxc_io_desc[] __initdata = { 29static struct map_desc imx27_io_desc[] __initdata = {
30 /* 30 /*
31 * this fixed mapping covers: 31 * this fixed mapping covers:
32 * - AIPI1 32 * - AIPI1
@@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
36 * - and some reserved space 36 * - and some reserved space
37 */ 37 */
38 { 38 {
39 .virtual = AIPI_BASE_ADDR_VIRT, 39 .virtual = MX27_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(AIPI_BASE_ADDR), 40 .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
41 .length = AIPI_SIZE, 41 .length = MX27_AIPI_SIZE,
42 .type = MT_DEVICE 42 .type = MT_DEVICE
43 }, 43 },
44 /* 44 /*
@@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
47 * - ATA 47 * - ATA
48 */ 48 */
49 { 49 {
50 .virtual = SAHB1_BASE_ADDR_VIRT, 50 .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), 51 .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
52 .length = SAHB1_SIZE, 52 .length = MX27_SAHB1_SIZE,
53 .type = MT_DEVICE 53 .type = MT_DEVICE
54 }, 54 },
55 /* 55 /*
@@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
57 * - EMI 57 * - EMI
58 */ 58 */
59 { 59 {
60 .virtual = X_MEMC_BASE_ADDR_VIRT, 60 .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), 61 .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
62 .length = X_MEMC_SIZE, 62 .length = MX27_X_MEMC_SIZE,
63 .type = MT_DEVICE 63 .type = MT_DEVICE
64 } 64 },
65}; 65};
66 66
67/* 67/*
@@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = {
69 * system startup to create static physical to virtual 69 * system startup to create static physical to virtual
70 * memory map for the IO modules. 70 * memory map for the IO modules.
71 */ 71 */
72void __init mx21_map_io(void)
73{
74 mxc_set_cpu_type(MXC_CPU_MX21);
75 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
76
77 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
78}
79
80void __init mx27_map_io(void) 72void __init mx27_map_io(void)
81{ 73{
82 mxc_set_cpu_type(MXC_CPU_MX27); 74 mxc_set_cpu_type(MXC_CPU_MX27);
83 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); 75 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
84 76
85 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 77 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
86} 78}
87 79
88void __init mx27_init_irq(void) 80void __init mx27_init_irq(void)
89{ 81{
90 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 82 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
91} 83}
92
93void __init mx21_init_irq(void)
94{
95 mx27_init_irq();
96}
97
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 3cb7f457e5d0..4aafd5b8b85b 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -24,7 +24,7 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25 25
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/iomux.h> 27#include <mach/iomux-mx27.h>
28#include <mach/imxfb.h> 28#include <mach/imxfb.h>
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/mmc.h> 30#include <mach/mmc.h>
@@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = {
190 190
191static struct resource pcm970_sja1000_resources[] = { 191static struct resource pcm970_sja1000_resources[] = {
192 { 192 {
193 .start = CS4_BASE_ADDR, 193 .start = MX27_CS4_BASE_ADDR,
194 .end = CS4_BASE_ADDR + 0x100 - 1, 194 .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
195 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
196 }, { 196 }, {
197 .start = IRQ_GPIOE(19), 197 .start = IRQ_GPIOE(19),
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index 40a485cdc10e..1c0c835b2252 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -26,12 +26,12 @@
26 26
27static struct resource uart0[] = { 27static struct resource uart0[] = {
28 { 28 {
29 .start = UART1_BASE_ADDR, 29 .start = MX2x_UART1_BASE_ADDR,
30 .end = UART1_BASE_ADDR + 0x0B5, 30 .end = MX2x_UART1_BASE_ADDR + 0x0B5,
31 .flags = IORESOURCE_MEM, 31 .flags = IORESOURCE_MEM,
32 }, { 32 }, {
33 .start = MXC_INT_UART1, 33 .start = MX2x_INT_UART1,
34 .end = MXC_INT_UART1, 34 .end = MX2x_INT_UART1,
35 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
36 }, 36 },
37}; 37};
@@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = {
45 45
46static struct resource uart1[] = { 46static struct resource uart1[] = {
47 { 47 {
48 .start = UART2_BASE_ADDR, 48 .start = MX2x_UART2_BASE_ADDR,
49 .end = UART2_BASE_ADDR + 0x0B5, 49 .end = MX2x_UART2_BASE_ADDR + 0x0B5,
50 .flags = IORESOURCE_MEM, 50 .flags = IORESOURCE_MEM,
51 }, { 51 }, {
52 .start = MXC_INT_UART2, 52 .start = MX2x_INT_UART2,
53 .end = MXC_INT_UART2, 53 .end = MX2x_INT_UART2,
54 .flags = IORESOURCE_IRQ, 54 .flags = IORESOURCE_IRQ,
55 }, 55 },
56}; 56};
@@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = {
64 64
65static struct resource uart2[] = { 65static struct resource uart2[] = {
66 { 66 {
67 .start = UART3_BASE_ADDR, 67 .start = MX2x_UART3_BASE_ADDR,
68 .end = UART3_BASE_ADDR + 0x0B5, 68 .end = MX2x_UART3_BASE_ADDR + 0x0B5,
69 .flags = IORESOURCE_MEM, 69 .flags = IORESOURCE_MEM,
70 }, { 70 }, {
71 .start = MXC_INT_UART3, 71 .start = MX2x_INT_UART3,
72 .end = MXC_INT_UART3, 72 .end = MX2x_INT_UART3,
73 .flags = IORESOURCE_IRQ, 73 .flags = IORESOURCE_IRQ,
74 }, 74 },
75}; 75};
@@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = {
83 83
84static struct resource uart3[] = { 84static struct resource uart3[] = {
85 { 85 {
86 .start = UART4_BASE_ADDR, 86 .start = MX2x_UART4_BASE_ADDR,
87 .end = UART4_BASE_ADDR + 0x0B5, 87 .end = MX2x_UART4_BASE_ADDR + 0x0B5,
88 .flags = IORESOURCE_MEM, 88 .flags = IORESOURCE_MEM,
89 }, { 89 }, {
90 .start = MXC_INT_UART4, 90 .start = MX2x_INT_UART4,
91 .end = MXC_INT_UART4, 91 .end = MX2x_INT_UART4,
92 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
93 }, 93 },
94}; 94};
@@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = {
103#ifdef CONFIG_MACH_MX27 103#ifdef CONFIG_MACH_MX27
104static struct resource uart4[] = { 104static struct resource uart4[] = {
105 { 105 {
106 .start = UART5_BASE_ADDR, 106 .start = MX27_UART5_BASE_ADDR,
107 .end = UART5_BASE_ADDR + 0x0B5, 107 .end = MX27_UART5_BASE_ADDR + 0x0B5,
108 .flags = IORESOURCE_MEM, 108 .flags = IORESOURCE_MEM,
109 }, { 109 }, {
110 .start = MXC_INT_UART5, 110 .start = MX27_INT_UART5,
111 .end = MXC_INT_UART5, 111 .end = MX27_INT_UART5,
112 .flags = IORESOURCE_IRQ, 112 .flags = IORESOURCE_IRQ,
113 }, 113 },
114}; 114};
@@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = {
122 122
123static struct resource uart5[] = { 123static struct resource uart5[] = {
124 { 124 {
125 .start = UART6_BASE_ADDR, 125 .start = MX27_UART6_BASE_ADDR,
126 .end = UART6_BASE_ADDR + 0x0B5, 126 .end = MX27_UART6_BASE_ADDR + 0x0B5,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, { 128 }, {
129 .start = MXC_INT_UART6, 129 .start = MX27_INT_UART6,
130 .end = MXC_INT_UART6, 130 .end = MX27_INT_UART6,
131 .flags = IORESOURCE_IRQ, 131 .flags = IORESOURCE_IRQ,
132 }, 132 },
133}; 133};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 02:46:16 -0500