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-rw-r--r--arch/arm/mach-mx2/Kconfig35
-rw-r--r--arch/arm/mach-mx2/Makefile3
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c2
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c11
-rw-r--r--arch/arm/mach-mx2/devices.c332
-rw-r--r--arch/arm/mach-mx2/devices.h9
-rw-r--r--arch/arm/mach-mx2/eukrea_cpuimx27.c234
-rw-r--r--arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c249
-rw-r--r--arch/arm/mach-mx2/generic.c12
-rw-r--r--arch/arm/mach-mx2/mx21ads.c44
-rw-r--r--arch/arm/mach-mx2/mx27ads.c38
-rw-r--r--arch/arm/mach-mx2/mx27lite.c2
-rw-r--r--arch/arm/mach-mx2/mx27pdk.c2
-rw-r--r--arch/arm/mach-mx2/pca100.c244
-rw-r--r--arch/arm/mach-mx2/pcm038.c17
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c112
16 files changed, 1164 insertions, 182 deletions
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c77da586b71d..c8a2eac4d13c 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD
53 53
54endchoice 54endchoice
55 55
56config MACH_EUKREA_CPUIMX27
57 bool "Eukrea CPUIMX27 module"
58 depends on MACH_MX27
59 help
60 Include support for Eukrea CPUIMX27 platform. This includes
61 specific configurations for the module and its peripherals.
62
63config MACH_EUKREA_CPUIMX27_USESDHC2
64 bool "CPUIMX27 integrates SDHC2 module"
65 depends on MACH_EUKREA_CPUIMX27
66 help
67 This adds support for the internal SDHC2 used on CPUIMX27 used
68 for wifi or eMMC.
69
70choice
71 prompt "Baseboard"
72 depends on MACH_EUKREA_CPUIMX27
73 default MACH_EUKREA_MBIMX27_BASEBOARD
74
75config MACH_EUKREA_MBIMX27_BASEBOARD
76 prompt "Eukrea MBIMX27 development board"
77 bool
78 help
79 This adds board specific devices that can be found on Eukrea's
80 MBIMX27 evaluation board.
81
82endchoice
83
56config MACH_MX27_3DS 84config MACH_MX27_3DS
57 bool "MX27PDK platform" 85 bool "MX27PDK platform"
58 depends on MACH_MX27 86 depends on MACH_MX27
@@ -67,4 +95,11 @@ config MACH_MX27LITE
67 Include support for MX27 LITEKIT platform. This includes specific 95 Include support for MX27 LITEKIT platform. This includes specific
68 configurations for the board and its peripherals. 96 configurations for the board and its peripherals.
69 97
98config MACH_PCA100
99 bool "Phytec phyCARD-s (pca100)"
100 depends on MACH_MX27
101 help
102 Include support for phyCARD-s (aka pca100) platform. This
103 includes specific configurations for the module and its peripherals.
104
70endif 105endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index b9b1cca4e9bc..19560f045632 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o
17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
18obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o 18obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
19obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o 19obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
20obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
21obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
22obj-$(CONFIG_MACH_PCA100) += pca100.o
20 23
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 0850fb88ec15..eede79855f4a 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
1004 clk_enable(&uart_clk[0]); 1004 clk_enable(&uart_clk[0]);
1005#endif 1005#endif
1006 1006
1007 mxc_timer_init(&gpt_clk[0]); 1007 mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
1008 return 0; 1008 return 0;
1009} 1009}
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 2c971442f3f2..4089951acb47 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = {
643 _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk) 643 _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
644 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 644 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
645 _REGISTER_CLOCK(NULL, "csi", csi_clk) 645 _REGISTER_CLOCK(NULL, "csi", csi_clk)
646 _REGISTER_CLOCK(NULL, "usb", usb_clk) 646 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
647 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
648 _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
649 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
650 _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
651 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
652 _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
653 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
647 _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) 654 _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
648 _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) 655 _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
649 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) 656 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref)
748 clk_enable(&uart1_clk); 755 clk_enable(&uart1_clk);
749#endif 756#endif
750 757
751 mxc_timer_init(&gpt1_clk); 758 mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
752 759
753 return 0; 760 return 0;
754} 761}
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0f1b3674327..50199aff0143 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,45 +40,87 @@
40#include "devices.h" 40#include "devices.h"
41 41
42/* 42/*
43 * Resource definition for the MXC IrDA 43 * SPI master controller
44 *
45 * - i.MX1: 2 channel (slighly different register setting)
46 * - i.MX21: 2 channel
47 * - i.MX27: 3 channel
44 */ 48 */
45static struct resource mxc_irda_resources[] = { 49static struct resource mxc_spi_resources0[] = {
46 [0] = { 50 {
47 .start = UART3_BASE_ADDR, 51 .start = CSPI1_BASE_ADDR,
48 .end = UART3_BASE_ADDR + SZ_4K - 1, 52 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
49 .flags = IORESOURCE_MEM, 53 .flags = IORESOURCE_MEM,
54 }, {
55 .start = MXC_INT_CSPI1,
56 .end = MXC_INT_CSPI1,
57 .flags = IORESOURCE_IRQ,
50 }, 58 },
51 [1] = { 59};
52 .start = MXC_INT_UART3, 60
53 .end = MXC_INT_UART3, 61static struct resource mxc_spi_resources1[] = {
54 .flags = IORESOURCE_IRQ, 62 {
63 .start = CSPI2_BASE_ADDR,
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
65 .flags = IORESOURCE_MEM,
66 }, {
67 .start = MXC_INT_CSPI2,
68 .end = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
55 }, 70 },
56}; 71};
57 72
58/* Platform Data for MXC IrDA */ 73#ifdef CONFIG_MACH_MX27
59struct platform_device mxc_irda_device = { 74static struct resource mxc_spi_resources2[] = {
60 .name = "mxc_irda", 75 {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
79 }, {
80 .start = MXC_INT_CSPI3,
81 .end = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
83 },
84};
85#endif
86
87struct platform_device mxc_spi_device0 = {
88 .name = "spi_imx",
61 .id = 0, 89 .id = 0,
62 .num_resources = ARRAY_SIZE(mxc_irda_resources), 90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
63 .resource = mxc_irda_resources, 91 .resource = mxc_spi_resources0,
92};
93
94struct platform_device mxc_spi_device1 = {
95 .name = "spi_imx",
96 .id = 1,
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
99};
100
101#ifdef CONFIG_MACH_MX27
102struct platform_device mxc_spi_device2 = {
103 .name = "spi_imx",
104 .id = 2,
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
64}; 107};
108#endif
65 109
66/* 110/*
67 * General Purpose Timer 111 * General Purpose Timer
68 * - i.MX1: 2 timer (slighly different register handling) 112 * - i.MX21: 3 timers
69 * - i.MX21: 3 timer 113 * - i.MX27: 6 timers
70 * - i.MX27: 6 timer
71 */ 114 */
72 115
73/* We use gpt0 as system timer, so do not add a device for this one */ 116/* We use gpt0 as system timer, so do not add a device for this one */
74 117
75static struct resource timer1_resources[] = { 118static struct resource timer1_resources[] = {
76 [0] = { 119 {
77 .start = GPT2_BASE_ADDR, 120 .start = GPT2_BASE_ADDR,
78 .end = GPT2_BASE_ADDR + 0x17, 121 .end = GPT2_BASE_ADDR + 0x17,
79 .flags = IORESOURCE_MEM 122 .flags = IORESOURCE_MEM,
80 }, 123 }, {
81 [1] = {
82 .start = MXC_INT_GPT2, 124 .start = MXC_INT_GPT2,
83 .end = MXC_INT_GPT2, 125 .end = MXC_INT_GPT2,
84 .flags = IORESOURCE_IRQ, 126 .flags = IORESOURCE_IRQ,
@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
89 .name = "imx_gpt", 131 .name = "imx_gpt",
90 .id = 1, 132 .id = 1,
91 .num_resources = ARRAY_SIZE(timer1_resources), 133 .num_resources = ARRAY_SIZE(timer1_resources),
92 .resource = timer1_resources 134 .resource = timer1_resources,
93}; 135};
94 136
95static struct resource timer2_resources[] = { 137static struct resource timer2_resources[] = {
96 [0] = { 138 {
97 .start = GPT3_BASE_ADDR, 139 .start = GPT3_BASE_ADDR,
98 .end = GPT3_BASE_ADDR + 0x17, 140 .end = GPT3_BASE_ADDR + 0x17,
99 .flags = IORESOURCE_MEM 141 .flags = IORESOURCE_MEM,
100 }, 142 }, {
101 [1] = {
102 .start = MXC_INT_GPT3, 143 .start = MXC_INT_GPT3,
103 .end = MXC_INT_GPT3, 144 .end = MXC_INT_GPT3,
104 .flags = IORESOURCE_IRQ, 145 .flags = IORESOURCE_IRQ,
@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
109 .name = "imx_gpt", 150 .name = "imx_gpt",
110 .id = 2, 151 .id = 2,
111 .num_resources = ARRAY_SIZE(timer2_resources), 152 .num_resources = ARRAY_SIZE(timer2_resources),
112 .resource = timer2_resources 153 .resource = timer2_resources,
113}; 154};
114 155
115#ifdef CONFIG_MACH_MX27 156#ifdef CONFIG_MACH_MX27
116static struct resource timer3_resources[] = { 157static struct resource timer3_resources[] = {
117 [0] = { 158 {
118 .start = GPT4_BASE_ADDR, 159 .start = GPT4_BASE_ADDR,
119 .end = GPT4_BASE_ADDR + 0x17, 160 .end = GPT4_BASE_ADDR + 0x17,
120 .flags = IORESOURCE_MEM 161 .flags = IORESOURCE_MEM,
121 }, 162 }, {
122 [1] = {
123 .start = MXC_INT_GPT4, 163 .start = MXC_INT_GPT4,
124 .end = MXC_INT_GPT4, 164 .end = MXC_INT_GPT4,
125 .flags = IORESOURCE_IRQ, 165 .flags = IORESOURCE_IRQ,
@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
130 .name = "imx_gpt", 170 .name = "imx_gpt",
131 .id = 3, 171 .id = 3,
132 .num_resources = ARRAY_SIZE(timer3_resources), 172 .num_resources = ARRAY_SIZE(timer3_resources),
133 .resource = timer3_resources 173 .resource = timer3_resources,
134}; 174};
135 175
136static struct resource timer4_resources[] = { 176static struct resource timer4_resources[] = {
137 [0] = { 177 {
138 .start = GPT5_BASE_ADDR, 178 .start = GPT5_BASE_ADDR,
139 .end = GPT5_BASE_ADDR + 0x17, 179 .end = GPT5_BASE_ADDR + 0x17,
140 .flags = IORESOURCE_MEM 180 .flags = IORESOURCE_MEM,
141 }, 181 }, {
142 [1] = {
143 .start = MXC_INT_GPT5, 182 .start = MXC_INT_GPT5,
144 .end = MXC_INT_GPT5, 183 .end = MXC_INT_GPT5,
145 .flags = IORESOURCE_IRQ, 184 .flags = IORESOURCE_IRQ,
@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
150 .name = "imx_gpt", 189 .name = "imx_gpt",
151 .id = 4, 190 .id = 4,
152 .num_resources = ARRAY_SIZE(timer4_resources), 191 .num_resources = ARRAY_SIZE(timer4_resources),
153 .resource = timer4_resources 192 .resource = timer4_resources,
154}; 193};
155 194
156static struct resource timer5_resources[] = { 195static struct resource timer5_resources[] = {
157 [0] = { 196 {
158 .start = GPT6_BASE_ADDR, 197 .start = GPT6_BASE_ADDR,
159 .end = GPT6_BASE_ADDR + 0x17, 198 .end = GPT6_BASE_ADDR + 0x17,
160 .flags = IORESOURCE_MEM 199 .flags = IORESOURCE_MEM,
161 }, 200 }, {
162 [1] = {
163 .start = MXC_INT_GPT6, 201 .start = MXC_INT_GPT6,
164 .end = MXC_INT_GPT6, 202 .end = MXC_INT_GPT6,
165 .flags = IORESOURCE_IRQ, 203 .flags = IORESOURCE_IRQ,
@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
170 .name = "imx_gpt", 208 .name = "imx_gpt",
171 .id = 5, 209 .id = 5,
172 .num_resources = ARRAY_SIZE(timer5_resources), 210 .num_resources = ARRAY_SIZE(timer5_resources),
173 .resource = timer5_resources 211 .resource = timer5_resources,
174}; 212};
175#endif 213#endif
176 214
@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
214 { 252 {
215 .start = NFC_BASE_ADDR, 253 .start = NFC_BASE_ADDR,
216 .end = NFC_BASE_ADDR + 0xfff, 254 .end = NFC_BASE_ADDR + 0xfff,
217 .flags = IORESOURCE_MEM 255 .flags = IORESOURCE_MEM,
218 }, { 256 }, {
219 .start = MXC_INT_NANDFC, 257 .start = MXC_INT_NANDFC,
220 .end = MXC_INT_NANDFC, 258 .end = MXC_INT_NANDFC,
221 .flags = IORESOURCE_IRQ 259 .flags = IORESOURCE_IRQ,
222 }, 260 },
223}; 261};
224 262
@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
240 .start = LCDC_BASE_ADDR, 278 .start = LCDC_BASE_ADDR,
241 .end = LCDC_BASE_ADDR + 0xFFF, 279 .end = LCDC_BASE_ADDR + 0xFFF,
242 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
243 }, 281 }, {
244 {
245 .start = MXC_INT_LCDC, 282 .start = MXC_INT_LCDC,
246 .end = MXC_INT_LCDC, 283 .end = MXC_INT_LCDC,
247 .flags = IORESOURCE_IRQ, 284 .flags = IORESOURCE_IRQ,
@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
264 { 301 {
265 .start = FEC_BASE_ADDR, 302 .start = FEC_BASE_ADDR,
266 .end = FEC_BASE_ADDR + 0xfff, 303 .end = FEC_BASE_ADDR + 0xfff,
267 .flags = IORESOURCE_MEM 304 .flags = IORESOURCE_MEM,
268 }, { 305 }, {
269 .start = MXC_INT_FEC, 306 .start = MXC_INT_FEC,
270 .end = MXC_INT_FEC, 307 .end = MXC_INT_FEC,
271 .flags = IORESOURCE_IRQ 308 .flags = IORESOURCE_IRQ,
272 }, 309 },
273}; 310};
274 311
@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
281#endif 318#endif
282 319
283static struct resource mxc_i2c_1_resources[] = { 320static struct resource mxc_i2c_1_resources[] = {
284 [0] = { 321 {
285 .start = I2C_BASE_ADDR, 322 .start = I2C_BASE_ADDR,
286 .end = I2C_BASE_ADDR + 0x0fff, 323 .end = I2C_BASE_ADDR + 0x0fff,
287 .flags = IORESOURCE_MEM 324 .flags = IORESOURCE_MEM,
288 }, 325 }, {
289 [1] = {
290 .start = MXC_INT_I2C, 326 .start = MXC_INT_I2C,
291 .end = MXC_INT_I2C, 327 .end = MXC_INT_I2C,
292 .flags = IORESOURCE_IRQ 328 .flags = IORESOURCE_IRQ,
293 } 329 }
294}; 330};
295 331
@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
297 .name = "imx-i2c", 333 .name = "imx-i2c",
298 .id = 0, 334 .id = 0,
299 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), 335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
300 .resource = mxc_i2c_1_resources 336 .resource = mxc_i2c_1_resources,
301}; 337};
302 338
303#ifdef CONFIG_MACH_MX27 339#ifdef CONFIG_MACH_MX27
304static struct resource mxc_i2c_2_resources[] = { 340static struct resource mxc_i2c_2_resources[] = {
305 [0] = { 341 {
306 .start = I2C2_BASE_ADDR, 342 .start = I2C2_BASE_ADDR,
307 .end = I2C2_BASE_ADDR + 0x0fff, 343 .end = I2C2_BASE_ADDR + 0x0fff,
308 .flags = IORESOURCE_MEM 344 .flags = IORESOURCE_MEM,
309 }, 345 }, {
310 [1] = {
311 .start = MXC_INT_I2C2, 346 .start = MXC_INT_I2C2,
312 .end = MXC_INT_I2C2, 347 .end = MXC_INT_I2C2,
313 .flags = IORESOURCE_IRQ 348 .flags = IORESOURCE_IRQ,
314 } 349 }
315}; 350};
316 351
@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
318 .name = "imx-i2c", 353 .name = "imx-i2c",
319 .id = 1, 354 .id = 1,
320 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), 355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
321 .resource = mxc_i2c_2_resources 356 .resource = mxc_i2c_2_resources,
322}; 357};
323#endif 358#endif
324 359
325static struct resource mxc_pwm_resources[] = { 360static struct resource mxc_pwm_resources[] = {
326 [0] = { 361 {
327 .start = PWM_BASE_ADDR, 362 .start = PWM_BASE_ADDR,
328 .end = PWM_BASE_ADDR + 0x0fff, 363 .end = PWM_BASE_ADDR + 0x0fff,
329 .flags = IORESOURCE_MEM 364 .flags = IORESOURCE_MEM,
330 }, 365 }, {
331 [1] = {
332 .start = MXC_INT_PWM, 366 .start = MXC_INT_PWM,
333 .end = MXC_INT_PWM, 367 .end = MXC_INT_PWM,
334 .flags = IORESOURCE_IRQ, 368 .flags = IORESOURCE_IRQ,
@@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = {
339 .name = "mxc_pwm", 373 .name = "mxc_pwm",
340 .id = 0, 374 .id = 0,
341 .num_resources = ARRAY_SIZE(mxc_pwm_resources), 375 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
342 .resource = mxc_pwm_resources 376 .resource = mxc_pwm_resources,
343}; 377};
344 378
345/* 379/*
346 * Resource definition for the MXC SDHC 380 * Resource definition for the MXC SDHC
347 */ 381 */
348static struct resource mxc_sdhc1_resources[] = { 382static struct resource mxc_sdhc1_resources[] = {
349 [0] = { 383 {
350 .start = SDHC1_BASE_ADDR, 384 .start = SDHC1_BASE_ADDR,
351 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 385 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
352 .flags = IORESOURCE_MEM, 386 .flags = IORESOURCE_MEM,
353 }, 387 }, {
354 [1] = { 388 .start = MXC_INT_SDHC1,
355 .start = MXC_INT_SDHC1, 389 .end = MXC_INT_SDHC1,
356 .end = MXC_INT_SDHC1, 390 .flags = IORESOURCE_IRQ,
357 .flags = IORESOURCE_IRQ, 391 }, {
358 }, 392 .start = DMA_REQ_SDHC1,
359 [2] = { 393 .end = DMA_REQ_SDHC1,
360 .start = DMA_REQ_SDHC1, 394 .flags = IORESOURCE_DMA,
361 .end = DMA_REQ_SDHC1, 395 },
362 .flags = IORESOURCE_DMA
363 },
364}; 396};
365 397
366static u64 mxc_sdhc1_dmamask = 0xffffffffUL; 398static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
@@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = {
377}; 409};
378 410
379static struct resource mxc_sdhc2_resources[] = { 411static struct resource mxc_sdhc2_resources[] = {
380 [0] = { 412 {
381 .start = SDHC2_BASE_ADDR, 413 .start = SDHC2_BASE_ADDR,
382 .end = SDHC2_BASE_ADDR + SZ_4K - 1, 414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
383 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
384 }, 416 }, {
385 [1] = { 417 .start = MXC_INT_SDHC2,
386 .start = MXC_INT_SDHC2, 418 .end = MXC_INT_SDHC2,
387 .end = MXC_INT_SDHC2, 419 .flags = IORESOURCE_IRQ,
388 .flags = IORESOURCE_IRQ, 420 }, {
389 }, 421 .start = DMA_REQ_SDHC2,
390 [2] = { 422 .end = DMA_REQ_SDHC2,
391 .start = DMA_REQ_SDHC2, 423 .flags = IORESOURCE_DMA,
392 .end = DMA_REQ_SDHC2, 424 },
393 .flags = IORESOURCE_DMA
394 },
395}; 425};
396 426
397static u64 mxc_sdhc2_dmamask = 0xffffffffUL; 427static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
407 .resource = mxc_sdhc2_resources, 437 .resource = mxc_sdhc2_resources,
408}; 438};
409 439
440#ifdef CONFIG_MACH_MX27
441static struct resource otg_resources[] = {
442 {
443 .start = OTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM,
446 }, {
447 .start = MXC_INT_USB3,
448 .end = MXC_INT_USB3,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static u64 otg_dmamask = 0xffffffffUL;
454
455/* OTG gadget device */
456struct platform_device mxc_otg_udc_device = {
457 .name = "fsl-usb2-udc",
458 .id = -1,
459 .dev = {
460 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL,
462 },
463 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources),
465};
466
467/* OTG host */
468struct platform_device mxc_otg_host = {
469 .name = "mxc-ehci",
470 .id = 0,
471 .dev = {
472 .coherent_dma_mask = 0xffffffff,
473 .dma_mask = &otg_dmamask,
474 },
475 .resource = otg_resources,
476 .num_resources = ARRAY_SIZE(otg_resources),
477};
478
479/* USB host 1 */
480
481static u64 usbh1_dmamask = 0xffffffffUL;
482
483static struct resource mxc_usbh1_resources[] = {
484 {
485 .start = OTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM,
488 }, {
489 .start = MXC_INT_USB1,
490 .end = MXC_INT_USB1,
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
495struct platform_device mxc_usbh1 = {
496 .name = "mxc-ehci",
497 .id = 1,
498 .dev = {
499 .coherent_dma_mask = 0xffffffff,
500 .dma_mask = &usbh1_dmamask,
501 },
502 .resource = mxc_usbh1_resources,
503 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
504};
505
506/* USB host 2 */
507static u64 usbh2_dmamask = 0xffffffffUL;
508
509static struct resource mxc_usbh2_resources[] = {
510 {
511 .start = OTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM,
514 }, {
515 .start = MXC_INT_USB2,
516 .end = MXC_INT_USB2,
517 .flags = IORESOURCE_IRQ,
518 },
519};
520
521struct platform_device mxc_usbh2 = {
522 .name = "mxc-ehci",
523 .id = 2,
524 .dev = {
525 .coherent_dma_mask = 0xffffffff,
526 .dma_mask = &usbh2_dmamask,
527 },
528 .resource = mxc_usbh2_resources,
529 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
530};
531#endif
532
410/* GPIO port description */ 533/* GPIO port description */
411static struct mxc_gpio_port imx_gpio_ports[] = { 534static struct mxc_gpio_port imx_gpio_ports[] = {
412 [0] = { 535 {
413 .chip.label = "gpio-0", 536 .chip.label = "gpio-0",
414 .irq = MXC_INT_GPIO, 537 .irq = MXC_INT_GPIO,
415 .base = IO_ADDRESS(GPIO_BASE_ADDR), 538 .base = IO_ADDRESS(GPIO_BASE_ADDR),
416 .virtual_irq_start = MXC_GPIO_IRQ_START, 539 .virtual_irq_start = MXC_GPIO_IRQ_START,
417 }, 540 }, {
418 [1] = {
419 .chip.label = "gpio-1", 541 .chip.label = "gpio-1",
420 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), 542 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
421 .virtual_irq_start = MXC_GPIO_IRQ_START + 32, 543 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
422 }, 544 }, {
423 [2] = {
424 .chip.label = "gpio-2", 545 .chip.label = "gpio-2",
425 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), 546 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
426 .virtual_irq_start = MXC_GPIO_IRQ_START + 64, 547 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
427 }, 548 }, {
428 [3] = {
429 .chip.label = "gpio-3", 549 .chip.label = "gpio-3",
430 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), 550 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
431 .virtual_irq_start = MXC_GPIO_IRQ_START + 96, 551 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
432 }, 552 }, {
433 [4] = {
434 .chip.label = "gpio-4", 553 .chip.label = "gpio-4",
435 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), 554 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
436 .virtual_irq_start = MXC_GPIO_IRQ_START + 128, 555 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
437 }, 556 }, {
438 [5] = {
439 .chip.label = "gpio-5", 557 .chip.label = "gpio-5",
440 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), 558 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
441 .virtual_irq_start = MXC_GPIO_IRQ_START + 160, 559 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 049005bb6aa9..d315406d6725 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3;
4extern struct platform_device mxc_gpt4; 4extern struct platform_device mxc_gpt4;
5extern struct platform_device mxc_gpt5; 5extern struct platform_device mxc_gpt5;
6extern struct platform_device mxc_wdt; 6extern struct platform_device mxc_wdt;
7extern struct platform_device mxc_irda_device;
8extern struct platform_device mxc_uart_device0; 7extern struct platform_device mxc_uart_device0;
9extern struct platform_device mxc_uart_device1; 8extern struct platform_device mxc_uart_device1;
10extern struct platform_device mxc_uart_device2; 9extern struct platform_device mxc_uart_device2;
@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0;
20extern struct platform_device mxc_i2c_device1; 19extern struct platform_device mxc_i2c_device1;
21extern struct platform_device mxc_sdhc_device0; 20extern struct platform_device mxc_sdhc_device0;
22extern struct platform_device mxc_sdhc_device1; 21extern struct platform_device mxc_sdhc_device1;
22extern struct platform_device mxc_otg_udc_device;
23extern struct platform_device mxc_otg_host;
24extern struct platform_device mxc_usbh1;
25extern struct platform_device mxc_usbh2;
26extern struct platform_device mxc_spi_device0;
27extern struct platform_device mxc_spi_device1;
28extern struct platform_device mxc_spi_device2;
29
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
new file mode 100644
index 000000000000..7b187606682c
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -0,0 +1,234 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm038.c which is :
5 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
6 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/mtd/plat-ram.h>
26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h>
28#include <linux/serial_8250.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/mach/map.h>
34
35#include <mach/board-eukrea_cpuimx27.h>
36#include <mach/common.h>
37#include <mach/hardware.h>
38#include <mach/i2c.h>
39#include <mach/iomux.h>
40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h>
42
43#include "devices.h"
44
45static int eukrea_cpuimx27_pins[] = {
46 /* UART1 */
47 PE12_PF_UART1_TXD,
48 PE13_PF_UART1_RXD,
49 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS,
51 /* UART4 */
52 PB26_AF_UART4_RTS,
53 PB28_AF_UART4_TXD,
54 PB29_AF_UART4_CTS,
55 PB31_AF_UART4_RXD,
56 /* FEC */
57 PD0_AIN_FEC_TXD0,
58 PD1_AIN_FEC_TXD1,
59 PD2_AIN_FEC_TXD2,
60 PD3_AIN_FEC_TXD3,
61 PD4_AOUT_FEC_RX_ER,
62 PD5_AOUT_FEC_RXD1,
63 PD6_AOUT_FEC_RXD2,
64 PD7_AOUT_FEC_RXD3,
65 PD8_AF_FEC_MDIO,
66 PD9_AIN_FEC_MDC,
67 PD10_AOUT_FEC_CRS,
68 PD11_AOUT_FEC_TX_CLK,
69 PD12_AOUT_FEC_RXD0,
70 PD13_AOUT_FEC_RX_DV,
71 PD14_AOUT_FEC_RX_CLK,
72 PD15_AOUT_FEC_COL,
73 PD16_AIN_FEC_TX_ER,
74 PF23_AIN_FEC_TX_EN,
75 /* I2C1 */
76 PD17_PF_I2C_DATA,
77 PD18_PF_I2C_CLK,
78 /* SDHC2 */
79 PB4_PF_SD2_D0,
80 PB5_PF_SD2_D1,
81 PB6_PF_SD2_D2,
82 PB7_PF_SD2_D3,
83 PB8_PF_SD2_CMD,
84 PB9_PF_SD2_CLK,
85#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
86 /* Quad UART's IRQ */
87 GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
88 GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
89 GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
90 GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
91#endif
92};
93
94static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
95 .width = 2,
96};
97
98static struct resource eukrea_cpuimx27_flash_resource = {
99 .start = 0xc0000000,
100 .end = 0xc3ffffff,
101 .flags = IORESOURCE_MEM,
102};
103
104static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
105 .name = "physmap-flash",
106 .id = 0,
107 .dev = {
108 .platform_data = &eukrea_cpuimx27_flash_data,
109 },
110 .num_resources = 1,
111 .resource = &eukrea_cpuimx27_flash_resource,
112};
113
114static struct imxuart_platform_data uart_pdata[] = {
115 {
116 .flags = IMXUART_HAVE_RTSCTS,
117 }, {
118 .flags = IMXUART_HAVE_RTSCTS,
119 },
120};
121
122static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
123 .width = 1,
124 .hw_ecc = 1,
125};
126
127static struct platform_device *platform_devices[] __initdata = {
128 &eukrea_cpuimx27_nor_mtd_device,
129 &mxc_fec_device,
130};
131
132static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
133 .bitrate = 100000,
134};
135
136static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
137 {
138 I2C_BOARD_INFO("pcf8563", 0x51),
139 },
140};
141
142#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
143static struct plat_serial8250_port serial_platform_data[] = {
144 {
145 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),
146 .irq = IRQ_GPIOB(23),
147 .uartclk = 14745600,
148 .regshift = 1,
149 .iotype = UPIO_MEM,
150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
151 }, {
152 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),
153 .irq = IRQ_GPIOB(22),
154 .uartclk = 14745600,
155 .regshift = 1,
156 .iotype = UPIO_MEM,
157 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
158 }, {
159 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),
160 .irq = IRQ_GPIOB(27),
161 .uartclk = 14745600,
162 .regshift = 1,
163 .iotype = UPIO_MEM,
164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
165 }, {
166 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),
167 .irq = IRQ_GPIOB(30),
168 .uartclk = 14745600,
169 .regshift = 1,
170 .iotype = UPIO_MEM,
171 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
172 }, {
173 }
174};
175
176static struct platform_device serial_device = {
177 .name = "serial8250",
178 .id = 0,
179 .dev = {
180 .platform_data = serial_platform_data,
181 },
182};
183#endif
184
185static void __init eukrea_cpuimx27_init(void)
186{
187 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
188 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
189
190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
191
192 mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
193
194 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
195 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
196
197 mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
198
199 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
200
201#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
202 /* SDHC2 can be used for Wifi */
203 mxc_register_device(&mxc_sdhc_device1, NULL);
204 /* in which case UART4 is also used for Bluetooth */
205 mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
206#endif
207
208#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
209 platform_device_register(&serial_device);
210#endif
211
212#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
213 eukrea_mbimx27_baseboard_init();
214#endif
215}
216
217static void __init eukrea_cpuimx27_timer_init(void)
218{
219 mx27_clocks_init(26000000);
220}
221
222static struct sys_timer eukrea_cpuimx27_timer = {
223 .init = eukrea_cpuimx27_timer_init,
224};
225
226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
227 .phys_io = AIPI_BASE_ADDR,
228 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
229 .boot_params = PHYS_OFFSET + 0x100,
230 .map_io = mx27_map_io,
231 .init_irq = mx27_init_irq,
232 .init_machine = eukrea_cpuimx27_init,
233 .timer = &eukrea_cpuimx27_timer,
234MACHINE_END
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
new file mode 100644
index 000000000000..7382b6d27ee1
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -0,0 +1,249 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h>
27
28#include <asm/mach/arch.h>
29
30#include <mach/common.h>
31#include <mach/iomux.h>
32#include <mach/imxfb.h>
33#include <mach/hardware.h>
34#include <mach/mmc.h>
35#include <mach/imx-uart.h>
36
37#include "devices.h"
38
39static int eukrea_mbimx27_pins[] = {
40 /* UART2 */
41 PE3_PF_UART2_CTS,
42 PE4_PF_UART2_RTS,
43 PE6_PF_UART2_TXD,
44 PE7_PF_UART2_RXD,
45 /* UART3 */
46 PE8_PF_UART3_TXD,
47 PE9_PF_UART3_RXD,
48 PE10_PF_UART3_CTS,
49 PE11_PF_UART3_RTS,
50 /* UART4 */
51 PB26_AF_UART4_RTS,
52 PB28_AF_UART4_TXD,
53 PB29_AF_UART4_CTS,
54 PB31_AF_UART4_RXD,
55 /* SDHC1*/
56 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1,
58 PE20_PF_SD1_D2,
59 PE21_PF_SD1_D3,
60 PE22_PF_SD1_CMD,
61 PE23_PF_SD1_CLK,
62 /* display */
63 PA5_PF_LSCLK,
64 PA6_PF_LD0,
65 PA7_PF_LD1,
66 PA8_PF_LD2,
67 PA9_PF_LD3,
68 PA10_PF_LD4,
69 PA11_PF_LD5,
70 PA12_PF_LD6,
71 PA13_PF_LD7,
72 PA14_PF_LD8,
73 PA15_PF_LD9,
74 PA16_PF_LD10,
75 PA17_PF_LD11,
76 PA18_PF_LD12,
77 PA19_PF_LD13,
78 PA20_PF_LD14,
79 PA21_PF_LD15,
80 PA22_PF_LD16,
81 PA23_PF_LD17,
82 PA28_PF_HSYNC,
83 PA29_PF_VSYNC,
84 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD,
86 /* SPI1 */
87 PD28_PF_CSPI1_SS0,
88 PD29_PF_CSPI1_SCLK,
89 PD30_PF_CSPI1_MISO,
90 PD31_PF_CSPI1_MOSI,
91};
92
93static struct gpio_led gpio_leds[] = {
94 {
95 .name = "led1",
96 .default_trigger = "heartbeat",
97 .active_low = 1,
98 .gpio = GPIO_PORTF | 16,
99 },
100 {
101 .name = "led2",
102 .default_trigger = "none",
103 .active_low = 1,
104 .gpio = GPIO_PORTF | 19,
105 },
106 {
107 .name = "backlight",
108 .default_trigger = "backlight",
109 .active_low = 0,
110 .gpio = GPIO_PORTE | 5,
111 },
112};
113
114static struct gpio_led_platform_data gpio_led_info = {
115 .leds = gpio_leds,
116 .num_leds = ARRAY_SIZE(gpio_leds),
117};
118
119static struct platform_device leds_gpio = {
120 .name = "leds-gpio",
121 .id = -1,
122 .dev = {
123 .platform_data = &gpio_led_info,
124 },
125};
126
127static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
128 {
129 .mode = {
130 .name = "CMO-QGVA",
131 .refresh = 60,
132 .xres = 320,
133 .yres = 240,
134 .pixclock = 156000,
135 .hsync_len = 30,
136 .left_margin = 38,
137 .right_margin = 20,
138 .vsync_len = 3,
139 .upper_margin = 15,
140 .lower_margin = 4,
141 },
142 .pcr = 0xFAD08B80,
143 .bpp = 16,
144 },
145};
146
147static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
148 .mode = eukrea_mbimx27_modes,
149 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
150
151 .pwmr = 0x00A903FF,
152 .lscr1 = 0x00120300,
153 .dmacr = 0x00040060,
154};
155
156static struct imxuart_platform_data uart_pdata[] = {
157 {
158 .flags = IMXUART_HAVE_RTSCTS,
159 },
160 {
161 .flags = IMXUART_HAVE_RTSCTS,
162 },
163};
164
165#if defined(CONFIG_TOUCHSCREEN_ADS7846)
166 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
167
168#define ADS7846_PENDOWN (GPIO_PORTD | 25)
169
170static void ads7846_dev_init(void)
171{
172 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
173 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
174 return;
175 }
176
177 gpio_direction_input(ADS7846_PENDOWN);
178}
179
180static int ads7846_get_pendown_state(void)
181{
182 return !gpio_get_value(ADS7846_PENDOWN);
183}
184
185static struct ads7846_platform_data ads7846_config __initdata = {
186 .get_pendown_state = ads7846_get_pendown_state,
187 .keep_vref_on = 1,
188};
189
190static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
191 [0] = {
192 .modalias = "ads7846",
193 .bus_num = 0,
194 .chip_select = 0,
195 .max_speed_hz = 1500000,
196 .irq = IRQ_GPIOD(25),
197 .platform_data = &ads7846_config,
198 .mode = SPI_MODE_2,
199 },
200};
201
202static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
203
204static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
205 .chipselect = eukrea_mbimx27_spi_cs,
206 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
207};
208#endif
209
210static struct platform_device *platform_devices[] __initdata = {
211 &leds_gpio,
212};
213
214/*
215 * system init for baseboard usage. Will be called by cpuimx27 init.
216 *
217 * Add platform devices present on this baseboard and init
218 * them from CPU side as far as required to use them later on
219 */
220void __init eukrea_mbimx27_baseboard_init(void)
221{
222 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
223 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
224
225 mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
226 mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
227
228 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
229 mxc_register_device(&mxc_sdhc_device0, NULL);
230
231#if defined(CONFIG_TOUCHSCREEN_ADS7846)
232 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
233 /* SPI and ADS7846 Touchscreen controler init */
234 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
235 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
236 mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
237 spi_register_board_info(eukrea_mbimx27_spi_board_info,
238 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
239 ads7846_dev_init();
240#endif
241
242 /* Leds configuration */
243 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
244 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
245 /* Backlight */
246 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
247
248 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
249}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index 169372f69d8f..ae8f759134d1 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
72void __init mx21_map_io(void) 72void __init mx21_map_io(void)
73{ 73{
74 mxc_set_cpu_type(MXC_CPU_MX21); 74 mxc_set_cpu_type(MXC_CPU_MX21);
75 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
75 76
76 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 77 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
77} 78}
@@ -79,7 +80,18 @@ void __init mx21_map_io(void)
79void __init mx27_map_io(void) 80void __init mx27_map_io(void)
80{ 81{
81 mxc_set_cpu_type(MXC_CPU_MX27); 82 mxc_set_cpu_type(MXC_CPU_MX27);
83 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
82 84
83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 85 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
84} 86}
85 87
88void __init mx27_init_irq(void)
89{
90 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
91}
92
93void __init mx21_init_irq(void)
94{
95 mx27_init_irq();
96}
97
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
index a5ee461cb405..cf5f77cbc2f1 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -164,25 +164,33 @@ static void mx21ads_fb_exit(struct platform_device *pdev)
164 * Connected is a portrait Sharp-QVGA display 164 * Connected is a portrait Sharp-QVGA display
165 * of type: LQ035Q7DB02 165 * of type: LQ035Q7DB02
166 */ 166 */
167static struct imx_fb_platform_data mx21ads_fb_data = { 167static struct imx_fb_videomode mx21ads_modes[] = {
168 .pixclock = 188679, /* in ps */ 168 {
169 .xres = 240, 169 .mode = {
170 .yres = 320, 170 .name = "Sharp-LQ035Q7",
171 171 .refresh = 60,
172 .bpp = 16, 172 .xres = 240,
173 .hsync_len = 2, 173 .yres = 320,
174 .left_margin = 6, 174 .pixclock = 188679, /* in ps (5.3MHz) */
175 .right_margin = 16, 175 .hsync_len = 2,
176 .left_margin = 6,
177 .right_margin = 16,
178 .vsync_len = 1,
179 .upper_margin = 8,
180 .lower_margin = 10,
181 },
182 .pcr = 0xfb108bc7,
183 .bpp = 16,
184 },
185};
176 186
177 .vsync_len = 1, 187static struct imx_fb_platform_data mx21ads_fb_data = {
178 .upper_margin = 8, 188 .mode = mx21ads_modes,
179 .lower_margin = 10, 189 .num_modes = ARRAY_SIZE(mx21ads_modes),
180 .fixed_screen_cpu = 0,
181 190
182 .pcr = 0xFB108BC7, 191 .pwmr = 0x00a903ff,
183 .pwmr = 0x00A901ff, 192 .lscr1 = 0x00120300,
184 .lscr1 = 0x00120300, 193 .dmacr = 0x00020008,
185 .dmacr = 0x00020008,
186 194
187 .init = mx21ads_fb_init, 195 .init = mx21ads_fb_init,
188 .exit = mx21ads_fb_exit, 196 .exit = mx21ads_fb_exit,
@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
280 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
281 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = PHYS_OFFSET + 0x100,
282 .map_io = mx21ads_map_io, 290 .map_io = mx21ads_map_io,
283 .init_irq = mxc_init_irq, 291 .init_irq = mx21_init_irq,
284 .init_machine = mx21ads_board_init, 292 .init_machine = mx21ads_board_init,
285 .timer = &mx21ads_timer, 293 .timer = &mx21ads_timer,
286MACHINE_END 294MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 02daddac6995..83e412b713e6 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -183,20 +183,29 @@ void lcd_power(int on)
183 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); 183 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
184} 184}
185 185
186static struct imx_fb_platform_data mx27ads_fb_data = { 186static struct imx_fb_videomode mx27ads_modes[] = {
187 .pixclock = 188679, 187 {
188 .xres = 240, 188 .mode = {
189 .yres = 320, 189 .name = "Sharp-LQ035Q7",
190 190 .refresh = 60,
191 .bpp = 16, 191 .xres = 240,
192 .hsync_len = 1, 192 .yres = 320,
193 .left_margin = 9, 193 .pixclock = 188679, /* in ps (5.3MHz) */
194 .right_margin = 16, 194 .hsync_len = 1,
195 .left_margin = 9,
196 .right_margin = 16,
197 .vsync_len = 1,
198 .upper_margin = 7,
199 .lower_margin = 9,
200 },
201 .bpp = 16,
202 .pcr = 0xFB008BC0,
203 },
204};
195 205
196 .vsync_len = 1, 206static struct imx_fb_platform_data mx27ads_fb_data = {
197 .upper_margin = 7, 207 .mode = mx27ads_modes,
198 .lower_margin = 9, 208 .num_modes = ARRAY_SIZE(mx27ads_modes),
199 .fixed_screen_cpu = 0,
200 209
201 /* 210 /*
202 * - HSYNC active high 211 * - HSYNC active high
@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = {
207 * - data enable low active 216 * - data enable low active
208 * - enable sharp mode 217 * - enable sharp mode
209 */ 218 */
210 .pcr = 0xFB008BC0,
211 .pwmr = 0x00A903FF, 219 .pwmr = 0x00A903FF,
212 .lscr1 = 0x00120300, 220 .lscr1 = 0x00120300,
213 .dmacr = 0x00020010, 221 .dmacr = 0x00020010,
@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
330 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 338 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
331 .boot_params = PHYS_OFFSET + 0x100, 339 .boot_params = PHYS_OFFSET + 0x100,
332 .map_io = mx27ads_map_io, 340 .map_io = mx27ads_map_io,
333 .init_irq = mxc_init_irq, 341 .init_irq = mx27_init_irq,
334 .init_machine = mx27ads_board_init, 342 .init_machine = mx27ads_board_init,
335 .timer = &mx27ads_timer, 343 .timer = &mx27ads_timer,
336MACHINE_END 344MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
index 3ae11cb8c04b..82ea227ea0cf 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mxc_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27lite_init, 93 .init_machine = mx27lite_init,
94 .timer = &mx27lite_timer, 94 .timer = &mx27lite_timer,
95MACHINE_END 95MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
index 1d9238c7a6c3..6761d1b79e43 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mxc_init_irq, 92 .init_irq = mx27_init_irq,
93 .init_machine = mx27pdk_init, 93 .init_machine = mx27pdk_init,
94 .timer = &mx27pdk_timer, 94 .timer = &mx27pdk_timer,
95MACHINE_END 95MACHINE_END
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
new file mode 100644
index 000000000000..fe5b165b88cc
--- /dev/null
+++ b/arch/arm/mach-mx2/pca100.c
@@ -0,0 +1,244 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/i2c.h>
23#include <linux/i2c/at24.h>
24#include <linux/dma-mapping.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/eeprom.h>
27#include <linux/irq.h>
28#include <linux/gpio.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach-types.h>
32#include <mach/common.h>
33#include <mach/hardware.h>
34#include <mach/iomux.h>
35#include <mach/i2c.h>
36#include <asm/mach/time.h>
37#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
38#include <mach/spi.h>
39#endif
40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h>
42#include <mach/irqs.h>
43#include <mach/mmc.h>
44
45#include "devices.h"
46
47static int pca100_pins[] = {
48 /* UART1 */
49 PE12_PF_UART1_TXD,
50 PE13_PF_UART1_RXD,
51 PE14_PF_UART1_CTS,
52 PE15_PF_UART1_RTS,
53 /* SDHC */
54 PB4_PF_SD2_D0,
55 PB5_PF_SD2_D1,
56 PB6_PF_SD2_D2,
57 PB7_PF_SD2_D3,
58 PB8_PF_SD2_CMD,
59 PB9_PF_SD2_CLK,
60 /* FEC */
61 PD0_AIN_FEC_TXD0,
62 PD1_AIN_FEC_TXD1,
63 PD2_AIN_FEC_TXD2,
64 PD3_AIN_FEC_TXD3,
65 PD4_AOUT_FEC_RX_ER,
66 PD5_AOUT_FEC_RXD1,
67 PD6_AOUT_FEC_RXD2,
68 PD7_AOUT_FEC_RXD3,
69 PD8_AF_FEC_MDIO,
70 PD9_AIN_FEC_MDC,
71 PD10_AOUT_FEC_CRS,
72 PD11_AOUT_FEC_TX_CLK,
73 PD12_AOUT_FEC_RXD0,
74 PD13_AOUT_FEC_RX_DV,
75 PD14_AOUT_FEC_RX_CLK,
76 PD15_AOUT_FEC_COL,
77 PD16_AIN_FEC_TX_ER,
78 PF23_AIN_FEC_TX_EN,
79 /* SSI1 */
80 PC20_PF_SSI1_FS,
81 PC21_PF_SSI1_RXD,
82 PC22_PF_SSI1_TXD,
83 PC23_PF_SSI1_CLK,
84 /* onboard I2C */
85 PC5_PF_I2C2_SDA,
86 PC6_PF_I2C2_SCL,
87 /* external I2C */
88 PD17_PF_I2C_DATA,
89 PD18_PF_I2C_CLK,
90 /* SPI1 */
91 PD25_PF_CSPI1_RDY,
92 PD29_PF_CSPI1_SCLK,
93 PD30_PF_CSPI1_MISO,
94 PD31_PF_CSPI1_MOSI,
95};
96
97static struct imxuart_platform_data uart_pdata = {
98 .flags = IMXUART_HAVE_RTSCTS,
99};
100
101static struct mxc_nand_platform_data pca100_nand_board_info = {
102 .width = 1,
103 .hw_ecc = 1,
104};
105
106static struct platform_device *platform_devices[] __initdata = {
107 &mxc_w1_master_device,
108 &mxc_fec_device,
109};
110
111static struct imxi2c_platform_data pca100_i2c_1_data = {
112 .bitrate = 100000,
113};
114
115static struct at24_platform_data board_eeprom = {
116 .byte_len = 4096,
117 .page_size = 32,
118 .flags = AT24_FLAG_ADDR16,
119};
120
121static struct i2c_board_info pca100_i2c_devices[] = {
122 {
123 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
124 .platform_data = &board_eeprom,
125 }, {
126 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
127 .type = "pcf8563"
128 }, {
129 I2C_BOARD_INFO("lm75", 0x4a),
130 .type = "lm75"
131 }
132};
133
134#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
135static struct spi_eeprom at25320 = {
136 .name = "at25320an",
137 .byte_len = 4096,
138 .page_size = 32,
139 .flags = EE_ADDR2,
140};
141
142static struct spi_board_info pca100_spi_board_info[] __initdata = {
143 {
144 .modalias = "at25",
145 .max_speed_hz = 30000,
146 .bus_num = 0,
147 .chip_select = 1,
148 .platform_data = &at25320,
149 },
150};
151
152static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
153
154static struct spi_imx_master pca100_spi_0_data = {
155 .chipselect = pca100_spi_cs,
156 .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
157};
158#endif
159
160static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
161 void *data)
162{
163 int ret;
164
165 ret = request_irq(IRQ_GPIOC(29), detect_irq,
166 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
167 "imx-mmc-detect", data);
168 if (ret)
169 printk(KERN_ERR
170 "pca100: Failed to reuest irq for sd/mmc detection\n");
171
172 return ret;
173}
174
175static void pca100_sdhc2_exit(struct device *dev, void *data)
176{
177 free_irq(IRQ_GPIOC(29), data);
178}
179
180static struct imxmmc_platform_data sdhc_pdata = {
181 .init = pca100_sdhc2_init,
182 .exit = pca100_sdhc2_exit,
183};
184
185static void __init pca100_init(void)
186{
187 int ret;
188
189 ret = mxc_gpio_setup_multiple_pins(pca100_pins,
190 ARRAY_SIZE(pca100_pins), "PCA100");
191 if (ret)
192 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
193
194 mxc_register_device(&mxc_uart_device0, &uart_pdata);
195
196 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
197 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
198
199 mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
200
201 /* only the i2c master 1 is used on this CPU card */
202 i2c_register_board_info(1, pca100_i2c_devices,
203 ARRAY_SIZE(pca100_i2c_devices));
204
205 mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
206
207 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
208 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
209
210 /* GPIO0_IRQ */
211 mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
212 /* GPIO1_IRQ */
213 mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
214 /* GPIO2_IRQ */
215 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
216
217#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
218 spi_register_board_info(pca100_spi_board_info,
219 ARRAY_SIZE(pca100_spi_board_info));
220 mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
221#endif
222
223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
224}
225
226static void __init pca100_timer_init(void)
227{
228 mx27_clocks_init(26000000);
229}
230
231static struct sys_timer pca100_timer = {
232 .init = pca100_timer_init,
233};
234
235MACHINE_START(PCA100, "phyCARD-i.MX27")
236 .phys_io = AIPI_BASE_ADDR,
237 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
238 .boot_params = PHYS_OFFSET + 0x100,
239 .map_io = mx27_map_io,
240 .init_irq = mxc_init_irq,
241 .init_machine = pca100_init,
242 .timer = &pca100_timer,
243MACHINE_END
244
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index a4628d004343..ee65dda584cf 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = {
186}; 186};
187 187
188static struct i2c_board_info pcm038_i2c_devices[] = { 188static struct i2c_board_info pcm038_i2c_devices[] = {
189 [0] = { 189 {
190 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ 190 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
191 .platform_data = &board_eeprom, 191 .platform_data = &board_eeprom,
192 }, 192 }, {
193 [1] = { 193 I2C_BOARD_INFO("pcf8563", 0x51),
194 I2C_BOARD_INFO("rtc-pcf8563", 0x51), 194 }, {
195 .type = "pcf8563"
196 },
197 [2] = {
198 I2C_BOARD_INFO("lm75", 0x4a), 195 I2C_BOARD_INFO("lm75", 0x4a),
199 .type = "lm75"
200 } 196 }
201}; 197};
202 198
@@ -220,6 +216,9 @@ static void __init pcm038_init(void)
220 216
221 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); 217 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
222 218
219 /* PE18 for user-LED D40 */
220 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
221
223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 222 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
224 223
225#ifdef CONFIG_MACH_PCM970_BASEBOARD 224#ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
241 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 240 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
242 .boot_params = PHYS_OFFSET + 0x100, 241 .boot_params = PHYS_OFFSET + 0x100,
243 .map_io = mx27_map_io, 242 .map_io = mx27_map_io,
244 .init_irq = mxc_init_irq, 243 .init_irq = mx27_init_irq,
245 .init_machine = pcm038_init, 244 .init_machine = pcm038_init,
246 .timer = &pcm038_timer, 245 .timer = &pcm038_timer,
247MACHINE_END 246MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 6a3acaf57dd4..c261f59b0b4c 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -19,6 +19,7 @@
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/can/platform/sja1000.h>
22 23
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24 25
@@ -125,40 +126,96 @@ static struct imxmmc_platform_data sdhc_pdata = {
125 .exit = pcm970_sdhc2_exit, 126 .exit = pcm970_sdhc2_exit,
126}; 127};
127 128
128/* 129static struct imx_fb_videomode pcm970_modes[] = {
129 * Connected is a portrait Sharp-QVGA display 130 {
130 * of type: LQ035Q7DH06 131 .mode = {
131 */ 132 .name = "Sharp-LQ035Q7",
132static struct imx_fb_platform_data pcm038_fb_data = { 133 .refresh = 60,
133 .pixclock = 188679, /* in ps (5.3MHz) */ 134 .xres = 240,
134 .xres = 240, 135 .yres = 320,
135 .yres = 320, 136 .pixclock = 188679, /* in ps (5.3MHz) */
136 137 .hsync_len = 7,
137 .bpp = 16, 138 .left_margin = 5,
138 .hsync_len = 7, 139 .right_margin = 16,
139 .left_margin = 5, 140 .vsync_len = 1,
140 .right_margin = 16, 141 .upper_margin = 7,
142 .lower_margin = 9,
143 },
144 /*
145 * - HSYNC active high
146 * - VSYNC active high
147 * - clk notenabled while idle
148 * - clock not inverted
149 * - data not inverted
150 * - data enable low active
151 * - enable sharp mode
152 */
153 .pcr = 0xF00080C0,
154 .bpp = 16,
155 }, {
156 .mode = {
157 .name = "TX090",
158 .refresh = 60,
159 .xres = 240,
160 .yres = 320,
161 .pixclock = 38255,
162 .left_margin = 144,
163 .right_margin = 0,
164 .upper_margin = 7,
165 .lower_margin = 40,
166 .hsync_len = 96,
167 .vsync_len = 1,
168 },
169 /*
170 * - HSYNC active low (1 << 22)
171 * - VSYNC active low (1 << 23)
172 * - clk notenabled while idle
173 * - clock not inverted
174 * - data not inverted
175 * - data enable low active
176 * - enable sharp mode
177 */
178 .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
179 .bpp = 32,
180 },
181};
141 182
142 .vsync_len = 1, 183static struct imx_fb_platform_data pcm038_fb_data = {
143 .upper_margin = 7, 184 .mode = pcm970_modes,
144 .lower_margin = 9, 185 .num_modes = ARRAY_SIZE(pcm970_modes),
145 .fixed_screen_cpu = 0,
146 186
147 /*
148 * - HSYNC active high
149 * - VSYNC active high
150 * - clk notenabled while idle
151 * - clock not inverted
152 * - data not inverted
153 * - data enable low active
154 * - enable sharp mode
155 */
156 .pcr = 0xFA0080C0,
157 .pwmr = 0x00A903FF, 187 .pwmr = 0x00A903FF,
158 .lscr1 = 0x00120300, 188 .lscr1 = 0x00120300,
159 .dmacr = 0x00020010, 189 .dmacr = 0x00020010,
160}; 190};
161 191
192static struct resource pcm970_sja1000_resources[] = {
193 {
194 .start = CS4_BASE_ADDR,
195 .end = CS4_BASE_ADDR + 0x100 - 1,
196 .flags = IORESOURCE_MEM,
197 }, {
198 .start = IRQ_GPIOE(19),
199 .end = IRQ_GPIOE(19),
200 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
201 },
202};
203
204struct sja1000_platform_data pcm970_sja1000_platform_data = {
205 .clock = 16000000 / 2,
206 .ocr = 0x40 | 0x18,
207 .cdr = 0x40,
208};
209
210static struct platform_device pcm970_sja1000 = {
211 .name = "sja1000_platform",
212 .dev = {
213 .platform_data = &pcm970_sja1000_platform_data,
214 },
215 .resource = pcm970_sja1000_resources,
216 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
217};
218
162/* 219/*
163 * system init for baseboard usage. Will be called by pcm038 init. 220 * system init for baseboard usage. Will be called by pcm038 init.
164 * 221 *
@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void)
172 229
173 mxc_register_device(&mxc_fb_device, &pcm038_fb_data); 230 mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
174 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 231 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
232 platform_device_register(&pcm970_sja1000);
175} 233}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 00:14:06 -0500