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-rw-r--r--arch/arm/mach-mx2/devices.c332
1 files changed, 225 insertions, 107 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0f1b3674327..50199aff0143 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,45 +40,87 @@
40#include "devices.h" 40#include "devices.h"
41 41
42/* 42/*
43 * Resource definition for the MXC IrDA 43 * SPI master controller
44 *
45 * - i.MX1: 2 channel (slighly different register setting)
46 * - i.MX21: 2 channel
47 * - i.MX27: 3 channel
44 */ 48 */
45static struct resource mxc_irda_resources[] = { 49static struct resource mxc_spi_resources0[] = {
46 [0] = { 50 {
47 .start = UART3_BASE_ADDR, 51 .start = CSPI1_BASE_ADDR,
48 .end = UART3_BASE_ADDR + SZ_4K - 1, 52 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
49 .flags = IORESOURCE_MEM, 53 .flags = IORESOURCE_MEM,
54 }, {
55 .start = MXC_INT_CSPI1,
56 .end = MXC_INT_CSPI1,
57 .flags = IORESOURCE_IRQ,
50 }, 58 },
51 [1] = { 59};
52 .start = MXC_INT_UART3, 60
53 .end = MXC_INT_UART3, 61static struct resource mxc_spi_resources1[] = {
54 .flags = IORESOURCE_IRQ, 62 {
63 .start = CSPI2_BASE_ADDR,
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
65 .flags = IORESOURCE_MEM,
66 }, {
67 .start = MXC_INT_CSPI2,
68 .end = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
55 }, 70 },
56}; 71};
57 72
58/* Platform Data for MXC IrDA */ 73#ifdef CONFIG_MACH_MX27
59struct platform_device mxc_irda_device = { 74static struct resource mxc_spi_resources2[] = {
60 .name = "mxc_irda", 75 {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
79 }, {
80 .start = MXC_INT_CSPI3,
81 .end = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
83 },
84};
85#endif
86
87struct platform_device mxc_spi_device0 = {
88 .name = "spi_imx",
61 .id = 0, 89 .id = 0,
62 .num_resources = ARRAY_SIZE(mxc_irda_resources), 90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
63 .resource = mxc_irda_resources, 91 .resource = mxc_spi_resources0,
92};
93
94struct platform_device mxc_spi_device1 = {
95 .name = "spi_imx",
96 .id = 1,
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
99};
100
101#ifdef CONFIG_MACH_MX27
102struct platform_device mxc_spi_device2 = {
103 .name = "spi_imx",
104 .id = 2,
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
64}; 107};
108#endif
65 109
66/* 110/*
67 * General Purpose Timer 111 * General Purpose Timer
68 * - i.MX1: 2 timer (slighly different register handling) 112 * - i.MX21: 3 timers
69 * - i.MX21: 3 timer 113 * - i.MX27: 6 timers
70 * - i.MX27: 6 timer
71 */ 114 */
72 115
73/* We use gpt0 as system timer, so do not add a device for this one */ 116/* We use gpt0 as system timer, so do not add a device for this one */
74 117
75static struct resource timer1_resources[] = { 118static struct resource timer1_resources[] = {
76 [0] = { 119 {
77 .start = GPT2_BASE_ADDR, 120 .start = GPT2_BASE_ADDR,
78 .end = GPT2_BASE_ADDR + 0x17, 121 .end = GPT2_BASE_ADDR + 0x17,
79 .flags = IORESOURCE_MEM 122 .flags = IORESOURCE_MEM,
80 }, 123 }, {
81 [1] = {
82 .start = MXC_INT_GPT2, 124 .start = MXC_INT_GPT2,
83 .end = MXC_INT_GPT2, 125 .end = MXC_INT_GPT2,
84 .flags = IORESOURCE_IRQ, 126 .flags = IORESOURCE_IRQ,
@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
89 .name = "imx_gpt", 131 .name = "imx_gpt",
90 .id = 1, 132 .id = 1,
91 .num_resources = ARRAY_SIZE(timer1_resources), 133 .num_resources = ARRAY_SIZE(timer1_resources),
92 .resource = timer1_resources 134 .resource = timer1_resources,
93}; 135};
94 136
95static struct resource timer2_resources[] = { 137static struct resource timer2_resources[] = {
96 [0] = { 138 {
97 .start = GPT3_BASE_ADDR, 139 .start = GPT3_BASE_ADDR,
98 .end = GPT3_BASE_ADDR + 0x17, 140 .end = GPT3_BASE_ADDR + 0x17,
99 .flags = IORESOURCE_MEM 141 .flags = IORESOURCE_MEM,
100 }, 142 }, {
101 [1] = {
102 .start = MXC_INT_GPT3, 143 .start = MXC_INT_GPT3,
103 .end = MXC_INT_GPT3, 144 .end = MXC_INT_GPT3,
104 .flags = IORESOURCE_IRQ, 145 .flags = IORESOURCE_IRQ,
@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
109 .name = "imx_gpt", 150 .name = "imx_gpt",
110 .id = 2, 151 .id = 2,
111 .num_resources = ARRAY_SIZE(timer2_resources), 152 .num_resources = ARRAY_SIZE(timer2_resources),
112 .resource = timer2_resources 153 .resource = timer2_resources,
113}; 154};
114 155
115#ifdef CONFIG_MACH_MX27 156#ifdef CONFIG_MACH_MX27
116static struct resource timer3_resources[] = { 157static struct resource timer3_resources[] = {
117 [0] = { 158 {
118 .start = GPT4_BASE_ADDR, 159 .start = GPT4_BASE_ADDR,
119 .end = GPT4_BASE_ADDR + 0x17, 160 .end = GPT4_BASE_ADDR + 0x17,
120 .flags = IORESOURCE_MEM 161 .flags = IORESOURCE_MEM,
121 }, 162 }, {
122 [1] = {
123 .start = MXC_INT_GPT4, 163 .start = MXC_INT_GPT4,
124 .end = MXC_INT_GPT4, 164 .end = MXC_INT_GPT4,
125 .flags = IORESOURCE_IRQ, 165 .flags = IORESOURCE_IRQ,
@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
130 .name = "imx_gpt", 170 .name = "imx_gpt",
131 .id = 3, 171 .id = 3,
132 .num_resources = ARRAY_SIZE(timer3_resources), 172 .num_resources = ARRAY_SIZE(timer3_resources),
133 .resource = timer3_resources 173 .resource = timer3_resources,
134}; 174};
135 175
136static struct resource timer4_resources[] = { 176static struct resource timer4_resources[] = {
137 [0] = { 177 {
138 .start = GPT5_BASE_ADDR, 178 .start = GPT5_BASE_ADDR,
139 .end = GPT5_BASE_ADDR + 0x17, 179 .end = GPT5_BASE_ADDR + 0x17,
140 .flags = IORESOURCE_MEM 180 .flags = IORESOURCE_MEM,
141 }, 181 }, {
142 [1] = {
143 .start = MXC_INT_GPT5, 182 .start = MXC_INT_GPT5,
144 .end = MXC_INT_GPT5, 183 .end = MXC_INT_GPT5,
145 .flags = IORESOURCE_IRQ, 184 .flags = IORESOURCE_IRQ,
@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
150 .name = "imx_gpt", 189 .name = "imx_gpt",
151 .id = 4, 190 .id = 4,
152 .num_resources = ARRAY_SIZE(timer4_resources), 191 .num_resources = ARRAY_SIZE(timer4_resources),
153 .resource = timer4_resources 192 .resource = timer4_resources,
154}; 193};
155 194
156static struct resource timer5_resources[] = { 195static struct resource timer5_resources[] = {
157 [0] = { 196 {
158 .start = GPT6_BASE_ADDR, 197 .start = GPT6_BASE_ADDR,
159 .end = GPT6_BASE_ADDR + 0x17, 198 .end = GPT6_BASE_ADDR + 0x17,
160 .flags = IORESOURCE_MEM 199 .flags = IORESOURCE_MEM,
161 }, 200 }, {
162 [1] = {
163 .start = MXC_INT_GPT6, 201 .start = MXC_INT_GPT6,
164 .end = MXC_INT_GPT6, 202 .end = MXC_INT_GPT6,
165 .flags = IORESOURCE_IRQ, 203 .flags = IORESOURCE_IRQ,
@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
170 .name = "imx_gpt", 208 .name = "imx_gpt",
171 .id = 5, 209 .id = 5,
172 .num_resources = ARRAY_SIZE(timer5_resources), 210 .num_resources = ARRAY_SIZE(timer5_resources),
173 .resource = timer5_resources 211 .resource = timer5_resources,
174}; 212};
175#endif 213#endif
176 214
@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
214 { 252 {
215 .start = NFC_BASE_ADDR, 253 .start = NFC_BASE_ADDR,
216 .end = NFC_BASE_ADDR + 0xfff, 254 .end = NFC_BASE_ADDR + 0xfff,
217 .flags = IORESOURCE_MEM 255 .flags = IORESOURCE_MEM,
218 }, { 256 }, {
219 .start = MXC_INT_NANDFC, 257 .start = MXC_INT_NANDFC,
220 .end = MXC_INT_NANDFC, 258 .end = MXC_INT_NANDFC,
221 .flags = IORESOURCE_IRQ 259 .flags = IORESOURCE_IRQ,
222 }, 260 },
223}; 261};
224 262
@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
240 .start = LCDC_BASE_ADDR, 278 .start = LCDC_BASE_ADDR,
241 .end = LCDC_BASE_ADDR + 0xFFF, 279 .end = LCDC_BASE_ADDR + 0xFFF,
242 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
243 }, 281 }, {
244 {
245 .start = MXC_INT_LCDC, 282 .start = MXC_INT_LCDC,
246 .end = MXC_INT_LCDC, 283 .end = MXC_INT_LCDC,
247 .flags = IORESOURCE_IRQ, 284 .flags = IORESOURCE_IRQ,
@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
264 { 301 {
265 .start = FEC_BASE_ADDR, 302 .start = FEC_BASE_ADDR,
266 .end = FEC_BASE_ADDR + 0xfff, 303 .end = FEC_BASE_ADDR + 0xfff,
267 .flags = IORESOURCE_MEM 304 .flags = IORESOURCE_MEM,
268 }, { 305 }, {
269 .start = MXC_INT_FEC, 306 .start = MXC_INT_FEC,
270 .end = MXC_INT_FEC, 307 .end = MXC_INT_FEC,
271 .flags = IORESOURCE_IRQ 308 .flags = IORESOURCE_IRQ,
272 }, 309 },
273}; 310};
274 311
@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
281#endif 318#endif
282 319
283static struct resource mxc_i2c_1_resources[] = { 320static struct resource mxc_i2c_1_resources[] = {
284 [0] = { 321 {
285 .start = I2C_BASE_ADDR, 322 .start = I2C_BASE_ADDR,
286 .end = I2C_BASE_ADDR + 0x0fff, 323 .end = I2C_BASE_ADDR + 0x0fff,
287 .flags = IORESOURCE_MEM 324 .flags = IORESOURCE_MEM,
288 }, 325 }, {
289 [1] = {
290 .start = MXC_INT_I2C, 326 .start = MXC_INT_I2C,
291 .end = MXC_INT_I2C, 327 .end = MXC_INT_I2C,
292 .flags = IORESOURCE_IRQ 328 .flags = IORESOURCE_IRQ,
293 } 329 }
294}; 330};
295 331
@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
297 .name = "imx-i2c", 333 .name = "imx-i2c",
298 .id = 0, 334 .id = 0,
299 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), 335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
300 .resource = mxc_i2c_1_resources 336 .resource = mxc_i2c_1_resources,
301}; 337};
302 338
303#ifdef CONFIG_MACH_MX27 339#ifdef CONFIG_MACH_MX27
304static struct resource mxc_i2c_2_resources[] = { 340static struct resource mxc_i2c_2_resources[] = {
305 [0] = { 341 {
306 .start = I2C2_BASE_ADDR, 342 .start = I2C2_BASE_ADDR,
307 .end = I2C2_BASE_ADDR + 0x0fff, 343 .end = I2C2_BASE_ADDR + 0x0fff,
308 .flags = IORESOURCE_MEM 344 .flags = IORESOURCE_MEM,
309 }, 345 }, {
310 [1] = {
311 .start = MXC_INT_I2C2, 346 .start = MXC_INT_I2C2,
312 .end = MXC_INT_I2C2, 347 .end = MXC_INT_I2C2,
313 .flags = IORESOURCE_IRQ 348 .flags = IORESOURCE_IRQ,
314 } 349 }
315}; 350};
316 351
@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
318 .name = "imx-i2c", 353 .name = "imx-i2c",
319 .id = 1, 354 .id = 1,
320 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), 355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
321 .resource = mxc_i2c_2_resources 356 .resource = mxc_i2c_2_resources,
322}; 357};
323#endif 358#endif
324 359
325static struct resource mxc_pwm_resources[] = { 360static struct resource mxc_pwm_resources[] = {
326 [0] = { 361 {
327 .start = PWM_BASE_ADDR, 362 .start = PWM_BASE_ADDR,
328 .end = PWM_BASE_ADDR + 0x0fff, 363 .end = PWM_BASE_ADDR + 0x0fff,
329 .flags = IORESOURCE_MEM 364 .flags = IORESOURCE_MEM,
330 }, 365 }, {
331 [1] = {
332 .start = MXC_INT_PWM, 366 .start = MXC_INT_PWM,
333 .end = MXC_INT_PWM, 367 .end = MXC_INT_PWM,
334 .flags = IORESOURCE_IRQ, 368 .flags = IORESOURCE_IRQ,
@@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = {
339 .name = "mxc_pwm", 373 .name = "mxc_pwm",
340 .id = 0, 374 .id = 0,
341 .num_resources = ARRAY_SIZE(mxc_pwm_resources), 375 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
342 .resource = mxc_pwm_resources 376 .resource = mxc_pwm_resources,
343}; 377};
344 378
345/* 379/*
346 * Resource definition for the MXC SDHC 380 * Resource definition for the MXC SDHC
347 */ 381 */
348static struct resource mxc_sdhc1_resources[] = { 382static struct resource mxc_sdhc1_resources[] = {
349 [0] = { 383 {
350 .start = SDHC1_BASE_ADDR, 384 .start = SDHC1_BASE_ADDR,
351 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 385 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
352 .flags = IORESOURCE_MEM, 386 .flags = IORESOURCE_MEM,
353 }, 387 }, {
354 [1] = { 388 .start = MXC_INT_SDHC1,
355 .start = MXC_INT_SDHC1, 389 .end = MXC_INT_SDHC1,
356 .end = MXC_INT_SDHC1, 390 .flags = IORESOURCE_IRQ,
357 .flags = IORESOURCE_IRQ, 391 }, {
358 }, 392 .start = DMA_REQ_SDHC1,
359 [2] = { 393 .end = DMA_REQ_SDHC1,
360 .start = DMA_REQ_SDHC1, 394 .flags = IORESOURCE_DMA,
361 .end = DMA_REQ_SDHC1, 395 },
362 .flags = IORESOURCE_DMA
363 },
364}; 396};
365 397
366static u64 mxc_sdhc1_dmamask = 0xffffffffUL; 398static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
@@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = {
377}; 409};
378 410
379static struct resource mxc_sdhc2_resources[] = { 411static struct resource mxc_sdhc2_resources[] = {
380 [0] = { 412 {
381 .start = SDHC2_BASE_ADDR, 413 .start = SDHC2_BASE_ADDR,
382 .end = SDHC2_BASE_ADDR + SZ_4K - 1, 414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
383 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
384 }, 416 }, {
385 [1] = { 417 .start = MXC_INT_SDHC2,
386 .start = MXC_INT_SDHC2, 418 .end = MXC_INT_SDHC2,
387 .end = MXC_INT_SDHC2, 419 .flags = IORESOURCE_IRQ,
388 .flags = IORESOURCE_IRQ, 420 }, {
389 }, 421 .start = DMA_REQ_SDHC2,
390 [2] = { 422 .end = DMA_REQ_SDHC2,
391 .start = DMA_REQ_SDHC2, 423 .flags = IORESOURCE_DMA,
392 .end = DMA_REQ_SDHC2, 424 },
393 .flags = IORESOURCE_DMA
394 },
395}; 425};
396 426
397static u64 mxc_sdhc2_dmamask = 0xffffffffUL; 427static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
407 .resource = mxc_sdhc2_resources, 437 .resource = mxc_sdhc2_resources,
408}; 438};
409 439
440#ifdef CONFIG_MACH_MX27
441static struct resource otg_resources[] = {
442 {
443 .start = OTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM,
446 }, {
447 .start = MXC_INT_USB3,
448 .end = MXC_INT_USB3,
449 .flags = IORESOURCE_IRQ,
450 },
451};
452
453static u64 otg_dmamask = 0xffffffffUL;
454
455/* OTG gadget device */
456struct platform_device mxc_otg_udc_device = {
457 .name = "fsl-usb2-udc",
458 .id = -1,
459 .dev = {
460 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL,
462 },
463 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources),
465};
466
467/* OTG host */
468struct platform_device mxc_otg_host = {
469 .name = "mxc-ehci",
470 .id = 0,
471 .dev = {
472 .coherent_dma_mask = 0xffffffff,
473 .dma_mask = &otg_dmamask,
474 },
475 .resource = otg_resources,
476 .num_resources = ARRAY_SIZE(otg_resources),
477};
478
479/* USB host 1 */
480
481static u64 usbh1_dmamask = 0xffffffffUL;
482
483static struct resource mxc_usbh1_resources[] = {
484 {
485 .start = OTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM,
488 }, {
489 .start = MXC_INT_USB1,
490 .end = MXC_INT_USB1,
491 .flags = IORESOURCE_IRQ,
492 },
493};
494
495struct platform_device mxc_usbh1 = {
496 .name = "mxc-ehci",
497 .id = 1,
498 .dev = {
499 .coherent_dma_mask = 0xffffffff,
500 .dma_mask = &usbh1_dmamask,
501 },
502 .resource = mxc_usbh1_resources,
503 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
504};
505
506/* USB host 2 */
507static u64 usbh2_dmamask = 0xffffffffUL;
508
509static struct resource mxc_usbh2_resources[] = {
510 {
511 .start = OTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM,
514 }, {
515 .start = MXC_INT_USB2,
516 .end = MXC_INT_USB2,
517 .flags = IORESOURCE_IRQ,
518 },
519};
520
521struct platform_device mxc_usbh2 = {
522 .name = "mxc-ehci",
523 .id = 2,
524 .dev = {
525 .coherent_dma_mask = 0xffffffff,
526 .dma_mask = &usbh2_dmamask,
527 },
528 .resource = mxc_usbh2_resources,
529 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
530};
531#endif
532
410/* GPIO port description */ 533/* GPIO port description */
411static struct mxc_gpio_port imx_gpio_ports[] = { 534static struct mxc_gpio_port imx_gpio_ports[] = {
412 [0] = { 535 {
413 .chip.label = "gpio-0", 536 .chip.label = "gpio-0",
414 .irq = MXC_INT_GPIO, 537 .irq = MXC_INT_GPIO,
415 .base = IO_ADDRESS(GPIO_BASE_ADDR), 538 .base = IO_ADDRESS(GPIO_BASE_ADDR),
416 .virtual_irq_start = MXC_GPIO_IRQ_START, 539 .virtual_irq_start = MXC_GPIO_IRQ_START,
417 }, 540 }, {
418 [1] = {
419 .chip.label = "gpio-1", 541 .chip.label = "gpio-1",
420 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), 542 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
421 .virtual_irq_start = MXC_GPIO_IRQ_START + 32, 543 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
422 }, 544 }, {
423 [2] = {
424 .chip.label = "gpio-2", 545 .chip.label = "gpio-2",
425 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), 546 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
426 .virtual_irq_start = MXC_GPIO_IRQ_START + 64, 547 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
427 }, 548 }, {
428 [3] = {
429 .chip.label = "gpio-3", 549 .chip.label = "gpio-3",
430 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), 550 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
431 .virtual_irq_start = MXC_GPIO_IRQ_START + 96, 551 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
432 }, 552 }, {
433 [4] = {
434 .chip.label = "gpio-4", 553 .chip.label = "gpio-4",
435 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), 554 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
436 .virtual_irq_start = MXC_GPIO_IRQ_START + 128, 555 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
437 }, 556 }, {
438 [5] = {
439 .chip.label = "gpio-5", 557 .chip.label = "gpio-5",
440 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), 558 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
441 .virtual_irq_start = MXC_GPIO_IRQ_START + 160, 559 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,