diff options
Diffstat (limited to 'arch/arm/mach-mx2/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx2/crm_regs.h | 273 |
1 files changed, 273 insertions, 0 deletions
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h new file mode 100644 index 000000000000..a40a9b950ce9 --- /dev/null +++ b/arch/arm/mach-mx2/crm_regs.h | |||
| @@ -0,0 +1,273 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__ | ||
| 21 | #define __ARCH_ARM_MACH_MX2_CRM_REGS_H__ | ||
| 22 | |||
| 23 | #include <asm/arch/hardware.h> | ||
| 24 | |||
| 25 | /* Register offsets */ | ||
| 26 | #define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) | ||
| 27 | #define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) | ||
| 28 | #define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) | ||
| 29 | #define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) | ||
| 30 | #define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) | ||
| 31 | #define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) | ||
| 32 | #define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) | ||
| 33 | #define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) | ||
| 34 | #define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) | ||
| 35 | #define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) | ||
| 36 | #define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) | ||
| 37 | #define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) | ||
| 38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | ||
| 39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | ||
| 40 | |||
| 41 | #define CCM_CSCR_USB_OFFSET 28 | ||
| 42 | #define CCM_CSCR_USB_MASK (0x7 << 28) | ||
| 43 | #define CCM_CSCR_SD_OFFSET 24 | ||
| 44 | #define CCM_CSCR_SD_MASK (0x3 << 24) | ||
| 45 | #define CCM_CSCR_SSI2 (1 << 23) | ||
| 46 | #define CCM_CSCR_SSI2_OFFSET 23 | ||
| 47 | #define CCM_CSCR_SSI1 (1 << 22) | ||
| 48 | #define CCM_CSCR_SSI1_OFFSET 22 | ||
| 49 | #define CCM_CSCR_VPU (1 << 21) | ||
| 50 | #define CCM_CSCR_VPU_OFFSET 21 | ||
| 51 | #define CCM_CSCR_MSHC (1 << 20) | ||
| 52 | #define CCM_CSCR_SPLLRES (1 << 19) | ||
| 53 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 54 | #define CCM_CSCR_SP (1 << 17) | ||
| 55 | #define CCM_CSCR_MCU (1 << 16) | ||
| 56 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | ||
| 57 | #define CCM_CSCR_ARM_SRC (1 << 15) | ||
| 58 | #define CCM_CSCR_ARM_OFFSET 12 | ||
| 59 | #define CCM_CSCR_ARM_MASK (0x3 << 12) | ||
| 60 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | ||
| 61 | #define CCM_CSCR_PRESC_OFFSET 13 | ||
| 62 | #define CCM_CSCR_PRESC_MASK (0x7 << 13) | ||
| 63 | #define CCM_CSCR_BCLK_OFFSET 9 | ||
| 64 | #define CCM_CSCR_BCLK_MASK (0xf << 9) | ||
| 65 | #define CCM_CSCR_IPDIV_OFFSET 8 | ||
| 66 | #define CCM_CSCR_IPDIV (1 << 8) | ||
| 67 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 68 | #define CCM_CSCR_AHB_OFFSET 8 | ||
| 69 | #define CCM_CSCR_AHB_MASK (0x3 << 8) | ||
| 70 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 71 | #define CCM_CSCR_OSC26MDIV (1 << 4) | ||
| 72 | #define CCM_CSCR_OSC26M (1 << 3) | ||
| 73 | #define CCM_CSCR_FPM (1 << 2) | ||
| 74 | #define CCM_CSCR_SPEN (1 << 1) | ||
| 75 | #define CCM_CSCR_MPEN 1 | ||
| 76 | |||
| 77 | #define CCM_MPCTL0_CPLM (1 << 31) | ||
| 78 | #define CCM_MPCTL0_PD_OFFSET 26 | ||
| 79 | #define CCM_MPCTL0_PD_MASK (0xf << 26) | ||
| 80 | #define CCM_MPCTL0_MFD_OFFSET 16 | ||
| 81 | #define CCM_MPCTL0_MFD_MASK (0x3ff << 16) | ||
| 82 | #define CCM_MPCTL0_MFI_OFFSET 10 | ||
| 83 | #define CCM_MPCTL0_MFI_MASK (0xf << 10) | ||
| 84 | #define CCM_MPCTL0_MFN_OFFSET 0 | ||
| 85 | #define CCM_MPCTL0_MFN_MASK 0x3ff | ||
| 86 | |||
| 87 | #define CCM_MPCTL1_LF (1 << 15) | ||
| 88 | #define CCM_MPCTL1_BRMO (1 << 6) | ||
| 89 | |||
| 90 | #define CCM_SPCTL0_CPLM (1 << 31) | ||
| 91 | #define CCM_SPCTL0_PD_OFFSET 26 | ||
| 92 | #define CCM_SPCTL0_PD_MASK (0xf << 26) | ||
| 93 | #define CCM_SPCTL0_MFD_OFFSET 16 | ||
| 94 | #define CCM_SPCTL0_MFD_MASK (0x3ff << 16) | ||
| 95 | #define CCM_SPCTL0_MFI_OFFSET 10 | ||
| 96 | #define CCM_SPCTL0_MFI_MASK (0xf << 10) | ||
| 97 | #define CCM_SPCTL0_MFN_OFFSET 0 | ||
| 98 | #define CCM_SPCTL0_MFN_MASK 0x3ff | ||
| 99 | |||
| 100 | #define CCM_SPCTL1_LF (1 << 15) | ||
| 101 | #define CCM_SPCTL1_BRMO (1 << 6) | ||
| 102 | |||
| 103 | #define CCM_OSC26MCTL_PEAK_OFFSET 16 | ||
| 104 | #define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) | ||
| 105 | #define CCM_OSC26MCTL_AGC_OFFSET 8 | ||
| 106 | #define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) | ||
| 107 | #define CCM_OSC26MCTL_ANATEST_OFFSET 0 | ||
| 108 | #define CCM_OSC26MCTL_ANATEST_MASK 0x3f | ||
| 109 | |||
| 110 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 | ||
| 111 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) | ||
| 112 | #define CCM_PCDR0_CLKO_EN 25 | ||
| 113 | #define CCM_PCDR0_CLKODIV_OFFSET 22 | ||
| 114 | #define CCM_PCDR0_CLKODIV_MASK (0x7 << 22) | ||
| 115 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 | ||
| 116 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) | ||
| 117 | /*The difinition for i.MX27 TO2*/ | ||
| 118 | #define CCM_PCDR0_VPUDIV2_OFFSET 10 | ||
| 119 | #define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10) | ||
| 120 | #define CCM_PCDR0_NFCDIV2_OFFSET 6 | ||
| 121 | #define CCM_PCDR0_NFCDIV2_MASK (0xf << 6) | ||
| 122 | #define CCM_PCDR0_MSHCDIV2_MASK 0x3f | ||
| 123 | /*The difinition for i.MX27 TO2*/ | ||
| 124 | #define CCM_PCDR0_NFCDIV_OFFSET 12 | ||
| 125 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) | ||
| 126 | #define CCM_PCDR0_VPUDIV_OFFSET 8 | ||
| 127 | #define CCM_PCDR0_VPUDIV_MASK (0xf << 8) | ||
| 128 | #define CCM_PCDR0_MSHCDIV_OFFSET 0 | ||
| 129 | #define CCM_PCDR0_MSHCDIV_MASK 0x1f | ||
| 130 | |||
| 131 | #define CCM_PCDR1_PERDIV4_OFFSET 24 | ||
| 132 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) | ||
| 133 | #define CCM_PCDR1_PERDIV3_OFFSET 16 | ||
| 134 | #define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) | ||
| 135 | #define CCM_PCDR1_PERDIV2_OFFSET 8 | ||
| 136 | #define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) | ||
| 137 | #define CCM_PCDR1_PERDIV1_OFFSET 0 | ||
| 138 | #define CCM_PCDR1_PERDIV1_MASK 0x3f | ||
| 139 | |||
| 140 | #define CCM_PCCR0_CSPI1_OFFSET 31 | ||
| 141 | #define CCM_PCCR0_CSPI1_MASK (1 << 31) | ||
| 142 | #define CCM_PCCR0_CSPI2_OFFSET 30 | ||
| 143 | #define CCM_PCCR0_CSPI2_MASK (1 << 30) | ||
| 144 | #define CCM_PCCR0_CSPI3_OFFSET 29 | ||
| 145 | #define CCM_PCCR0_CSPI3_MASK (1 << 29) | ||
| 146 | #define CCM_PCCR0_DMA_OFFSET 28 | ||
| 147 | #define CCM_PCCR0_DMA_MASK (1 << 28) | ||
| 148 | #define CCM_PCCR0_EMMA_OFFSET 27 | ||
| 149 | #define CCM_PCCR0_EMMA_MASK (1 << 27) | ||
| 150 | #define CCM_PCCR0_FEC_OFFSET 26 | ||
| 151 | #define CCM_PCCR0_FEC_MASK (1 << 26) | ||
| 152 | #define CCM_PCCR0_GPIO_OFFSET 25 | ||
| 153 | #define CCM_PCCR0_GPIO_MASK (1 << 25) | ||
| 154 | #define CCM_PCCR0_GPT1_OFFSET 24 | ||
| 155 | #define CCM_PCCR0_GPT1_MASK (1 << 24) | ||
| 156 | #define CCM_PCCR0_GPT2_OFFSET 23 | ||
| 157 | #define CCM_PCCR0_GPT2_MASK (1 << 23) | ||
| 158 | #define CCM_PCCR0_GPT3_OFFSET 22 | ||
| 159 | #define CCM_PCCR0_GPT3_MASK (1 << 22) | ||
| 160 | #define CCM_PCCR0_GPT4_OFFSET 21 | ||
| 161 | #define CCM_PCCR0_GPT4_MASK (1 << 21) | ||
| 162 | #define CCM_PCCR0_GPT5_OFFSET 20 | ||
| 163 | #define CCM_PCCR0_GPT5_MASK (1 << 20) | ||
| 164 | #define CCM_PCCR0_GPT6_OFFSET 19 | ||
| 165 | #define CCM_PCCR0_GPT6_MASK (1 << 19) | ||
| 166 | #define CCM_PCCR0_I2C1_OFFSET 18 | ||
| 167 | #define CCM_PCCR0_I2C1_MASK (1 << 18) | ||
| 168 | #define CCM_PCCR0_I2C2_OFFSET 17 | ||
| 169 | #define CCM_PCCR0_I2C2_MASK (1 << 17) | ||
| 170 | #define CCM_PCCR0_IIM_OFFSET 16 | ||
| 171 | #define CCM_PCCR0_IIM_MASK (1 << 16) | ||
| 172 | #define CCM_PCCR0_KPP_OFFSET 15 | ||
| 173 | #define CCM_PCCR0_KPP_MASK (1 << 15) | ||
| 174 | #define CCM_PCCR0_LCDC_OFFSET 14 | ||
| 175 | #define CCM_PCCR0_LCDC_MASK (1 << 14) | ||
| 176 | #define CCM_PCCR0_MSHC_OFFSET 13 | ||
| 177 | #define CCM_PCCR0_MSHC_MASK (1 << 13) | ||
| 178 | #define CCM_PCCR0_OWIRE_OFFSET 12 | ||
| 179 | #define CCM_PCCR0_OWIRE_MASK (1 << 12) | ||
| 180 | #define CCM_PCCR0_PWM_OFFSET 11 | ||
| 181 | #define CCM_PCCR0_PWM_MASK (1 << 11) | ||
| 182 | #define CCM_PCCR0_RTC_OFFSET 9 | ||
| 183 | #define CCM_PCCR0_RTC_MASK (1 << 9) | ||
| 184 | #define CCM_PCCR0_RTIC_OFFSET 8 | ||
| 185 | #define CCM_PCCR0_RTIC_MASK (1 << 8) | ||
| 186 | #define CCM_PCCR0_SAHARA_OFFSET 7 | ||
| 187 | #define CCM_PCCR0_SAHARA_MASK (1 << 7) | ||
| 188 | #define CCM_PCCR0_SCC_OFFSET 6 | ||
| 189 | #define CCM_PCCR0_SCC_MASK (1 << 6) | ||
| 190 | #define CCM_PCCR0_SDHC1_OFFSET 5 | ||
| 191 | #define CCM_PCCR0_SDHC1_MASK (1 << 5) | ||
| 192 | #define CCM_PCCR0_SDHC2_OFFSET 4 | ||
| 193 | #define CCM_PCCR0_SDHC2_MASK (1 << 4) | ||
| 194 | #define CCM_PCCR0_SDHC3_OFFSET 3 | ||
| 195 | #define CCM_PCCR0_SDHC3_MASK (1 << 3) | ||
| 196 | #define CCM_PCCR0_SLCDC_OFFSET 2 | ||
| 197 | #define CCM_PCCR0_SLCDC_MASK (1 << 2) | ||
| 198 | #define CCM_PCCR0_SSI1_IPG_OFFSET 1 | ||
| 199 | #define CCM_PCCR0_SSI1_IPG_MASK (1 << 1) | ||
| 200 | #define CCM_PCCR0_SSI2_IPG_OFFSET 0 | ||
| 201 | #define CCM_PCCR0_SSI2_IPG_MASK (1 << 0) | ||
| 202 | |||
| 203 | #define CCM_PCCR1_UART1_OFFSET 31 | ||
| 204 | #define CCM_PCCR1_UART1_MASK (1 << 31) | ||
| 205 | #define CCM_PCCR1_UART2_OFFSET 30 | ||
| 206 | #define CCM_PCCR1_UART2_MASK (1 << 30) | ||
| 207 | #define CCM_PCCR1_UART3_OFFSET 29 | ||
| 208 | #define CCM_PCCR1_UART3_MASK (1 << 29) | ||
| 209 | #define CCM_PCCR1_UART4_OFFSET 28 | ||
| 210 | #define CCM_PCCR1_UART4_MASK (1 << 28) | ||
| 211 | #define CCM_PCCR1_UART5_OFFSET 27 | ||
| 212 | #define CCM_PCCR1_UART5_MASK (1 << 27) | ||
| 213 | #define CCM_PCCR1_UART6_OFFSET 26 | ||
| 214 | #define CCM_PCCR1_UART6_MASK (1 << 26) | ||
| 215 | #define CCM_PCCR1_USBOTG_OFFSET 25 | ||
| 216 | #define CCM_PCCR1_USBOTG_MASK (1 << 25) | ||
| 217 | #define CCM_PCCR1_WDT_OFFSET 24 | ||
| 218 | #define CCM_PCCR1_WDT_MASK (1 << 24) | ||
| 219 | #define CCM_PCCR1_HCLK_ATA_OFFSET 23 | ||
| 220 | #define CCM_PCCR1_HCLK_ATA_MASK (1 << 23) | ||
| 221 | #define CCM_PCCR1_HCLK_BROM_OFFSET 22 | ||
| 222 | #define CCM_PCCR1_HCLK_BROM_MASK (1 << 22) | ||
| 223 | #define CCM_PCCR1_HCLK_CSI_OFFSET 21 | ||
| 224 | #define CCM_PCCR1_HCLK_CSI_MASK (1 << 21) | ||
| 225 | #define CCM_PCCR1_HCLK_DMA_OFFSET 20 | ||
| 226 | #define CCM_PCCR1_HCLK_DMA_MASK (1 << 20) | ||
| 227 | #define CCM_PCCR1_HCLK_EMI_OFFSET 19 | ||
| 228 | #define CCM_PCCR1_HCLK_EMI_MASK (1 << 19) | ||
| 229 | #define CCM_PCCR1_HCLK_EMMA_OFFSET 18 | ||
| 230 | #define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18) | ||
| 231 | #define CCM_PCCR1_HCLK_FEC_OFFSET 17 | ||
| 232 | #define CCM_PCCR1_HCLK_FEC_MASK (1 << 17) | ||
| 233 | #define CCM_PCCR1_HCLK_VPU_OFFSET 16 | ||
| 234 | #define CCM_PCCR1_HCLK_VPU_MASK (1 << 16) | ||
| 235 | #define CCM_PCCR1_HCLK_LCDC_OFFSET 15 | ||
| 236 | #define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15) | ||
| 237 | #define CCM_PCCR1_HCLK_RTIC_OFFSET 14 | ||
| 238 | #define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14) | ||
| 239 | #define CCM_PCCR1_HCLK_SAHARA_OFFSET 13 | ||
| 240 | #define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13) | ||
| 241 | #define CCM_PCCR1_HCLK_SLCDC_OFFSET 12 | ||
| 242 | #define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12) | ||
| 243 | #define CCM_PCCR1_HCLK_USBOTG_OFFSET 11 | ||
| 244 | #define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11) | ||
| 245 | #define CCM_PCCR1_PERCLK1_OFFSET 10 | ||
| 246 | #define CCM_PCCR1_PERCLK1_MASK (1 << 10) | ||
| 247 | #define CCM_PCCR1_PERCLK2_OFFSET 9 | ||
| 248 | #define CCM_PCCR1_PERCLK2_MASK (1 << 9) | ||
| 249 | #define CCM_PCCR1_PERCLK3_OFFSET 8 | ||
| 250 | #define CCM_PCCR1_PERCLK3_MASK (1 << 8) | ||
| 251 | #define CCM_PCCR1_PERCLK4_OFFSET 7 | ||
| 252 | #define CCM_PCCR1_PERCLK4_MASK (1 << 7) | ||
| 253 | #define CCM_PCCR1_VPU_BAUD_OFFSET 6 | ||
| 254 | #define CCM_PCCR1_VPU_BAUD_MASK (1 << 6) | ||
| 255 | #define CCM_PCCR1_SSI1_BAUD_OFFSET 5 | ||
| 256 | #define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5) | ||
| 257 | #define CCM_PCCR1_SSI2_BAUD_OFFSET 4 | ||
| 258 | #define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4) | ||
| 259 | #define CCM_PCCR1_NFC_BAUD_OFFSET 3 | ||
| 260 | #define CCM_PCCR1_NFC_BAUD_MASK (1 << 3) | ||
| 261 | #define CCM_PCCR1_MSHC_BAUD_OFFSET 2 | ||
| 262 | #define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2) | ||
| 263 | |||
| 264 | #define CCM_CCSR_32KSR (1 << 15) | ||
| 265 | #define CCM_CCSR_CLKMODE1 (1 << 9) | ||
| 266 | #define CCM_CCSR_CLKMODE0 (1 << 8) | ||
| 267 | #define CCM_CCSR_CLKOSEL_OFFSET 0 | ||
| 268 | #define CCM_CCSR_CLKOSEL_MASK 0x1f | ||
| 269 | |||
| 270 | #define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ | ||
| 271 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ | ||
| 272 | |||
| 273 | #endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ | ||