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-rw-r--r--arch/arm/mach-mx2/clock_imx27.c1656
1 files changed, 393 insertions, 1263 deletions
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index c69896d011a1..3f7280c490f0 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
4 * 5 *
5 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
@@ -20,23 +21,60 @@
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/io.h> 22#include <linux/io.h>
22#include <linux/module.h> 23#include <linux/module.h>
23#include <linux/spinlock.h>
24 24
25#include <mach/clock.h> 25#include <asm/clkdev.h>
26#include <mach/common.h>
27#include <asm/div64.h> 26#include <asm/div64.h>
28 27
29#include "crm_regs.h" 28#include <mach/clock.h>
30 29#include <mach/common.h>
31static struct clk ckil_clk; 30#include <mach/hardware.h>
32static struct clk mpll_clk; 31
33static struct clk mpll_main_clk[]; 32/* Register offsets */
34static struct clk spll_clk; 33#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
35 34#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
36static int _clk_enable(struct clk *clk) 35#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
36#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
37#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
38#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
39#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
40#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
41#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
42#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
43#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
44#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
45#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
46#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
47
48#define CCM_CSCR_UPDATE_DIS (1 << 31)
49#define CCM_CSCR_SSI2 (1 << 23)
50#define CCM_CSCR_SSI1 (1 << 22)
51#define CCM_CSCR_VPU (1 << 21)
52#define CCM_CSCR_MSHC (1 << 20)
53#define CCM_CSCR_SPLLRES (1 << 19)
54#define CCM_CSCR_MPLLRES (1 << 18)
55#define CCM_CSCR_SP (1 << 17)
56#define CCM_CSCR_MCU (1 << 16)
57#define CCM_CSCR_OSC26MDIV (1 << 4)
58#define CCM_CSCR_OSC26M (1 << 3)
59#define CCM_CSCR_FPM (1 << 2)
60#define CCM_CSCR_SPEN (1 << 1)
61#define CCM_CSCR_MPEN (1 << 0)
62
63/* i.MX27 TO 2+ */
64#define CCM_CSCR_ARM_SRC (1 << 15)
65
66#define CCM_SPCTL1_LF (1 << 15)
67#define CCM_SPCTL1_BRMO (1 << 6)
68
69static struct clk mpll_main1_clk, mpll_main2_clk;
70
71static int clk_pccr_enable(struct clk *clk)
37{ 72{
38 unsigned long reg; 73 unsigned long reg;
39 74
75 if (!clk->enable_reg)
76 return 0;
77
40 reg = __raw_readl(clk->enable_reg); 78 reg = __raw_readl(clk->enable_reg);
41 reg |= 1 << clk->enable_shift; 79 reg |= 1 << clk->enable_shift;
42 __raw_writel(reg, clk->enable_reg); 80 __raw_writel(reg, clk->enable_reg);
@@ -44,16 +82,19 @@ static int _clk_enable(struct clk *clk)
44 return 0; 82 return 0;
45} 83}
46 84
47static void _clk_disable(struct clk *clk) 85static void clk_pccr_disable(struct clk *clk)
48{ 86{
49 unsigned long reg; 87 unsigned long reg;
50 88
89 if (!clk->enable_reg)
90 return;
91
51 reg = __raw_readl(clk->enable_reg); 92 reg = __raw_readl(clk->enable_reg);
52 reg &= ~(1 << clk->enable_shift); 93 reg &= ~(1 << clk->enable_shift);
53 __raw_writel(reg, clk->enable_reg); 94 __raw_writel(reg, clk->enable_reg);
54} 95}
55 96
56static int _clk_spll_enable(struct clk *clk) 97static int clk_spll_enable(struct clk *clk)
57{ 98{
58 unsigned long reg; 99 unsigned long reg;
59 100
@@ -61,13 +102,12 @@ static int _clk_spll_enable(struct clk *clk)
61 reg |= CCM_CSCR_SPEN; 102 reg |= CCM_CSCR_SPEN;
62 __raw_writel(reg, CCM_CSCR); 103 __raw_writel(reg, CCM_CSCR);
63 104
64 while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) 105 while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
65 ;
66 106
67 return 0; 107 return 0;
68} 108}
69 109
70static void _clk_spll_disable(struct clk *clk) 110static void clk_spll_disable(struct clk *clk)
71{ 111{
72 unsigned long reg; 112 unsigned long reg;
73 113
@@ -76,192 +116,30 @@ static void _clk_spll_disable(struct clk *clk)
76 __raw_writel(reg, CCM_CSCR); 116 __raw_writel(reg, CCM_CSCR);
77} 117}
78 118
79static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1) 119static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
80{
81 unsigned long reg;
82
83 reg = __raw_readl(CCM_PCCR0);
84 reg |= mask0;
85 __raw_writel(reg, CCM_PCCR0);
86
87 reg = __raw_readl(CCM_PCCR1);
88 reg |= mask1;
89 __raw_writel(reg, CCM_PCCR1);
90
91}
92
93static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
94{
95 unsigned long reg;
96
97 reg = __raw_readl(CCM_PCCR0);
98 reg &= ~mask0;
99 __raw_writel(reg, CCM_PCCR0);
100
101 reg = __raw_readl(CCM_PCCR1);
102 reg &= ~mask1;
103 __raw_writel(reg, CCM_PCCR1);
104}
105
106static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
107{
108 unsigned long reg;
109
110 reg = __raw_readl(CCM_PCCR1);
111 reg |= mask1;
112 __raw_writel(reg, CCM_PCCR1);
113
114 reg = __raw_readl(CCM_PCCR0);
115 reg |= mask0;
116 __raw_writel(reg, CCM_PCCR0);
117}
118
119static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
120{
121 unsigned long reg;
122
123 reg = __raw_readl(CCM_PCCR1);
124 reg &= ~mask1;
125 __raw_writel(reg, CCM_PCCR1);
126
127 reg = __raw_readl(CCM_PCCR0);
128 reg &= ~mask0;
129 __raw_writel(reg, CCM_PCCR0);
130}
131
132static int _clk_dma_enable(struct clk *clk)
133{
134 _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
135
136 return 0;
137}
138
139static void _clk_dma_disable(struct clk *clk)
140{
141 _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
142}
143
144static int _clk_rtic_enable(struct clk *clk)
145{
146 _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
147
148 return 0;
149}
150
151static void _clk_rtic_disable(struct clk *clk)
152{
153 _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
154}
155
156static int _clk_emma_enable(struct clk *clk)
157{
158 _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
159
160 return 0;
161}
162
163static void _clk_emma_disable(struct clk *clk)
164{
165 _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
166}
167
168static int _clk_slcdc_enable(struct clk *clk)
169{
170 _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
171
172 return 0;
173}
174
175static void _clk_slcdc_disable(struct clk *clk)
176{
177 _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
178}
179
180static int _clk_fec_enable(struct clk *clk)
181{
182 _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
183
184 return 0;
185}
186
187static void _clk_fec_disable(struct clk *clk)
188{
189 _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
190}
191
192static int _clk_vpu_enable(struct clk *clk)
193{
194 unsigned long reg;
195
196 reg = __raw_readl(CCM_PCCR1);
197 reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
198 __raw_writel(reg, CCM_PCCR1);
199
200 return 0;
201}
202
203static void _clk_vpu_disable(struct clk *clk)
204{ 120{
205 unsigned long reg; 121 int cscr = __raw_readl(CCM_CSCR);
206
207 reg = __raw_readl(CCM_PCCR1);
208 reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
209 __raw_writel(reg, CCM_PCCR1);
210}
211
212static int _clk_sahara2_enable(struct clk *clk)
213{
214 _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
215
216 return 0;
217}
218
219static void _clk_sahara2_disable(struct clk *clk)
220{
221 _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
222}
223
224static int _clk_mstick1_enable(struct clk *clk)
225{
226 _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
227
228 return 0;
229}
230
231static void _clk_mstick1_disable(struct clk *clk)
232{
233 _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
234}
235
236#define CSCR() (__raw_readl(CCM_CSCR))
237#define PCDR0() (__raw_readl(CCM_PCDR0))
238#define PCDR1() (__raw_readl(CCM_PCDR1))
239
240static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
241{
242 int cscr = CSCR();
243 122
244 if (clk->parent == parent) 123 if (clk->parent == parent)
245 return 0; 124 return 0;
246 125
247 if (mx27_revision() >= CHIP_REV_2_0) { 126 if (mx27_revision() >= CHIP_REV_2_0) {
248 if (parent == &mpll_main_clk[0]) { 127 if (parent == &mpll_main1_clk) {
249 cscr |= CCM_CSCR_ARM_SRC; 128 cscr |= CCM_CSCR_ARM_SRC;
250 } else { 129 } else {
251 if (parent == &mpll_main_clk[1]) 130 if (parent == &mpll_main2_clk)
252 cscr &= ~CCM_CSCR_ARM_SRC; 131 cscr &= ~CCM_CSCR_ARM_SRC;
253 else 132 else
254 return -EINVAL; 133 return -EINVAL;
255 } 134 }
256 __raw_writel(cscr, CCM_CSCR); 135 __raw_writel(cscr, CCM_CSCR);
257 } else 136 clk->parent = parent;
258 return -ENODEV; 137 return 0;
259 138 }
260 clk->parent = parent; 139 return -ENODEV;
261 return 0;
262} 140}
263 141
264static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) 142static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
265{ 143{
266 int div; 144 int div;
267 unsigned long parent_rate; 145 unsigned long parent_rate;
@@ -278,7 +156,7 @@ static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
278 return parent_rate / div; 156 return parent_rate / div;
279} 157}
280 158
281static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) 159static int set_rate_cpu(struct clk *clk, unsigned long rate)
282{ 160{
283 unsigned int div; 161 unsigned int div;
284 uint32_t reg; 162 uint32_t reg;
@@ -295,19 +173,18 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
295 173
296 reg = __raw_readl(CCM_CSCR); 174 reg = __raw_readl(CCM_CSCR);
297 if (mx27_revision() >= CHIP_REV_2_0) { 175 if (mx27_revision() >= CHIP_REV_2_0) {
298 reg &= ~CCM_CSCR_ARM_MASK; 176 reg &= ~(3 << 12);
299 reg |= div << CCM_CSCR_ARM_OFFSET; 177 reg |= div << 12;
300 reg &= ~0x06; 178 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
301 __raw_writel(reg | 0x80000000, CCM_CSCR); 179 __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
302 } else { 180 } else {
303 printk(KERN_ERR "Cant set CPU frequency!\n"); 181 printk(KERN_ERR "Can't set CPU frequency!\n");
304 } 182 }
305 183
306 return 0; 184 return 0;
307} 185}
308 186
309static unsigned long _clk_perclkx_round_rate(struct clk *clk, 187static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
310 unsigned long rate)
311{ 188{
312 u32 div; 189 u32 div;
313 unsigned long parent_rate; 190 unsigned long parent_rate;
@@ -324,7 +201,7 @@ static unsigned long _clk_perclkx_round_rate(struct clk *clk,
324 return parent_rate / div; 201 return parent_rate / div;
325} 202}
326 203
327static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) 204static int set_rate_per(struct clk *clk, unsigned long rate)
328{ 205{
329 u32 reg; 206 u32 reg;
330 u32 div; 207 u32 div;
@@ -340,84 +217,65 @@ static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
340 return -EINVAL; 217 return -EINVAL;
341 div--; 218 div--;
342 219
343 reg = 220 reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
344 __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
345 (clk->id << 3));
346 reg |= div << (clk->id << 3); 221 reg |= div << (clk->id << 3);
347 __raw_writel(reg, CCM_PCDR1); 222 __raw_writel(reg, CCM_PCDR1);
348 223
349 return 0; 224 return 0;
350} 225}
351 226
352static unsigned long _clk_usb_recalc(struct clk *clk) 227static unsigned long get_rate_usb(struct clk *clk)
353{ 228{
354 unsigned long usb_pdf; 229 unsigned long usb_pdf;
355 unsigned long parent_rate; 230 unsigned long parent_rate;
356 231
357 parent_rate = clk_get_rate(clk->parent); 232 parent_rate = clk_get_rate(clk->parent);
358 233
359 usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; 234 usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
360 235
361 return parent_rate / (usb_pdf + 1U); 236 return parent_rate / (usb_pdf + 1U);
362} 237}
363 238
364static unsigned long _clk_ssi1_recalc(struct clk *clk) 239static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
365{ 240{
366 unsigned long ssi1_pdf;
367 unsigned long parent_rate; 241 unsigned long parent_rate;
368 242
369 parent_rate = clk_get_rate(clk->parent); 243 parent_rate = clk_get_rate(clk->parent);
370 244
371 ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
372 CCM_PCDR0_SSI1BAUDDIV_OFFSET;
373
374 if (mx27_revision() >= CHIP_REV_2_0) 245 if (mx27_revision() >= CHIP_REV_2_0)
375 ssi1_pdf += 4; 246 pdf += 4; /* MX27 TO2+ */
376 else 247 else
377 ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf; 248 pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
378 249
379 return 2UL * parent_rate / ssi1_pdf; 250 return 2UL * parent_rate / pdf;
380} 251}
381 252
382static unsigned long _clk_ssi2_recalc(struct clk *clk) 253static unsigned long get_rate_ssi1(struct clk *clk)
383{ 254{
384 unsigned long ssi2_pdf; 255 return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
385 unsigned long parent_rate; 256}
386
387 parent_rate = clk_get_rate(clk->parent);
388
389 ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
390 CCM_PCDR0_SSI2BAUDDIV_OFFSET;
391
392 if (mx27_revision() >= CHIP_REV_2_0)
393 ssi2_pdf += 4;
394 else
395 ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
396 257
397 return 2UL * parent_rate / ssi2_pdf; 258static unsigned long get_rate_ssi2(struct clk *clk)
259{
260 return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
398} 261}
399 262
400static unsigned long _clk_nfc_recalc(struct clk *clk) 263static unsigned long get_rate_nfc(struct clk *clk)
401{ 264{
402 unsigned long nfc_pdf; 265 unsigned long nfc_pdf;
403 unsigned long parent_rate; 266 unsigned long parent_rate;
404 267
405 parent_rate = clk_get_rate(clk->parent); 268 parent_rate = clk_get_rate(clk->parent);
406 269
407 if (mx27_revision() >= CHIP_REV_2_0) { 270 if (mx27_revision() >= CHIP_REV_2_0)
408 nfc_pdf = 271 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
409 (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >> 272 else
410 CCM_PCDR0_NFCDIV2_OFFSET; 273 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
411 } else {
412 nfc_pdf =
413 (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
414 CCM_PCDR0_NFCDIV_OFFSET;
415 }
416 274
417 return parent_rate / (nfc_pdf + 1); 275 return parent_rate / (nfc_pdf + 1);
418} 276}
419 277
420static unsigned long _clk_vpu_recalc(struct clk *clk) 278static unsigned long get_rate_vpu(struct clk *clk)
421{ 279{
422 unsigned long vpu_pdf; 280 unsigned long vpu_pdf;
423 unsigned long parent_rate; 281 unsigned long parent_rate;
@@ -425,25 +283,27 @@ static unsigned long _clk_vpu_recalc(struct clk *clk)
425 parent_rate = clk_get_rate(clk->parent); 283 parent_rate = clk_get_rate(clk->parent);
426 284
427 if (mx27_revision() >= CHIP_REV_2_0) { 285 if (mx27_revision() >= CHIP_REV_2_0) {
428 vpu_pdf = 286 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
429 (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
430 CCM_PCDR0_VPUDIV2_OFFSET;
431 vpu_pdf += 4; 287 vpu_pdf += 4;
432 } else { 288 } else {
433 vpu_pdf = 289 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
434 (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
435 CCM_PCDR0_VPUDIV_OFFSET;
436 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; 290 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
437 } 291 }
292
438 return 2UL * parent_rate / vpu_pdf; 293 return 2UL * parent_rate / vpu_pdf;
439} 294}
440 295
441static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) 296static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
442{ 297{
443 return clk->parent->round_rate(clk->parent, rate); 298 return clk->parent->round_rate(clk->parent, rate);
444} 299}
445 300
446static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) 301static unsigned long get_rate_parent(struct clk *clk)
302{
303 return clk_get_rate(clk->parent);
304}
305
306static int set_rate_parent(struct clk *clk, unsigned long rate)
447{ 307{
448 return clk->parent->set_rate(clk->parent, rate); 308 return clk->parent->set_rate(clk->parent, rate);
449} 309}
@@ -451,1112 +311,380 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
451/* in Hz */ 311/* in Hz */
452static unsigned long external_high_reference = 26000000; 312static unsigned long external_high_reference = 26000000;
453 313
454static unsigned long get_high_reference_clock_rate(struct clk *clk) 314static unsigned long get_rate_high_reference(struct clk *clk)
455{ 315{
456 return external_high_reference; 316 return external_high_reference;
457} 317}
458 318
459/*
460 * the high frequency external clock reference
461 * Default case is 26MHz. Could be changed at runtime
462 * with a call to change_external_high_reference()
463 */
464static struct clk ckih_clk = {
465 .name = "ckih",
466 .get_rate = get_high_reference_clock_rate,
467};
468
469/* in Hz */ 319/* in Hz */
470static unsigned long external_low_reference = 32768; 320static unsigned long external_low_reference = 32768;
471 321
472static unsigned long get_low_reference_clock_rate(struct clk *clk) 322static unsigned long get_rate_low_reference(struct clk *clk)
473{ 323{
474 return external_low_reference; 324 return external_low_reference;
475} 325}
476 326
477/* 327static unsigned long get_rate_fpm(struct clk *clk)
478 * the low frequency external clock reference
479 * Default case is 32.768kHz Could be changed at runtime
480 * with a call to change_external_low_reference()
481 */
482static struct clk ckil_clk = {
483 .name = "ckil",
484 .get_rate = get_low_reference_clock_rate,
485};
486
487static unsigned long get_mpll_clk(struct clk *clk)
488{ 328{
489 uint32_t reg; 329 return clk_get_rate(clk->parent) * 1024;
490 unsigned long ref_clk;
491 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
492 unsigned long long temp;
493
494 ref_clk = clk_get_rate(clk->parent);
495
496 reg = __raw_readl(CCM_MPCTL0);
497 pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
498 mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
499 mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
500 mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
501
502 mfi = (mfi <= 5) ? 5 : mfi;
503 temp = 2LL * ref_clk * mfn;
504 do_div(temp, mfd + 1);
505 temp = 2LL * ref_clk * mfi + temp;
506 do_div(temp, pdf + 1);
507
508 return (unsigned long)temp;
509} 330}
510 331
511static struct clk mpll_clk = { 332static unsigned long get_rate_mpll(struct clk *clk)
512 .name = "mpll", 333{
513 .parent = &ckih_clk, 334 return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
514 .get_rate = get_mpll_clk, 335 clk_get_rate(clk->parent));
515}; 336}
516 337
517static unsigned long _clk_mpll_main_get_rate(struct clk *clk) 338static unsigned long get_rate_mpll_main(struct clk *clk)
518{ 339{
519 unsigned long parent_rate; 340 unsigned long parent_rate;
520 341
521 parent_rate = clk_get_rate(clk->parent); 342 parent_rate = clk_get_rate(clk->parent);
522 343
523 /* i.MX27 TO2: 344 /* i.MX27 TO2:
524 * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2 345 * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
525 * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3 346 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
526 */ 347 */
527
528 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) 348 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
529 return 2UL * parent_rate / 3UL; 349 return 2UL * parent_rate / 3UL;
530 350
531 return parent_rate; 351 return parent_rate;
532} 352}
533 353
534static struct clk mpll_main_clk[] = { 354static unsigned long get_rate_spll(struct clk *clk)
535 {
536 /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
537 * It provide the clock source whose rate is same as MPLL
538 */
539 .name = "mpll_main",
540 .id = 0,
541 .parent = &mpll_clk,
542 .get_rate = _clk_mpll_main_get_rate
543 }, {
544 /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
545 * It provide the clock source whose rate is same MPLL * 2/3
546 */
547 .name = "mpll_main",
548 .id = 1,
549 .parent = &mpll_clk,
550 .get_rate = _clk_mpll_main_get_rate
551 }
552};
553
554static unsigned long get_spll_clk(struct clk *clk)
555{ 355{
556 uint32_t reg; 356 uint32_t reg;
557 unsigned long ref_clk; 357 unsigned long rate;
558 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
559 unsigned long long temp;
560 358
561 ref_clk = clk_get_rate(clk->parent); 359 rate = clk_get_rate(clk->parent);
562 360
563 reg = __raw_readl(CCM_SPCTL0); 361 reg = __raw_readl(CCM_SPCTL0);
564 /*TODO: This is TO2 Bug */ 362
363 /* On TO2 we have to write the value back. Otherwise we
364 * read 0 from this register the next time.
365 */
565 if (mx27_revision() >= CHIP_REV_2_0) 366 if (mx27_revision() >= CHIP_REV_2_0)
566 __raw_writel(reg, CCM_SPCTL0); 367 __raw_writel(reg, CCM_SPCTL0);
567 368
568 pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; 369 return mxc_decode_pll(reg, rate);
569 mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
570 mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
571 mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
572
573 mfi = (mfi <= 5) ? 5 : mfi;
574 temp = 2LL * ref_clk * mfn;
575 do_div(temp, mfd + 1);
576 temp = 2LL * ref_clk * mfi + temp;
577 do_div(temp, pdf + 1);
578
579 return (unsigned long)temp;
580} 370}
581 371
582static struct clk spll_clk = { 372static unsigned long get_rate_cpu(struct clk *clk)
583 .name = "spll",
584 .parent = &ckih_clk,
585 .get_rate = get_spll_clk,
586 .enable = _clk_spll_enable,
587 .disable = _clk_spll_disable,
588};
589
590static unsigned long get_cpu_clk(struct clk *clk)
591{ 373{
592 u32 div; 374 u32 div;
593 unsigned long rate; 375 unsigned long rate;
594 376
595 if (mx27_revision() >= CHIP_REV_2_0) 377 if (mx27_revision() >= CHIP_REV_2_0)
596 div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET; 378 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
597 else 379 else
598 div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; 380 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
599 381
600 rate = clk_get_rate(clk->parent); 382 rate = clk_get_rate(clk->parent);
601 return rate / (div + 1); 383 return rate / (div + 1);
602} 384}
603 385
604static struct clk cpu_clk = { 386static unsigned long get_rate_ahb(struct clk *clk)
605 .name = "cpu_clk",
606 .parent = &mpll_main_clk[1],
607 .set_parent = _clk_cpu_set_parent,
608 .round_rate = _clk_cpu_round_rate,
609 .get_rate = get_cpu_clk,
610 .set_rate = _clk_cpu_set_rate,
611};
612
613static unsigned long get_ahb_clk(struct clk *clk)
614{ 387{
615 unsigned long rate; 388 unsigned long rate, bclk_pdf;
616 unsigned long bclk_pdf;
617 389
618 if (mx27_revision() >= CHIP_REV_2_0) 390 if (mx27_revision() >= CHIP_REV_2_0)
619 bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) 391 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
620 >> CCM_CSCR_AHB_OFFSET;
621 else 392 else
622 bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) 393 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
623 >> CCM_CSCR_BCLK_OFFSET;
624 394
625 rate = clk_get_rate(clk->parent); 395 rate = clk_get_rate(clk->parent);
626 return rate / (bclk_pdf + 1); 396 return rate / (bclk_pdf + 1);
627} 397}
628 398
629static struct clk ahb_clk = { 399static unsigned long get_rate_ipg(struct clk *clk)
630 .name = "ahb_clk",
631 .parent = &mpll_main_clk[1],
632 .get_rate = get_ahb_clk,
633};
634
635static unsigned long get_ipg_clk(struct clk *clk)
636{ 400{
637 unsigned long rate; 401 unsigned long rate, ipg_pdf;
638 unsigned long ipg_pdf;
639 402
640 if (mx27_revision() >= CHIP_REV_2_0) 403 if (mx27_revision() >= CHIP_REV_2_0)
641 return clk_get_rate(clk->parent); 404 return clk_get_rate(clk->parent);
642 else 405 else
643 ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; 406 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
644 407
645 rate = clk_get_rate(clk->parent); 408 rate = clk_get_rate(clk->parent);
646 return rate / (ipg_pdf + 1); 409 return rate / (ipg_pdf + 1);
647} 410}
648 411
649static struct clk ipg_clk = { 412static unsigned long get_rate_per(struct clk *clk)
650 .name = "ipg_clk",
651 .parent = &ahb_clk,
652 .get_rate = get_ipg_clk,
653};
654
655static unsigned long _clk_perclkx_recalc(struct clk *clk)
656{ 413{
657 unsigned long perclk_pdf; 414 unsigned long perclk_pdf, parent_rate;
658 unsigned long parent_rate;
659 415
660 parent_rate = clk_get_rate(clk->parent); 416 parent_rate = clk_get_rate(clk->parent);
661 417
662 if (clk->id < 0 || clk->id > 3) 418 if (clk->id < 0 || clk->id > 3)
663 return 0; 419 return 0;
664 420
665 perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; 421 perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
666 422
667 return parent_rate / (perclk_pdf + 1); 423 return parent_rate / (perclk_pdf + 1);
668} 424}
669 425
670static struct clk per_clk[] = { 426/*
671 { 427 * the high frequency external clock reference
672 .name = "per_clk", 428 * Default case is 26MHz. Could be changed at runtime
673 .id = 0, 429 * with a call to change_external_high_reference()
674 .parent = &mpll_main_clk[1], 430 */
675 .get_rate = _clk_perclkx_recalc, 431static struct clk ckih_clk = {
676 .enable = _clk_enable, 432 .get_rate = get_rate_high_reference,
677 .enable_reg = CCM_PCCR1,
678 .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
679 .disable = _clk_disable,
680 }, {
681 .name = "per_clk",
682 .id = 1,
683 .parent = &mpll_main_clk[1],
684 .get_rate = _clk_perclkx_recalc,
685 .enable = _clk_enable,
686 .enable_reg = CCM_PCCR1,
687 .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
688 .disable = _clk_disable,
689 }, {
690 .name = "per_clk",
691 .id = 2,
692 .parent = &mpll_main_clk[1],
693 .round_rate = _clk_perclkx_round_rate,
694 .set_rate = _clk_perclkx_set_rate,
695 .get_rate = _clk_perclkx_recalc,
696 .enable = _clk_enable,
697 .enable_reg = CCM_PCCR1,
698 .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
699 .disable = _clk_disable,
700 }, {
701 .name = "per_clk",
702 .id = 3,
703 .parent = &mpll_main_clk[1],
704 .round_rate = _clk_perclkx_round_rate,
705 .set_rate = _clk_perclkx_set_rate,
706 .get_rate = _clk_perclkx_recalc,
707 .enable = _clk_enable,
708 .enable_reg = CCM_PCCR1,
709 .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
710 .disable = _clk_disable,
711 },
712};
713
714struct clk uart1_clk[] = {
715 {
716 .name = "uart_clk",
717 .id = 0,
718 .parent = &per_clk[0],
719 .secondary = &uart1_clk[1],
720 }, {
721 .name = "uart_ipg_clk",
722 .id = 0,
723 .parent = &ipg_clk,
724 .enable = _clk_enable,
725 .enable_reg = CCM_PCCR1,
726 .enable_shift = CCM_PCCR1_UART1_OFFSET,
727 .disable = _clk_disable,
728 },
729};
730
731struct clk uart2_clk[] = {
732 {
733 .name = "uart_clk",
734 .id = 1,
735 .parent = &per_clk[0],
736 .secondary = &uart2_clk[1],
737 }, {
738 .name = "uart_ipg_clk",
739 .id = 1,
740 .parent = &ipg_clk,
741 .enable = _clk_enable,
742 .enable_reg = CCM_PCCR1,
743 .enable_shift = CCM_PCCR1_UART2_OFFSET,
744 .disable = _clk_disable,
745 },
746};
747
748struct clk uart3_clk[] = {
749 {
750 .name = "uart_clk",
751 .id = 2,
752 .parent = &per_clk[0],
753 .secondary = &uart3_clk[1],
754 }, {
755 .name = "uart_ipg_clk",
756 .id = 2,
757 .parent = &ipg_clk,
758 .enable = _clk_enable,
759 .enable_reg = CCM_PCCR1,
760 .enable_shift = CCM_PCCR1_UART3_OFFSET,
761 .disable = _clk_disable,
762 },
763};
764
765struct clk uart4_clk[] = {
766 {
767 .name = "uart_clk",
768 .id = 3,
769 .parent = &per_clk[0],
770 .secondary = &uart4_clk[1],
771 }, {
772 .name = "uart_ipg_clk",
773 .id = 3,
774 .parent = &ipg_clk,
775 .enable = _clk_enable,
776 .enable_reg = CCM_PCCR1,
777 .enable_shift = CCM_PCCR1_UART4_OFFSET,
778 .disable = _clk_disable,
779 },
780};
781
782struct clk uart5_clk[] = {
783 {
784 .name = "uart_clk",
785 .id = 4,
786 .parent = &per_clk[0],
787 .secondary = &uart5_clk[1],
788 }, {
789 .name = "uart_ipg_clk",
790 .id = 4,
791 .parent = &ipg_clk,
792 .enable = _clk_enable,
793 .enable_reg = CCM_PCCR1,
794 .enable_shift = CCM_PCCR1_UART5_OFFSET,
795 .disable = _clk_disable,
796 },
797};
798
799struct clk uart6_clk[] = {
800 {
801 .name = "uart_clk",
802 .id = 5,
803 .parent = &per_clk[0],
804 .secondary = &uart6_clk[1],
805 }, {
806 .name = "uart_ipg_clk",
807 .id = 5,
808 .parent = &ipg_clk,
809 .enable = _clk_enable,
810 .enable_reg = CCM_PCCR1,
811 .enable_shift = CCM_PCCR1_UART6_OFFSET,
812 .disable = _clk_disable,
813 },
814};
815
816static struct clk gpt1_clk[] = {
817 {
818 .name = "gpt_clk",
819 .id = 0,
820 .parent = &per_clk[0],
821 .secondary = &gpt1_clk[1],
822 }, {
823 .name = "gpt_ipg_clk",
824 .id = 0,
825 .parent = &ipg_clk,
826 .enable = _clk_enable,
827 .enable_reg = CCM_PCCR0,
828 .enable_shift = CCM_PCCR0_GPT1_OFFSET,
829 .disable = _clk_disable,
830 },
831};
832
833static struct clk gpt2_clk[] = {
834 {
835 .name = "gpt_clk",
836 .id = 1,
837 .parent = &per_clk[0],
838 .secondary = &gpt2_clk[1],
839 }, {
840 .name = "gpt_ipg_clk",
841 .id = 1,
842 .parent = &ipg_clk,
843 .enable = _clk_enable,
844 .enable_reg = CCM_PCCR0,
845 .enable_shift = CCM_PCCR0_GPT2_OFFSET,
846 .disable = _clk_disable,
847 },
848};
849
850static struct clk gpt3_clk[] = {
851 {
852 .name = "gpt_clk",
853 .id = 2,
854 .parent = &per_clk[0],
855 .secondary = &gpt3_clk[1],
856 }, {
857 .name = "gpt_ipg_clk",
858 .id = 2,
859 .parent = &ipg_clk,
860 .enable = _clk_enable,
861 .enable_reg = CCM_PCCR0,
862 .enable_shift = CCM_PCCR0_GPT3_OFFSET,
863 .disable = _clk_disable,
864 },
865};
866
867static struct clk gpt4_clk[] = {
868 {
869 .name = "gpt_clk",
870 .id = 3,
871 .parent = &per_clk[0],
872 .secondary = &gpt4_clk[1],
873 }, {
874 .name = "gpt_ipg_clk",
875 .id = 3,
876 .parent = &ipg_clk,
877 .enable = _clk_enable,
878 .enable_reg = CCM_PCCR0,
879 .enable_shift = CCM_PCCR0_GPT4_OFFSET,
880 .disable = _clk_disable,
881 },
882};
883
884static struct clk gpt5_clk[] = {
885 {
886 .name = "gpt_clk",
887 .id = 4,
888 .parent = &per_clk[0],
889 .secondary = &gpt5_clk[1],
890 }, {
891 .name = "gpt_ipg_clk",
892 .id = 4,
893 .parent = &ipg_clk,
894 .enable = _clk_enable,
895 .enable_reg = CCM_PCCR0,
896 .enable_shift = CCM_PCCR0_GPT5_OFFSET,
897 .disable = _clk_disable,
898 },
899}; 433};
900 434
901static struct clk gpt6_clk[] = { 435static struct clk mpll_clk = {
902 { 436 .parent = &ckih_clk,
903 .name = "gpt_clk", 437 .get_rate = get_rate_mpll,
904 .id = 5,
905 .parent = &per_clk[0],
906 .secondary = &gpt6_clk[1],
907 }, {
908 .name = "gpt_ipg_clk",
909 .id = 5,
910 .parent = &ipg_clk,
911 .enable = _clk_enable,
912 .enable_reg = CCM_PCCR0,
913 .enable_shift = CCM_PCCR0_GPT6_OFFSET,
914 .disable = _clk_disable,
915 },
916}; 438};
917 439
918static struct clk pwm_clk[] = { 440/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
919 { 441 * It provides the clock source whose rate is same as MPLL
920 .name = "pwm_clk", 442 */
921 .parent = &per_clk[0], 443static struct clk mpll_main1_clk = {
922 .secondary = &pwm_clk[1], 444 .id = 0,
923 }, { 445 .parent = &mpll_clk,
924 .name = "pwm_clk", 446 .get_rate = get_rate_mpll_main,
925 .parent = &ipg_clk,
926 .enable = _clk_enable,
927 .enable_reg = CCM_PCCR0,
928 .enable_shift = CCM_PCCR0_PWM_OFFSET,
929 .disable = _clk_disable,
930 },
931}; 447};
932 448
933static struct clk sdhc1_clk[] = { 449/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
934 { 450 * It provides the clock source whose rate is same MPLL * 2 / 3
935 .name = "sdhc_clk", 451 */
936 .id = 0, 452static struct clk mpll_main2_clk = {
937 .parent = &per_clk[1], 453 .id = 1,
938 .secondary = &sdhc1_clk[1], 454 .parent = &mpll_clk,
939 }, { 455 .get_rate = get_rate_mpll_main,
940 .name = "sdhc_ipg_clk",
941 .id = 0,
942 .parent = &ipg_clk,
943 .enable = _clk_enable,
944 .enable_reg = CCM_PCCR0,
945 .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
946 .disable = _clk_disable,
947 },
948}; 456};
949 457
950static struct clk sdhc2_clk[] = { 458static struct clk ahb_clk = {
951 { 459 .parent = &mpll_main2_clk,
952 .name = "sdhc_clk", 460 .get_rate = get_rate_ahb,
953 .id = 1,
954 .parent = &per_clk[1],
955 .secondary = &sdhc2_clk[1],
956 }, {
957 .name = "sdhc_ipg_clk",
958 .id = 1,
959 .parent = &ipg_clk,
960 .enable = _clk_enable,
961 .enable_reg = CCM_PCCR0,
962 .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
963 .disable = _clk_disable,
964 },
965}; 461};
966 462
967static struct clk sdhc3_clk[] = { 463static struct clk ipg_clk = {
968 { 464 .parent = &ahb_clk,
969 .name = "sdhc_clk", 465 .get_rate = get_rate_ipg,
970 .id = 2,
971 .parent = &per_clk[1],
972 .secondary = &sdhc3_clk[1],
973 }, {
974 .name = "sdhc_ipg_clk",
975 .id = 2,
976 .parent = &ipg_clk,
977 .enable = _clk_enable,
978 .enable_reg = CCM_PCCR0,
979 .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
980 .disable = _clk_disable,
981 },
982}; 466};
983 467
984static struct clk cspi1_clk[] = { 468static struct clk cpu_clk = {
985 { 469 .parent = &mpll_main2_clk,
986 .name = "cspi_clk", 470 .set_parent = clk_cpu_set_parent,
987 .id = 0, 471 .round_rate = round_rate_cpu,
988 .parent = &per_clk[1], 472 .get_rate = get_rate_cpu,
989 .secondary = &cspi1_clk[1], 473 .set_rate = set_rate_cpu,
990 }, {
991 .name = "cspi_ipg_clk",
992 .id = 0,
993 .parent = &ipg_clk,
994 .enable = _clk_enable,
995 .enable_reg = CCM_PCCR0,
996 .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
997 .disable = _clk_disable,
998 },
999}; 474};
1000 475
1001static struct clk cspi2_clk[] = { 476static struct clk spll_clk = {
1002 { 477 .parent = &ckih_clk,
1003 .name = "cspi_clk", 478 .get_rate = get_rate_spll,
1004 .id = 1, 479 .enable = clk_spll_enable,
1005 .parent = &per_clk[1], 480 .disable = clk_spll_disable,
1006 .secondary = &cspi2_clk[1],
1007 }, {
1008 .name = "cspi_ipg_clk",
1009 .id = 1,
1010 .parent = &ipg_clk,
1011 .enable = _clk_enable,
1012 .enable_reg = CCM_PCCR0,
1013 .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
1014 .disable = _clk_disable,
1015 },
1016}; 481};
1017 482
1018static struct clk cspi3_clk[] = { 483/*
1019 { 484 * the low frequency external clock reference
1020 .name = "cspi_clk", 485 * Default case is 32.768kHz.
1021 .id = 2, 486 */
1022 .parent = &per_clk[1], 487static struct clk ckil_clk = {
1023 .secondary = &cspi3_clk[1], 488 .get_rate = get_rate_low_reference,
1024 }, {
1025 .name = "cspi_ipg_clk",
1026 .id = 2,
1027 .parent = &ipg_clk,
1028 .enable = _clk_enable,
1029 .enable_reg = CCM_PCCR0,
1030 .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
1031 .disable = _clk_disable,
1032 },
1033}; 489};
1034 490
1035static struct clk lcdc_clk[] = { 491/* Output of frequency pre multiplier */
1036 { 492static struct clk fpm_clk = {
1037 .name = "lcdc_clk", 493 .parent = &ckil_clk,
1038 .parent = &per_clk[2], 494 .get_rate = get_rate_fpm,
1039 .secondary = &lcdc_clk[1],
1040 .round_rate = _clk_parent_round_rate,
1041 .set_rate = _clk_parent_set_rate,
1042 }, {
1043 .name = "lcdc_ipg_clk",
1044 .parent = &ipg_clk,
1045 .secondary = &lcdc_clk[2],
1046 .enable = _clk_enable,
1047 .enable_reg = CCM_PCCR0,
1048 .enable_shift = CCM_PCCR0_LCDC_OFFSET,
1049 .disable = _clk_disable,
1050 }, {
1051 .name = "lcdc_ahb_clk",
1052 .parent = &ahb_clk,
1053 .enable = _clk_enable,
1054 .enable_reg = CCM_PCCR1,
1055 .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
1056 .disable = _clk_disable,
1057 },
1058}; 495};
1059 496
1060static struct clk csi_clk[] = { 497#define PCCR0 CCM_PCCR0
1061 { 498#define PCCR1 CCM_PCCR1
1062 .name = "csi_perclk",
1063 .parent = &per_clk[3],
1064 .secondary = &csi_clk[1],
1065 .round_rate = _clk_parent_round_rate,
1066 .set_rate = _clk_parent_set_rate,
1067 }, {
1068 .name = "csi_ahb_clk",
1069 .parent = &ahb_clk,
1070 .enable = _clk_enable,
1071 .enable_reg = CCM_PCCR1,
1072 .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
1073 .disable = _clk_disable,
1074 },
1075};
1076 499
1077static struct clk usb_clk[] = { 500#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
1078 { 501 static struct clk name = { \
1079 .name = "usb_clk", 502 .id = i, \
1080 .parent = &spll_clk, 503 .enable_reg = er, \
1081 .get_rate = _clk_usb_recalc, 504 .enable_shift = es, \
1082 .enable = _clk_enable, 505 .get_rate = gr, \
1083 .enable_reg = CCM_PCCR1, 506 .enable = clk_pccr_enable, \
1084 .enable_shift = CCM_PCCR1_USBOTG_OFFSET, 507 .disable = clk_pccr_disable, \
1085 .disable = _clk_disable, 508 .secondary = s, \
1086 }, { 509 .parent = p, \
1087 .name = "usb_ahb_clk",
1088 .parent = &ahb_clk,
1089 .enable = _clk_enable,
1090 .enable_reg = CCM_PCCR1,
1091 .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
1092 .disable = _clk_disable,
1093 } 510 }
1094};
1095 511
1096static struct clk ssi1_clk[] = { 512#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
1097 { 513 static struct clk name = { \
1098 .name = "ssi_clk", 514 .id = i, \
1099 .id = 0, 515 .enable_reg = er, \
1100 .parent = &mpll_main_clk[1], 516 .enable_shift = es, \
1101 .secondary = &ssi1_clk[1], 517 .get_rate = get_rate_##getsetround, \
1102 .get_rate = _clk_ssi1_recalc, 518 .set_rate = set_rate_##getsetround, \
1103 .enable = _clk_enable, 519 .round_rate = round_rate_##getsetround, \
1104 .enable_reg = CCM_PCCR1, 520 .enable = clk_pccr_enable, \
1105 .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET, 521 .disable = clk_pccr_disable, \
1106 .disable = _clk_disable, 522 .secondary = s, \
1107 }, { 523 .parent = p, \
1108 .name = "ssi_ipg_clk", 524 }
1109 .id = 0,
1110 .parent = &ipg_clk,
1111 .enable = _clk_enable,
1112 .enable_reg = CCM_PCCR0,
1113 .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
1114 .disable = _clk_disable,
1115 },
1116};
1117 525
1118static struct clk ssi2_clk[] = { 526/* Forward declaration to keep the following list in order */
1119 { 527static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
1120 .name = "ssi_clk", 528 dma_clk1, lcdc_clk2, vpu_clk1;
1121 .id = 1, 529
1122 .parent = &mpll_main_clk[1], 530/* All clocks we can gate through PCCRx in the order of PCCRx bits */
1123 .secondary = &ssi2_clk[1], 531DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
1124 .get_rate = _clk_ssi2_recalc, 532DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
1125 .enable = _clk_enable, 533DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
1126 .enable_reg = CCM_PCCR1, 534DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
1127 .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET, 535DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
1128 .disable = _clk_disable, 536DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
1129 }, { 537DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
1130 .name = "ssi_ipg_clk", 538DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
1131 .id = 1, 539DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
1132 .parent = &ipg_clk, 540DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
1133 .enable = _clk_enable, 541DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk);
1134 .enable_reg = CCM_PCCR0, 542DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk);
1135 .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET, 543DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk);
1136 .disable = _clk_disable, 544DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
545DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk);
546DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk);
547DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk);
548DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk);
549DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
550DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk);
551DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk);
552DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk);
553DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk);
554DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk);
555DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk);
556DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
557DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
558DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
559DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
560DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk);
561DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk);
562
563DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk);
564DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk);
565DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
566DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
567DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
568DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
569DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
570DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk);
571DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk);
572DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk);
573DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk);
574DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
575DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk);
576DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk);
577DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk);
578DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk);
579DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk);
580DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk);
581DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk);
582DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk);
583DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk);
584DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk);
585DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk);
586DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
587DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk);
588DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk);
589DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk);
590DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk);
591DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
592DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
593
594/* Clocks we cannot directly gate, but drivers need their rates */
595DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
596DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
597DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
598DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
599DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
600DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
601DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
602DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
603DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
604DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
605DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
606DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
607DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
608DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
609DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
610DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
611DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
612DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
613DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
614DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
615DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
616
617#define _REGISTER_CLOCK(d, n, c) \
618 { \
619 .dev_id = d, \
620 .con_id = n, \
621 .clk = &c, \
1137 }, 622 },
1138};
1139
1140static struct clk nfc_clk = {
1141 .name = "nfc_clk",
1142 .parent = &cpu_clk,
1143 .get_rate = _clk_nfc_recalc,
1144 .enable = _clk_enable,
1145 .enable_reg = CCM_PCCR1,
1146 .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
1147 .disable = _clk_disable,
1148};
1149
1150static struct clk vpu_clk = {
1151 .name = "vpu_clk",
1152 .parent = &mpll_main_clk[1],
1153 .get_rate = _clk_vpu_recalc,
1154 .enable = _clk_vpu_enable,
1155 .disable = _clk_vpu_disable,
1156};
1157
1158static struct clk dma_clk = {
1159 .name = "dma_clk",
1160 .parent = &ahb_clk,
1161 .enable = _clk_dma_enable,
1162 .disable = _clk_dma_disable,
1163};
1164
1165static struct clk rtic_clk = {
1166 .name = "rtic_clk",
1167 .parent = &ahb_clk,
1168 .enable = _clk_rtic_enable,
1169 .disable = _clk_rtic_disable,
1170};
1171 623
1172static struct clk brom_clk = { 624static struct clk_lookup lookups[] __initdata = {
1173 .name = "brom_clk", 625 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1174 .parent = &ahb_clk, 626 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1175 .enable = _clk_enable, 627 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1176 .enable_reg = CCM_PCCR1, 628 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
1177 .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET, 629 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
1178 .disable = _clk_disable, 630 _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
1179}; 631 _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
1180 632 _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
1181static struct clk emma_clk = { 633 _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
1182 .name = "emma_clk", 634 _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
1183 .parent = &ahb_clk, 635 _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
1184 .enable = _clk_emma_enable, 636 _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
1185 .disable = _clk_emma_disable, 637 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
1186}; 638 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
1187 639 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
1188static struct clk slcdc_clk = { 640 _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
1189 .name = "slcdc_clk", 641 _REGISTER_CLOCK(NULL, "cspi1", cspi1_clk)
1190 .parent = &ahb_clk, 642 _REGISTER_CLOCK(NULL, "cspi2", cspi2_clk)
1191 .enable = _clk_slcdc_enable, 643 _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
1192 .disable = _clk_slcdc_disable, 644 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
1193}; 645 _REGISTER_CLOCK(NULL, "csi", csi_clk)
1194 646 _REGISTER_CLOCK(NULL, "usb", usb_clk)
1195static struct clk fec_clk = { 647 _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
1196 .name = "fec_clk", 648 _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
1197 .parent = &ahb_clk, 649 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
1198 .enable = _clk_fec_enable, 650 _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
1199 .disable = _clk_fec_disable, 651 _REGISTER_CLOCK(NULL, "dma", dma_clk)
1200}; 652 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
1201 653 _REGISTER_CLOCK(NULL, "brom", brom_clk)
1202static struct clk emi_clk = { 654 _REGISTER_CLOCK(NULL, "emma", emma_clk)
1203 .name = "emi_clk", 655 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
1204 .parent = &ahb_clk, 656 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1205 .enable = _clk_enable, 657 _REGISTER_CLOCK(NULL, "emi", emi_clk)
1206 .enable_reg = CCM_PCCR1, 658 _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
1207 .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET, 659 _REGISTER_CLOCK(NULL, "ata", ata_clk)
1208 .disable = _clk_disable, 660 _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
1209}; 661 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
1210 662 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
1211static struct clk sahara2_clk = { 663 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1212 .name = "sahara_clk", 664 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1213 .parent = &ahb_clk, 665 _REGISTER_CLOCK(NULL, "iim", iim_clk)
1214 .enable = _clk_sahara2_enable, 666 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
1215 .disable = _clk_sahara2_disable, 667 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
1216}; 668 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
1217 669 _REGISTER_CLOCK(NULL, "scc", scc_clk)
1218static struct clk ata_clk = { 670};
1219 .name = "ata_clk", 671
1220 .parent = &ahb_clk, 672/* Adjust the clock path for TO2 and later */
1221 .enable = _clk_enable, 673static void __init to2_adjust_clocks(void)
1222 .enable_reg = CCM_PCCR1, 674{
1223 .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET, 675 unsigned long cscr = __raw_readl(CCM_CSCR);
1224 .disable = _clk_disable,
1225};
1226
1227static struct clk mstick1_clk = {
1228 .name = "mstick1_clk",
1229 .parent = &ipg_clk,
1230 .enable = _clk_mstick1_enable,
1231 .disable = _clk_mstick1_disable,
1232};
1233
1234static struct clk wdog_clk = {
1235 .name = "wdog_clk",
1236 .parent = &ipg_clk,
1237 .enable = _clk_enable,
1238 .enable_reg = CCM_PCCR1,
1239 .enable_shift = CCM_PCCR1_WDT_OFFSET,
1240 .disable = _clk_disable,
1241};
1242
1243static struct clk gpio_clk = {
1244 .name = "gpio_clk",
1245 .parent = &ipg_clk,
1246 .enable = _clk_enable,
1247 .enable_reg = CCM_PCCR1,
1248 .enable_shift = CCM_PCCR0_GPIO_OFFSET,
1249 .disable = _clk_disable,
1250};
1251
1252static struct clk i2c_clk[] = {
1253 {
1254 .name = "i2c_clk",
1255 .id = 0,
1256 .parent = &ipg_clk,
1257 .enable = _clk_enable,
1258 .enable_reg = CCM_PCCR0,
1259 .enable_shift = CCM_PCCR0_I2C1_OFFSET,
1260 .disable = _clk_disable,
1261 }, {
1262 .name = "i2c_clk",
1263 .id = 1,
1264 .parent = &ipg_clk,
1265 .enable = _clk_enable,
1266 .enable_reg = CCM_PCCR0,
1267 .enable_shift = CCM_PCCR0_I2C2_OFFSET,
1268 .disable = _clk_disable,
1269 },
1270};
1271
1272static struct clk iim_clk = {
1273 .name = "iim_clk",
1274 .parent = &ipg_clk,
1275 .enable = _clk_enable,
1276 .enable_reg = CCM_PCCR0,
1277 .enable_shift = CCM_PCCR0_IIM_OFFSET,
1278 .disable = _clk_disable,
1279};
1280
1281static struct clk kpp_clk = {
1282 .name = "kpp_clk",
1283 .parent = &ipg_clk,
1284 .enable = _clk_enable,
1285 .enable_reg = CCM_PCCR0,
1286 .enable_shift = CCM_PCCR0_KPP_OFFSET,
1287 .disable = _clk_disable,
1288};
1289
1290static struct clk owire_clk = {
1291 .name = "owire_clk",
1292 .parent = &ipg_clk,
1293 .enable = _clk_enable,
1294 .enable_reg = CCM_PCCR0,
1295 .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
1296 .disable = _clk_disable,
1297};
1298
1299static struct clk rtc_clk = {
1300 .name = "rtc_clk",
1301 .parent = &ipg_clk,
1302 .enable = _clk_enable,
1303 .enable_reg = CCM_PCCR0,
1304 .enable_shift = CCM_PCCR0_RTC_OFFSET,
1305 .disable = _clk_disable,
1306};
1307
1308static struct clk scc_clk = {
1309 .name = "scc_clk",
1310 .parent = &ipg_clk,
1311 .enable = _clk_enable,
1312 .enable_reg = CCM_PCCR0,
1313 .enable_shift = CCM_PCCR0_SCC_OFFSET,
1314 .disable = _clk_disable,
1315};
1316
1317static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
1318{
1319 u32 div;
1320 unsigned long parent_rate;
1321
1322 parent_rate = clk_get_rate(clk->parent);
1323 div = parent_rate / rate;
1324 if (parent_rate % rate)
1325 div++;
1326
1327 if (div > 8)
1328 div = 8;
1329
1330 return parent_rate / div;
1331}
1332
1333static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
1334{
1335 u32 reg;
1336 u32 div;
1337 unsigned long parent_rate;
1338
1339 parent_rate = clk_get_rate(clk->parent);
1340
1341 div = parent_rate / rate;
1342
1343 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
1344 return -EINVAL;
1345 div--;
1346
1347 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
1348 reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
1349 __raw_writel(reg, CCM_PCDR0);
1350
1351 return 0;
1352}
1353
1354static unsigned long _clk_clko_recalc(struct clk *clk)
1355{
1356 u32 div;
1357 unsigned long parent_rate;
1358
1359 parent_rate = clk_get_rate(clk->parent);
1360
1361 div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
1362 CCM_PCDR0_CLKODIV_OFFSET;
1363 div++;
1364
1365 return parent_rate / div;
1366}
1367
1368static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
1369{
1370 u32 reg;
1371
1372 reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
1373
1374 if (parent == &ckil_clk)
1375 reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
1376 else if (parent == &ckih_clk)
1377 reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
1378 else if (parent == mpll_clk.parent)
1379 reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
1380 else if (parent == spll_clk.parent)
1381 reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
1382 else if (parent == &mpll_clk)
1383 reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
1384 else if (parent == &spll_clk)
1385 reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
1386 else if (parent == &cpu_clk)
1387 reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
1388 else if (parent == &ahb_clk)
1389 reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
1390 else if (parent == &ipg_clk)
1391 reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
1392 else if (parent == &per_clk[0])
1393 reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
1394 else if (parent == &per_clk[1])
1395 reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
1396 else if (parent == &per_clk[2])
1397 reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
1398 else if (parent == &per_clk[3])
1399 reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
1400 else if (parent == &ssi1_clk[0])
1401 reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
1402 else if (parent == &ssi2_clk[0])
1403 reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
1404 else if (parent == &nfc_clk)
1405 reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
1406 else if (parent == &mstick1_clk)
1407 reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
1408 else if (parent == &vpu_clk)
1409 reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
1410 else if (parent == &usb_clk[0])
1411 reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
1412 else
1413 return -EINVAL;
1414
1415 __raw_writel(reg, CCM_CCSR);
1416
1417 return 0;
1418}
1419
1420static int _clk_clko_enable(struct clk *clk)
1421{
1422 u32 reg;
1423
1424 reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
1425 __raw_writel(reg, CCM_PCDR0);
1426
1427 return 0;
1428}
1429
1430static void _clk_clko_disable(struct clk *clk)
1431{
1432 u32 reg;
1433
1434 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
1435 __raw_writel(reg, CCM_PCDR0);
1436}
1437
1438static struct clk clko_clk = {
1439 .name = "clko_clk",
1440 .get_rate = _clk_clko_recalc,
1441 .set_rate = _clk_clko_set_rate,
1442 .round_rate = _clk_clko_round_rate,
1443 .set_parent = _clk_clko_set_parent,
1444 .enable = _clk_clko_enable,
1445 .disable = _clk_clko_disable,
1446};
1447
1448static struct clk *mxc_clks[] = {
1449 &ckih_clk,
1450 &ckil_clk,
1451 &mpll_clk,
1452 &mpll_main_clk[0],
1453 &mpll_main_clk[1],
1454 &spll_clk,
1455 &cpu_clk,
1456 &ahb_clk,
1457 &ipg_clk,
1458 &per_clk[0],
1459 &per_clk[1],
1460 &per_clk[2],
1461 &per_clk[3],
1462 &clko_clk,
1463 &uart1_clk[0],
1464 &uart1_clk[1],
1465 &uart2_clk[0],
1466 &uart2_clk[1],
1467 &uart3_clk[0],
1468 &uart3_clk[1],
1469 &uart4_clk[0],
1470 &uart4_clk[1],
1471 &uart5_clk[0],
1472 &uart5_clk[1],
1473 &uart6_clk[0],
1474 &uart6_clk[1],
1475 &gpt1_clk[0],
1476 &gpt1_clk[1],
1477 &gpt2_clk[0],
1478 &gpt2_clk[1],
1479 &gpt3_clk[0],
1480 &gpt3_clk[1],
1481 &gpt4_clk[0],
1482 &gpt4_clk[1],
1483 &gpt5_clk[0],
1484 &gpt5_clk[1],
1485 &gpt6_clk[0],
1486 &gpt6_clk[1],
1487 &pwm_clk[0],
1488 &pwm_clk[1],
1489 &sdhc1_clk[0],
1490 &sdhc1_clk[1],
1491 &sdhc2_clk[0],
1492 &sdhc2_clk[1],
1493 &sdhc3_clk[0],
1494 &sdhc3_clk[1],
1495 &cspi1_clk[0],
1496 &cspi1_clk[1],
1497 &cspi2_clk[0],
1498 &cspi2_clk[1],
1499 &cspi3_clk[0],
1500 &cspi3_clk[1],
1501 &lcdc_clk[0],
1502 &lcdc_clk[1],
1503 &lcdc_clk[2],
1504 &csi_clk[0],
1505 &csi_clk[1],
1506 &usb_clk[0],
1507 &usb_clk[1],
1508 &ssi1_clk[0],
1509 &ssi1_clk[1],
1510 &ssi2_clk[0],
1511 &ssi2_clk[1],
1512 &nfc_clk,
1513 &vpu_clk,
1514 &dma_clk,
1515 &rtic_clk,
1516 &brom_clk,
1517 &emma_clk,
1518 &slcdc_clk,
1519 &fec_clk,
1520 &emi_clk,
1521 &sahara2_clk,
1522 &ata_clk,
1523 &mstick1_clk,
1524 &wdog_clk,
1525 &gpio_clk,
1526 &i2c_clk[0],
1527 &i2c_clk[1],
1528 &iim_clk,
1529 &kpp_clk,
1530 &owire_clk,
1531 &rtc_clk,
1532 &scc_clk,
1533};
1534
1535void __init change_external_low_reference(unsigned long new_ref)
1536{
1537 external_low_reference = new_ref;
1538}
1539
1540unsigned long __init clk_early_get_timer_rate(void)
1541{
1542 return clk_get_rate(&per_clk[0]);
1543}
1544
1545static void __init probe_mxc_clocks(void)
1546{
1547 int i;
1548 676
1549 if (mx27_revision() >= CHIP_REV_2_0) { 677 if (mx27_revision() >= CHIP_REV_2_0) {
1550 if (CSCR() & 0x8000) 678 if (cscr & CCM_CSCR_ARM_SRC)
1551 cpu_clk.parent = &mpll_main_clk[0]; 679 cpu_clk.parent = &mpll_main1_clk;
1552 680
1553 if (!(CSCR() & 0x00800000)) 681 if (!(cscr & CCM_CSCR_SSI2))
1554 ssi2_clk[0].parent = &spll_clk; 682 ssi1_clk.parent = &spll_clk;
1555 683
1556 if (!(CSCR() & 0x00400000)) 684 if (!(cscr & CCM_CSCR_SSI1))
1557 ssi1_clk[0].parent = &spll_clk; 685 ssi1_clk.parent = &spll_clk;
1558 686
1559 if (!(CSCR() & 0x00200000)) 687 if (!(cscr & CCM_CSCR_VPU))
1560 vpu_clk.parent = &spll_clk; 688 vpu_clk.parent = &spll_clk;
1561 } else { 689 } else {
1562 cpu_clk.parent = &mpll_clk; 690 cpu_clk.parent = &mpll_clk;
@@ -1565,11 +693,13 @@ static void __init probe_mxc_clocks(void)
1565 cpu_clk.set_rate = NULL; 693 cpu_clk.set_rate = NULL;
1566 ahb_clk.parent = &mpll_clk; 694 ahb_clk.parent = &mpll_clk;
1567 695
1568 for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) 696 per1_clk.parent = &mpll_clk;
1569 per_clk[i].parent = &mpll_clk; 697 per2_clk.parent = &mpll_clk;
698 per3_clk.parent = &mpll_clk;
699 per4_clk.parent = &mpll_clk;
1570 700
1571 ssi1_clk[0].parent = &mpll_clk; 701 ssi1_clk.parent = &mpll_clk;
1572 ssi2_clk[0].parent = &mpll_clk; 702 ssi2_clk.parent = &mpll_clk;
1573 703
1574 vpu_clk.parent = &mpll_clk; 704 vpu_clk.parent = &mpll_clk;
1575 } 705 }
@@ -1579,47 +709,47 @@ static void __init probe_mxc_clocks(void)
1579 * must be called very early to get information about the 709 * must be called very early to get information about the
1580 * available clock rate when the timer framework starts 710 * available clock rate when the timer framework starts
1581 */ 711 */
1582int __init mxc_clocks_init(unsigned long fref) 712int __init mx27_clocks_init(unsigned long fref)
1583{ 713{
1584 u32 cscr; 714 u32 cscr = __raw_readl(CCM_CSCR);
1585 struct clk **clkp; 715 int i;
1586 716
1587 external_high_reference = fref; 717 external_high_reference = fref;
1588 718
1589 /* detect clock reference for both system PLL */ 719 /* detect clock reference for both system PLLs */
1590 cscr = CSCR();
1591 if (cscr & CCM_CSCR_MCU) 720 if (cscr & CCM_CSCR_MCU)
1592 mpll_clk.parent = &ckih_clk; 721 mpll_clk.parent = &ckih_clk;
1593 else 722 else
1594 mpll_clk.parent = &ckil_clk; 723 mpll_clk.parent = &fpm_clk;
1595 724
1596 if (cscr & CCM_CSCR_SP) 725 if (cscr & CCM_CSCR_SP)
1597 spll_clk.parent = &ckih_clk; 726 spll_clk.parent = &ckih_clk;
1598 else 727 else
1599 spll_clk.parent = &ckil_clk; 728 spll_clk.parent = &fpm_clk;
1600 729
1601 probe_mxc_clocks(); 730 to2_adjust_clocks();
1602 731
1603 per_clk[0].enable(&per_clk[0]); 732 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1604 gpt1_clk[1].enable(&gpt1_clk[1]); 733 clkdev_add(&lookups[i]);
1605 734
1606 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 735 /* Turn off all clocks we do not need */
1607 clk_register(*clkp); 736 __raw_writel(0, CCM_PCCR0);
737 __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
1608 738
1609 /* Turn off all possible clocks */
1610 __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
1611 __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
1612 CCM_PCCR1);
1613 spll_clk.disable(&spll_clk); 739 spll_clk.disable(&spll_clk);
1614 740
1615 /* This will propagate to all children and init all the clock rates */ 741 /* enable basic clocks */
1616 742 clk_enable(&per1_clk);
1617 clk_enable(&emi_clk);
1618 clk_enable(&gpio_clk); 743 clk_enable(&gpio_clk);
744 clk_enable(&emi_clk);
1619 clk_enable(&iim_clk); 745 clk_enable(&iim_clk);
1620 clk_enable(&gpt1_clk[0]); 746
1621#ifdef CONFIG_DEBUG_LL_CONSOLE 747#ifdef CONFIG_DEBUG_LL_CONSOLE
1622 clk_enable(&uart1_clk[0]); 748 clk_enable(&uart1_clk);
1623#endif 749#endif
750
751 mxc_timer_init(&gpt1_clk);
752
1624 return 0; 753 return 0;
1625} 754}
755
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:33:01 -0500