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-rw-r--r--arch/arm/mach-mx1/clock.c86
-rw-r--r--arch/arm/mach-mx1/devices.c87
-rw-r--r--arch/arm/mach-mx1/generic.c7
-rw-r--r--arch/arm/mach-mx1/mx1ads.c10
-rw-r--r--arch/arm/mach-mx1/scb9328.c16
5 files changed, 80 insertions, 126 deletions
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 0d0f306851d0..d1b588519ad2 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -18,11 +18,14 @@
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/list.h>
21#include <linux/math64.h> 22#include <linux/math64.h>
22#include <linux/err.h> 23#include <linux/err.h>
23#include <linux/clk.h> 24#include <linux/clk.h>
24#include <linux/io.h> 25#include <linux/io.h>
25 26
27#include <asm/clkdev.h>
28
26#include <mach/clock.h> 29#include <mach/clock.h>
27#include <mach/hardware.h> 30#include <mach/hardware.h>
28#include <mach/common.h> 31#include <mach/common.h>
@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
94} 97}
95 98
96static struct clk clk16m = { 99static struct clk clk16m = {
97 .name = "CLK16M",
98 .get_rate = clk16m_get_rate, 100 .get_rate = clk16m_get_rate,
99 .enable = _clk_enable, 101 .enable = _clk_enable,
100 .enable_reg = CCM_CSCR, 102 .enable_reg = CCM_CSCR,
@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
111} 113}
112 114
113static struct clk clk32 = { 115static struct clk clk32 = {
114 .name = "CLK32",
115 .get_rate = clk32_get_rate, 116 .get_rate = clk32_get_rate,
116}; 117};
117 118
@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
121} 122}
122 123
123static struct clk clk32_premult = { 124static struct clk clk32_premult = {
124 .name = "CLK32_premultiplier",
125 .parent = &clk32, 125 .parent = &clk32,
126 .get_rate = clk32_premult_get_rate, 126 .get_rate = clk32_premult_get_rate,
127}; 127};
@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
156} 156}
157 157
158static struct clk prem_clk = { 158static struct clk prem_clk = {
159 .name = "prem_clk",
160 .set_parent = prem_clk_set_parent, 159 .set_parent = prem_clk_set_parent,
161}; 160};
162 161
@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
167} 166}
168 167
169static struct clk system_clk = { 168static struct clk system_clk = {
170 .name = "system_clk",
171 .parent = &prem_clk, 169 .parent = &prem_clk,
172 .get_rate = system_clk_get_rate, 170 .get_rate = system_clk_get_rate,
173}; 171};
@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
179} 177}
180 178
181static struct clk mcu_clk = { 179static struct clk mcu_clk = {
182 .name = "mcu_clk",
183 .parent = &clk32_premult, 180 .parent = &clk32_premult,
184 .get_rate = mcu_clk_get_rate, 181 .get_rate = mcu_clk_get_rate,
185}; 182};
@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
195} 192}
196 193
197static struct clk fclk = { 194static struct clk fclk = {
198 .name = "fclk",
199 .parent = &mcu_clk, 195 .parent = &mcu_clk,
200 .get_rate = fclk_get_rate, 196 .get_rate = fclk_get_rate,
201}; 197};
@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
238} 234}
239 235
240static struct clk hclk = { 236static struct clk hclk = {
241 .name = "hclk",
242 .parent = &system_clk, 237 .parent = &system_clk,
243 .get_rate = hclk_get_rate, 238 .get_rate = hclk_get_rate,
244 .round_rate = hclk_round_rate, 239 .round_rate = hclk_round_rate,
@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
280} 275}
281 276
282static struct clk clk48m = { 277static struct clk clk48m = {
283 .name = "CLK48M",
284 .parent = &system_clk, 278 .parent = &system_clk,
285 .get_rate = clk48m_get_rate, 279 .get_rate = clk48m_get_rate,
286 .round_rate = clk48m_round_rate, 280 .round_rate = clk48m_round_rate,
@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
400 394
401static struct clk perclk[] = { 395static struct clk perclk[] = {
402 { 396 {
403 .name = "perclk",
404 .id = 0, 397 .id = 0,
405 .parent = &system_clk, 398 .parent = &system_clk,
406 .get_rate = perclk1_get_rate, 399 .get_rate = perclk1_get_rate,
407 .round_rate = perclk1_round_rate, 400 .round_rate = perclk1_round_rate,
408 .set_rate = perclk1_set_rate, 401 .set_rate = perclk1_set_rate,
409 }, { 402 }, {
410 .name = "perclk",
411 .id = 1, 403 .id = 1,
412 .parent = &system_clk, 404 .parent = &system_clk,
413 .get_rate = perclk2_get_rate, 405 .get_rate = perclk2_get_rate,
414 .round_rate = perclk2_round_rate, 406 .round_rate = perclk2_round_rate,
415 .set_rate = perclk2_set_rate, 407 .set_rate = perclk2_set_rate,
416 }, { 408 }, {
417 .name = "perclk",
418 .id = 2, 409 .id = 2,
419 .parent = &system_clk, 410 .parent = &system_clk,
420 .get_rate = perclk3_get_rate, 411 .get_rate = perclk3_get_rate,
@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
457} 448}
458 449
459static struct clk clko_clk = { 450static struct clk clko_clk = {
460 .name = "clko_clk",
461 .set_parent = clko_set_parent, 451 .set_parent = clko_set_parent,
462}; 452};
463 453
464static struct clk dma_clk = { 454static struct clk dma_clk = {
465 .name = "dma",
466 .parent = &hclk, 455 .parent = &hclk,
467 .round_rate = _clk_parent_round_rate, 456 .round_rate = _clk_parent_round_rate,
468 .set_rate = _clk_parent_set_rate, 457 .set_rate = _clk_parent_set_rate,
@@ -473,7 +462,6 @@ static struct clk dma_clk = {
473}; 462};
474 463
475static struct clk csi_clk = { 464static struct clk csi_clk = {
476 .name = "csi_clk",
477 .parent = &hclk, 465 .parent = &hclk,
478 .round_rate = _clk_parent_round_rate, 466 .round_rate = _clk_parent_round_rate,
479 .set_rate = _clk_parent_set_rate, 467 .set_rate = _clk_parent_set_rate,
@@ -484,7 +472,6 @@ static struct clk csi_clk = {
484}; 472};
485 473
486static struct clk mma_clk = { 474static struct clk mma_clk = {
487 .name = "mma_clk",
488 .parent = &hclk, 475 .parent = &hclk,
489 .round_rate = _clk_parent_round_rate, 476 .round_rate = _clk_parent_round_rate,
490 .set_rate = _clk_parent_set_rate, 477 .set_rate = _clk_parent_set_rate,
@@ -495,7 +482,6 @@ static struct clk mma_clk = {
495}; 482};
496 483
497static struct clk usbd_clk = { 484static struct clk usbd_clk = {
498 .name = "usbd_clk",
499 .parent = &clk48m, 485 .parent = &clk48m,
500 .round_rate = _clk_parent_round_rate, 486 .round_rate = _clk_parent_round_rate,
501 .set_rate = _clk_parent_set_rate, 487 .set_rate = _clk_parent_set_rate,
@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
506}; 492};
507 493
508static struct clk gpt_clk = { 494static struct clk gpt_clk = {
509 .name = "gpt_clk",
510 .parent = &perclk[0], 495 .parent = &perclk[0],
511 .round_rate = _clk_parent_round_rate, 496 .round_rate = _clk_parent_round_rate,
512 .set_rate = _clk_parent_set_rate, 497 .set_rate = _clk_parent_set_rate,
513}; 498};
514 499
515static struct clk uart_clk = { 500static struct clk uart_clk = {
516 .name = "uart",
517 .parent = &perclk[0], 501 .parent = &perclk[0],
518 .round_rate = _clk_parent_round_rate, 502 .round_rate = _clk_parent_round_rate,
519 .set_rate = _clk_parent_set_rate, 503 .set_rate = _clk_parent_set_rate,
520}; 504};
521 505
522static struct clk i2c_clk = { 506static struct clk i2c_clk = {
523 .name = "i2c_clk",
524 .parent = &hclk, 507 .parent = &hclk,
525 .round_rate = _clk_parent_round_rate, 508 .round_rate = _clk_parent_round_rate,
526 .set_rate = _clk_parent_set_rate, 509 .set_rate = _clk_parent_set_rate,
527}; 510};
528 511
529static struct clk spi_clk = { 512static struct clk spi_clk = {
530 .name = "spi_clk",
531 .parent = &perclk[1], 513 .parent = &perclk[1],
532 .round_rate = _clk_parent_round_rate, 514 .round_rate = _clk_parent_round_rate,
533 .set_rate = _clk_parent_set_rate, 515 .set_rate = _clk_parent_set_rate,
534}; 516};
535 517
536static struct clk sdhc_clk = { 518static struct clk sdhc_clk = {
537 .name = "sdhc_clk",
538 .parent = &perclk[1], 519 .parent = &perclk[1],
539 .round_rate = _clk_parent_round_rate, 520 .round_rate = _clk_parent_round_rate,
540 .set_rate = _clk_parent_set_rate, 521 .set_rate = _clk_parent_set_rate,
541}; 522};
542 523
543static struct clk lcdc_clk = { 524static struct clk lcdc_clk = {
544 .name = "lcdc_clk",
545 .parent = &perclk[1], 525 .parent = &perclk[1],
546 .round_rate = _clk_parent_round_rate, 526 .round_rate = _clk_parent_round_rate,
547 .set_rate = _clk_parent_set_rate, 527 .set_rate = _clk_parent_set_rate,
548}; 528};
549 529
550static struct clk mshc_clk = { 530static struct clk mshc_clk = {
551 .name = "mshc_clk",
552 .parent = &hclk, 531 .parent = &hclk,
553 .round_rate = _clk_parent_round_rate, 532 .round_rate = _clk_parent_round_rate,
554 .set_rate = _clk_parent_set_rate, 533 .set_rate = _clk_parent_set_rate,
555}; 534};
556 535
557static struct clk ssi_clk = { 536static struct clk ssi_clk = {
558 .name = "ssi_clk",
559 .parent = &perclk[2], 537 .parent = &perclk[2],
560 .round_rate = _clk_parent_round_rate, 538 .round_rate = _clk_parent_round_rate,
561 .set_rate = _clk_parent_set_rate, 539 .set_rate = _clk_parent_set_rate,
562}; 540};
563 541
564static struct clk rtc_clk = { 542static struct clk rtc_clk = {
565 .name = "rtc_clk",
566 .parent = &clk32, 543 .parent = &clk32,
567}; 544};
568 545
569static struct clk *mxc_clks[] = { 546#define _REGISTER_CLOCK(d, n, c) \
570 &clk16m, 547 { \
571 &clk32, 548 .dev_id = d, \
572 &clk32_premult, 549 .con_id = n, \
573 &prem_clk, 550 .clk = &c, \
574 &system_clk, 551 },
575 &mcu_clk, 552static struct clk_lookup lookups[] __initdata = {
576 &fclk, 553 _REGISTER_CLOCK(NULL, "dma", dma_clk)
577 &hclk, 554 _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
578 &clk48m, 555 _REGISTER_CLOCK(NULL, "mma", mma_clk)
579 &perclk[0], 556 _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
580 &perclk[1], 557 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
581 &perclk[2], 558 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
582 &clko_clk, 559 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
583 &dma_clk, 560 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
584 &csi_clk, 561 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
585 &mma_clk, 562 _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
586 &usbd_clk, 563 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
587 &gpt_clk, 564 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
588 &uart_clk, 565 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
589 &i2c_clk, 566 _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
590 &spi_clk, 567 _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
591 &sdhc_clk,
592 &lcdc_clk,
593 &mshc_clk,
594 &ssi_clk,
595 &rtc_clk,
596}; 568};
597 569
598int __init mx1_clocks_init(unsigned long fref) 570int __init mx1_clocks_init(unsigned long fref)
599{ 571{
600 struct clk **clkp;
601 unsigned int reg; 572 unsigned int reg;
573 int i;
602 574
603 /* disable clocks we are able to */ 575 /* disable clocks we are able to */
604 __raw_writel(0, SCM_GCCR); 576 __raw_writel(0, SCM_GCCR);
@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
620 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET; 592 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
621 clko_clk.parent = (struct clk *)clko_clocks[reg]; 593 clko_clk.parent = (struct clk *)clko_clocks[reg];
622 594
623 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 595 for (i = 0; i < ARRAY_SIZE(lookups); i++)
624 clk_register(*clkp); 596 clkdev_add(&lookups[i]);
625 597
626 clk_enable(&hclk); 598 clk_enable(&hclk);
627 clk_enable(&fclk); 599 clk_enable(&fclk);
628 600
629 mxc_timer_init(&gpt_clk); 601 mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
630 602
631 return 0; 603 return 0;
632} 604}
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 76d1ffb48079..b6be29d1cb08 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -29,12 +29,11 @@
29#include "devices.h" 29#include "devices.h"
30 30
31static struct resource imx_csi_resources[] = { 31static struct resource imx_csi_resources[] = {
32 [0] = { 32 {
33 .start = 0x00224000, 33 .start = 0x00224000,
34 .end = 0x00224010, 34 .end = 0x00224010,
35 .flags = IORESOURCE_MEM, 35 .flags = IORESOURCE_MEM,
36 }, 36 }, {
37 [1] = {
38 .start = CSI_INT, 37 .start = CSI_INT,
39 .end = CSI_INT, 38 .end = CSI_INT,
40 .flags = IORESOURCE_IRQ, 39 .flags = IORESOURCE_IRQ,
@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = {
55}; 54};
56 55
57static struct resource imx_i2c_resources[] = { 56static struct resource imx_i2c_resources[] = {
58 [0] = { 57 {
59 .start = 0x00217000, 58 .start = 0x00217000,
60 .end = 0x00217010, 59 .end = 0x00217010,
61 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
62 }, 61 }, {
63 [1] = {
64 .start = I2C_INT, 62 .start = I2C_INT,
65 .end = I2C_INT, 63 .end = I2C_INT,
66 .flags = IORESOURCE_IRQ, 64 .flags = IORESOURCE_IRQ,
@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = {
75}; 73};
76 74
77static struct resource imx_uart1_resources[] = { 75static struct resource imx_uart1_resources[] = {
78 [0] = { 76 {
79 .start = UART1_BASE_ADDR, 77 .start = UART1_BASE_ADDR,
80 .end = UART1_BASE_ADDR + 0xD0, 78 .end = UART1_BASE_ADDR + 0xD0,
81 .flags = IORESOURCE_MEM, 79 .flags = IORESOURCE_MEM,
82 }, 80 }, {
83 [1] = {
84 .start = UART1_MINT_RX, 81 .start = UART1_MINT_RX,
85 .end = UART1_MINT_RX, 82 .end = UART1_MINT_RX,
86 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
87 }, 84 }, {
88 [2] = {
89 .start = UART1_MINT_TX, 85 .start = UART1_MINT_TX,
90 .end = UART1_MINT_TX, 86 .end = UART1_MINT_TX,
91 .flags = IORESOURCE_IRQ, 87 .flags = IORESOURCE_IRQ,
92 }, 88 }, {
93 [3] = {
94 .start = UART1_MINT_RTS, 89 .start = UART1_MINT_RTS,
95 .end = UART1_MINT_RTS, 90 .end = UART1_MINT_RTS,
96 .flags = IORESOURCE_IRQ, 91 .flags = IORESOURCE_IRQ,
@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = {
105}; 100};
106 101
107static struct resource imx_uart2_resources[] = { 102static struct resource imx_uart2_resources[] = {
108 [0] = { 103 {
109 .start = UART2_BASE_ADDR, 104 .start = UART2_BASE_ADDR,
110 .end = UART2_BASE_ADDR + 0xD0, 105 .end = UART2_BASE_ADDR + 0xD0,
111 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
112 }, 107 }, {
113 [1] = {
114 .start = UART2_MINT_RX, 108 .start = UART2_MINT_RX,
115 .end = UART2_MINT_RX, 109 .end = UART2_MINT_RX,
116 .flags = IORESOURCE_IRQ, 110 .flags = IORESOURCE_IRQ,
117 }, 111 }, {
118 [2] = {
119 .start = UART2_MINT_TX, 112 .start = UART2_MINT_TX,
120 .end = UART2_MINT_TX, 113 .end = UART2_MINT_TX,
121 .flags = IORESOURCE_IRQ, 114 .flags = IORESOURCE_IRQ,
122 }, 115 }, {
123 [3] = {
124 .start = UART2_MINT_RTS, 116 .start = UART2_MINT_RTS,
125 .end = UART2_MINT_RTS, 117 .end = UART2_MINT_RTS,
126 .flags = IORESOURCE_IRQ, 118 .flags = IORESOURCE_IRQ,
@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = {
135}; 127};
136 128
137static struct resource imx_rtc_resources[] = { 129static struct resource imx_rtc_resources[] = {
138 [0] = { 130 {
139 .start = 0x00204000, 131 .start = 0x00204000,
140 .end = 0x00204024, 132 .end = 0x00204024,
141 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
142 }, 134 }, {
143 [1] = {
144 .start = RTC_INT, 135 .start = RTC_INT,
145 .end = RTC_INT, 136 .end = RTC_INT,
146 .flags = IORESOURCE_IRQ, 137 .flags = IORESOURCE_IRQ,
147 }, 138 }, {
148 [2] = {
149 .start = RTC_SAMINT, 139 .start = RTC_SAMINT,
150 .end = RTC_SAMINT, 140 .end = RTC_SAMINT,
151 .flags = IORESOURCE_IRQ, 141 .flags = IORESOURCE_IRQ,
@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = {
160}; 150};
161 151
162static struct resource imx_wdt_resources[] = { 152static struct resource imx_wdt_resources[] = {
163 [0] = { 153 {
164 .start = 0x00201000, 154 .start = 0x00201000,
165 .end = 0x00201008, 155 .end = 0x00201008,
166 .flags = IORESOURCE_MEM, 156 .flags = IORESOURCE_MEM,
167 }, 157 }, {
168 [1] = {
169 .start = WDT_INT, 158 .start = WDT_INT,
170 .end = WDT_INT, 159 .end = WDT_INT,
171 .flags = IORESOURCE_IRQ, 160 .flags = IORESOURCE_IRQ,
@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = {
180}; 169};
181 170
182static struct resource imx_usb_resources[] = { 171static struct resource imx_usb_resources[] = {
183 [0] = { 172 {
184 .start = 0x00212000, 173 .start = 0x00212000,
185 .end = 0x00212148, 174 .end = 0x00212148,
186 .flags = IORESOURCE_MEM, 175 .flags = IORESOURCE_MEM,
187 }, 176 }, {
188 [1] = {
189 .start = USBD_INT0, 177 .start = USBD_INT0,
190 .end = USBD_INT0, 178 .end = USBD_INT0,
191 .flags = IORESOURCE_IRQ, 179 .flags = IORESOURCE_IRQ,
192 }, 180 }, {
193 [2] = {
194 .start = USBD_INT1, 181 .start = USBD_INT1,
195 .end = USBD_INT1, 182 .end = USBD_INT1,
196 .flags = IORESOURCE_IRQ, 183 .flags = IORESOURCE_IRQ,
197 }, 184 }, {
198 [3] = {
199 .start = USBD_INT2, 185 .start = USBD_INT2,
200 .end = USBD_INT2, 186 .end = USBD_INT2,
201 .flags = IORESOURCE_IRQ, 187 .flags = IORESOURCE_IRQ,
202 }, 188 }, {
203 [4] = {
204 .start = USBD_INT3, 189 .start = USBD_INT3,
205 .end = USBD_INT3, 190 .end = USBD_INT3,
206 .flags = IORESOURCE_IRQ, 191 .flags = IORESOURCE_IRQ,
207 }, 192 }, {
208 [5] = {
209 .start = USBD_INT4, 193 .start = USBD_INT4,
210 .end = USBD_INT4, 194 .end = USBD_INT4,
211 .flags = IORESOURCE_IRQ, 195 .flags = IORESOURCE_IRQ,
212 }, 196 }, {
213 [6] = {
214 .start = USBD_INT5, 197 .start = USBD_INT5,
215 .end = USBD_INT5, 198 .end = USBD_INT5,
216 .flags = IORESOURCE_IRQ, 199 .flags = IORESOURCE_IRQ,
217 }, 200 }, {
218 [7] = {
219 .start = USBD_INT6, 201 .start = USBD_INT6,
220 .end = USBD_INT6, 202 .end = USBD_INT6,
221 .flags = IORESOURCE_IRQ, 203 .flags = IORESOURCE_IRQ,
@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = {
231 213
232/* GPIO port description */ 214/* GPIO port description */
233static struct mxc_gpio_port imx_gpio_ports[] = { 215static struct mxc_gpio_port imx_gpio_ports[] = {
234 [0] = { 216 {
235 .chip.label = "gpio-0", 217 .chip.label = "gpio-0",
236 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), 218 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
237 .irq = GPIO_INT_PORTA, 219 .irq = GPIO_INT_PORTA,
238 .virtual_irq_start = MXC_GPIO_IRQ_START 220 .virtual_irq_start = MXC_GPIO_IRQ_START,
239 }, 221 }, {
240 [1] = {
241 .chip.label = "gpio-1", 222 .chip.label = "gpio-1",
242 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), 223 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
243 .irq = GPIO_INT_PORTB, 224 .irq = GPIO_INT_PORTB,
244 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 225 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
245 }, 226 }, {
246 [2] = {
247 .chip.label = "gpio-2", 227 .chip.label = "gpio-2",
248 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), 228 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
249 .irq = GPIO_INT_PORTC, 229 .irq = GPIO_INT_PORTC,
250 .virtual_irq_start = MXC_GPIO_IRQ_START + 64 230 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
251 }, 231 }, {
252 [3] = {
253 .chip.label = "gpio-3", 232 .chip.label = "gpio-3",
254 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), 233 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
255 .irq = GPIO_INT_PORTD, 234 .irq = GPIO_INT_PORTD,
256 .virtual_irq_start = MXC_GPIO_IRQ_START + 96 235 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
257 } 236 }
258}; 237};
259 238
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 7622c9b38c97..7f9fc1034c08 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = {
41void __init mx1_map_io(void) 41void __init mx1_map_io(void)
42{ 42{
43 mxc_set_cpu_type(MXC_CPU_MX1); 43 mxc_set_cpu_type(MXC_CPU_MX1);
44 mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
44 45
45 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); 46 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
46} 47}
48
49void __init mx1_init_irq(void)
50{
51 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
52}
53
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index e5b0c0a83c3b..30f04e56fafe 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = {
104 104
105static struct i2c_board_info mx1ads_i2c_devices[] = { 105static struct i2c_board_info mx1ads_i2c_devices[] = {
106 { 106 {
107 I2C_BOARD_INFO("pcf857x", 0x22), 107 I2C_BOARD_INFO("pcf8575", 0x22),
108 .type = "pcf8575",
109 .platform_data = &pcf857x_data[0], 108 .platform_data = &pcf857x_data[0],
110 }, { 109 }, {
111 I2C_BOARD_INFO("pcf857x", 0x24), 110 I2C_BOARD_INFO("pcf8575", 0x24),
112 .type = "pcf8575",
113 .platform_data = &pcf857x_data[1], 111 .platform_data = &pcf857x_data[1],
114 }, 112 },
115}; 113};
@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
151 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 149 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
152 .boot_params = PHYS_OFFSET + 0x100, 150 .boot_params = PHYS_OFFSET + 0x100,
153 .map_io = mx1_map_io, 151 .map_io = mx1_map_io,
154 .init_irq = mxc_init_irq, 152 .init_irq = mx1_init_irq,
155 .timer = &mx1ads_timer, 153 .timer = &mx1ads_timer,
156 .init_machine = mx1ads_init, 154 .init_machine = mx1ads_init,
157MACHINE_END 155MACHINE_END
@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
161 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, 159 .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
162 .boot_params = PHYS_OFFSET + 0x100, 160 .boot_params = PHYS_OFFSET + 0x100,
163 .map_io = mx1_map_io, 161 .map_io = mx1_map_io,
164 .init_irq = mxc_init_irq, 162 .init_irq = mx1_init_irq,
165 .timer = &mx1ads_timer, 163 .timer = &mx1ads_timer,
166 .init_machine = mx1ads_init, 164 .init_machine = mx1ads_init,
167MACHINE_END 165MACHINE_END
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
index 20e0b5bcdffc..325d98df6053 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = {
68 * to gain access to address latch registers and the data path. 68 * to gain access to address latch registers and the data path.
69 */ 69 */
70static struct resource dm9000x_resources[] = { 70static struct resource dm9000x_resources[] = {
71 [0] = { 71 {
72 .name = "address area", 72 .name = "address area",
73 .start = IMX_CS5_PHYS, 73 .start = IMX_CS5_PHYS,
74 .end = IMX_CS5_PHYS + 1, 74 .end = IMX_CS5_PHYS + 1,
75 .flags = IORESOURCE_MEM /* address access */ 75 .flags = IORESOURCE_MEM, /* address access */
76 }, 76 }, {
77 [1] = {
78 .name = "data area", 77 .name = "data area",
79 .start = IMX_CS5_PHYS + 4, 78 .start = IMX_CS5_PHYS + 4,
80 .end = IMX_CS5_PHYS + 5, 79 .end = IMX_CS5_PHYS + 5,
81 .flags = IORESOURCE_MEM /* data access */ 80 .flags = IORESOURCE_MEM, /* data access */
82 }, 81 }, {
83 [2] = {
84 .start = IRQ_GPIOC(3), 82 .start = IRQ_GPIOC(3),
85 .end = IRQ_GPIOC(3), 83 .end = IRQ_GPIOC(3),
86 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL 84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
87 }, 85 },
88}; 86};
89 87
@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
154 .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, 152 .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc,
155 .boot_params = 0x08000100, 153 .boot_params = 0x08000100,
156 .map_io = mx1_map_io, 154 .map_io = mx1_map_io,
157 .init_irq = mxc_init_irq, 155 .init_irq = mx1_init_irq,
158 .timer = &scb9328_timer, 156 .timer = &scb9328_timer,
159 .init_machine = scb9328_init, 157 .init_machine = scb9328_init,
160MACHINE_END 158MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 06:29:26 -0500