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-rw-r--r--arch/arm/mach-mx1/clock.c86
1 files changed, 29 insertions, 57 deletions
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 0d0f306851d0..d1b588519ad2 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -18,11 +18,14 @@
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/list.h>
21#include <linux/math64.h> 22#include <linux/math64.h>
22#include <linux/err.h> 23#include <linux/err.h>
23#include <linux/clk.h> 24#include <linux/clk.h>
24#include <linux/io.h> 25#include <linux/io.h>
25 26
27#include <asm/clkdev.h>
28
26#include <mach/clock.h> 29#include <mach/clock.h>
27#include <mach/hardware.h> 30#include <mach/hardware.h>
28#include <mach/common.h> 31#include <mach/common.h>
@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
94} 97}
95 98
96static struct clk clk16m = { 99static struct clk clk16m = {
97 .name = "CLK16M",
98 .get_rate = clk16m_get_rate, 100 .get_rate = clk16m_get_rate,
99 .enable = _clk_enable, 101 .enable = _clk_enable,
100 .enable_reg = CCM_CSCR, 102 .enable_reg = CCM_CSCR,
@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
111} 113}
112 114
113static struct clk clk32 = { 115static struct clk clk32 = {
114 .name = "CLK32",
115 .get_rate = clk32_get_rate, 116 .get_rate = clk32_get_rate,
116}; 117};
117 118
@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
121} 122}
122 123
123static struct clk clk32_premult = { 124static struct clk clk32_premult = {
124 .name = "CLK32_premultiplier",
125 .parent = &clk32, 125 .parent = &clk32,
126 .get_rate = clk32_premult_get_rate, 126 .get_rate = clk32_premult_get_rate,
127}; 127};
@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
156} 156}
157 157
158static struct clk prem_clk = { 158static struct clk prem_clk = {
159 .name = "prem_clk",
160 .set_parent = prem_clk_set_parent, 159 .set_parent = prem_clk_set_parent,
161}; 160};
162 161
@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
167} 166}
168 167
169static struct clk system_clk = { 168static struct clk system_clk = {
170 .name = "system_clk",
171 .parent = &prem_clk, 169 .parent = &prem_clk,
172 .get_rate = system_clk_get_rate, 170 .get_rate = system_clk_get_rate,
173}; 171};
@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
179} 177}
180 178
181static struct clk mcu_clk = { 179static struct clk mcu_clk = {
182 .name = "mcu_clk",
183 .parent = &clk32_premult, 180 .parent = &clk32_premult,
184 .get_rate = mcu_clk_get_rate, 181 .get_rate = mcu_clk_get_rate,
185}; 182};
@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
195} 192}
196 193
197static struct clk fclk = { 194static struct clk fclk = {
198 .name = "fclk",
199 .parent = &mcu_clk, 195 .parent = &mcu_clk,
200 .get_rate = fclk_get_rate, 196 .get_rate = fclk_get_rate,
201}; 197};
@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
238} 234}
239 235
240static struct clk hclk = { 236static struct clk hclk = {
241 .name = "hclk",
242 .parent = &system_clk, 237 .parent = &system_clk,
243 .get_rate = hclk_get_rate, 238 .get_rate = hclk_get_rate,
244 .round_rate = hclk_round_rate, 239 .round_rate = hclk_round_rate,
@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
280} 275}
281 276
282static struct clk clk48m = { 277static struct clk clk48m = {
283 .name = "CLK48M",
284 .parent = &system_clk, 278 .parent = &system_clk,
285 .get_rate = clk48m_get_rate, 279 .get_rate = clk48m_get_rate,
286 .round_rate = clk48m_round_rate, 280 .round_rate = clk48m_round_rate,
@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
400 394
401static struct clk perclk[] = { 395static struct clk perclk[] = {
402 { 396 {
403 .name = "perclk",
404 .id = 0, 397 .id = 0,
405 .parent = &system_clk, 398 .parent = &system_clk,
406 .get_rate = perclk1_get_rate, 399 .get_rate = perclk1_get_rate,
407 .round_rate = perclk1_round_rate, 400 .round_rate = perclk1_round_rate,
408 .set_rate = perclk1_set_rate, 401 .set_rate = perclk1_set_rate,
409 }, { 402 }, {
410 .name = "perclk",
411 .id = 1, 403 .id = 1,
412 .parent = &system_clk, 404 .parent = &system_clk,
413 .get_rate = perclk2_get_rate, 405 .get_rate = perclk2_get_rate,
414 .round_rate = perclk2_round_rate, 406 .round_rate = perclk2_round_rate,
415 .set_rate = perclk2_set_rate, 407 .set_rate = perclk2_set_rate,
416 }, { 408 }, {
417 .name = "perclk",
418 .id = 2, 409 .id = 2,
419 .parent = &system_clk, 410 .parent = &system_clk,
420 .get_rate = perclk3_get_rate, 411 .get_rate = perclk3_get_rate,
@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
457} 448}
458 449
459static struct clk clko_clk = { 450static struct clk clko_clk = {
460 .name = "clko_clk",
461 .set_parent = clko_set_parent, 451 .set_parent = clko_set_parent,
462}; 452};
463 453
464static struct clk dma_clk = { 454static struct clk dma_clk = {
465 .name = "dma",
466 .parent = &hclk, 455 .parent = &hclk,
467 .round_rate = _clk_parent_round_rate, 456 .round_rate = _clk_parent_round_rate,
468 .set_rate = _clk_parent_set_rate, 457 .set_rate = _clk_parent_set_rate,
@@ -473,7 +462,6 @@ static struct clk dma_clk = {
473}; 462};
474 463
475static struct clk csi_clk = { 464static struct clk csi_clk = {
476 .name = "csi_clk",
477 .parent = &hclk, 465 .parent = &hclk,
478 .round_rate = _clk_parent_round_rate, 466 .round_rate = _clk_parent_round_rate,
479 .set_rate = _clk_parent_set_rate, 467 .set_rate = _clk_parent_set_rate,
@@ -484,7 +472,6 @@ static struct clk csi_clk = {
484}; 472};
485 473
486static struct clk mma_clk = { 474static struct clk mma_clk = {
487 .name = "mma_clk",
488 .parent = &hclk, 475 .parent = &hclk,
489 .round_rate = _clk_parent_round_rate, 476 .round_rate = _clk_parent_round_rate,
490 .set_rate = _clk_parent_set_rate, 477 .set_rate = _clk_parent_set_rate,
@@ -495,7 +482,6 @@ static struct clk mma_clk = {
495}; 482};
496 483
497static struct clk usbd_clk = { 484static struct clk usbd_clk = {
498 .name = "usbd_clk",
499 .parent = &clk48m, 485 .parent = &clk48m,
500 .round_rate = _clk_parent_round_rate, 486 .round_rate = _clk_parent_round_rate,
501 .set_rate = _clk_parent_set_rate, 487 .set_rate = _clk_parent_set_rate,
@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
506}; 492};
507 493
508static struct clk gpt_clk = { 494static struct clk gpt_clk = {
509 .name = "gpt_clk",
510 .parent = &perclk[0], 495 .parent = &perclk[0],
511 .round_rate = _clk_parent_round_rate, 496 .round_rate = _clk_parent_round_rate,
512 .set_rate = _clk_parent_set_rate, 497 .set_rate = _clk_parent_set_rate,
513}; 498};
514 499
515static struct clk uart_clk = { 500static struct clk uart_clk = {
516 .name = "uart",
517 .parent = &perclk[0], 501 .parent = &perclk[0],
518 .round_rate = _clk_parent_round_rate, 502 .round_rate = _clk_parent_round_rate,
519 .set_rate = _clk_parent_set_rate, 503 .set_rate = _clk_parent_set_rate,
520}; 504};
521 505
522static struct clk i2c_clk = { 506static struct clk i2c_clk = {
523 .name = "i2c_clk",
524 .parent = &hclk, 507 .parent = &hclk,
525 .round_rate = _clk_parent_round_rate, 508 .round_rate = _clk_parent_round_rate,
526 .set_rate = _clk_parent_set_rate, 509 .set_rate = _clk_parent_set_rate,
527}; 510};
528 511
529static struct clk spi_clk = { 512static struct clk spi_clk = {
530 .name = "spi_clk",
531 .parent = &perclk[1], 513 .parent = &perclk[1],
532 .round_rate = _clk_parent_round_rate, 514 .round_rate = _clk_parent_round_rate,
533 .set_rate = _clk_parent_set_rate, 515 .set_rate = _clk_parent_set_rate,
534}; 516};
535 517
536static struct clk sdhc_clk = { 518static struct clk sdhc_clk = {
537 .name = "sdhc_clk",
538 .parent = &perclk[1], 519 .parent = &perclk[1],
539 .round_rate = _clk_parent_round_rate, 520 .round_rate = _clk_parent_round_rate,
540 .set_rate = _clk_parent_set_rate, 521 .set_rate = _clk_parent_set_rate,
541}; 522};
542 523
543static struct clk lcdc_clk = { 524static struct clk lcdc_clk = {
544 .name = "lcdc_clk",
545 .parent = &perclk[1], 525 .parent = &perclk[1],
546 .round_rate = _clk_parent_round_rate, 526 .round_rate = _clk_parent_round_rate,
547 .set_rate = _clk_parent_set_rate, 527 .set_rate = _clk_parent_set_rate,
548}; 528};
549 529
550static struct clk mshc_clk = { 530static struct clk mshc_clk = {
551 .name = "mshc_clk",
552 .parent = &hclk, 531 .parent = &hclk,
553 .round_rate = _clk_parent_round_rate, 532 .round_rate = _clk_parent_round_rate,
554 .set_rate = _clk_parent_set_rate, 533 .set_rate = _clk_parent_set_rate,
555}; 534};
556 535
557static struct clk ssi_clk = { 536static struct clk ssi_clk = {
558 .name = "ssi_clk",
559 .parent = &perclk[2], 537 .parent = &perclk[2],
560 .round_rate = _clk_parent_round_rate, 538 .round_rate = _clk_parent_round_rate,
561 .set_rate = _clk_parent_set_rate, 539 .set_rate = _clk_parent_set_rate,
562}; 540};
563 541
564static struct clk rtc_clk = { 542static struct clk rtc_clk = {
565 .name = "rtc_clk",
566 .parent = &clk32, 543 .parent = &clk32,
567}; 544};
568 545
569static struct clk *mxc_clks[] = { 546#define _REGISTER_CLOCK(d, n, c) \
570 &clk16m, 547 { \
571 &clk32, 548 .dev_id = d, \
572 &clk32_premult, 549 .con_id = n, \
573 &prem_clk, 550 .clk = &c, \
574 &system_clk, 551 },
575 &mcu_clk, 552static struct clk_lookup lookups[] __initdata = {
576 &fclk, 553 _REGISTER_CLOCK(NULL, "dma", dma_clk)
577 &hclk, 554 _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
578 &clk48m, 555 _REGISTER_CLOCK(NULL, "mma", mma_clk)
579 &perclk[0], 556 _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
580 &perclk[1], 557 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
581 &perclk[2], 558 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
582 &clko_clk, 559 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
583 &dma_clk, 560 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
584 &csi_clk, 561 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
585 &mma_clk, 562 _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
586 &usbd_clk, 563 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
587 &gpt_clk, 564 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
588 &uart_clk, 565 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
589 &i2c_clk, 566 _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
590 &spi_clk, 567 _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
591 &sdhc_clk,
592 &lcdc_clk,
593 &mshc_clk,
594 &ssi_clk,
595 &rtc_clk,
596}; 568};
597 569
598int __init mx1_clocks_init(unsigned long fref) 570int __init mx1_clocks_init(unsigned long fref)
599{ 571{
600 struct clk **clkp;
601 unsigned int reg; 572 unsigned int reg;
573 int i;
602 574
603 /* disable clocks we are able to */ 575 /* disable clocks we are able to */
604 __raw_writel(0, SCM_GCCR); 576 __raw_writel(0, SCM_GCCR);
@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
620 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET; 592 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
621 clko_clk.parent = (struct clk *)clko_clocks[reg]; 593 clko_clk.parent = (struct clk *)clko_clocks[reg];
622 594
623 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 595 for (i = 0; i < ARRAY_SIZE(lookups); i++)
624 clk_register(*clkp); 596 clkdev_add(&lookups[i]);
625 597
626 clk_enable(&hclk); 598 clk_enable(&hclk);
627 clk_enable(&fclk); 599 clk_enable(&fclk);
628 600
629 mxc_timer_init(&gpt_clk); 601 mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
630 602
631 return 0; 603 return 0;
632} 604}