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-rw-r--r--arch/arm/mach-mvebu/coherency.c58
1 files changed, 3 insertions, 55 deletions
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index caa21e9b8cd9..440799ba664a 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -33,6 +33,7 @@
33#include <asm/smp_plat.h> 33#include <asm/smp_plat.h>
34#include <asm/cacheflush.h> 34#include <asm/cacheflush.h>
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36#include <asm/dma-mapping.h>
36#include "coherency.h" 37#include "coherency.h"
37#include "mvebu-soc-id.h" 38#include "mvebu-soc-id.h"
38 39
@@ -76,54 +77,6 @@ int set_cpu_coherent(void)
76 return ll_enable_coherency(); 77 return ll_enable_coherency();
77} 78}
78 79
79static inline void mvebu_hwcc_sync_io_barrier(void)
80{
81 writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
82 while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
83}
84
85static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
86 unsigned long offset, size_t size,
87 enum dma_data_direction dir,
88 struct dma_attrs *attrs)
89{
90 if (dir != DMA_TO_DEVICE)
91 mvebu_hwcc_sync_io_barrier();
92 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
93}
94
95
96static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
97 size_t size, enum dma_data_direction dir,
98 struct dma_attrs *attrs)
99{
100 if (dir != DMA_TO_DEVICE)
101 mvebu_hwcc_sync_io_barrier();
102}
103
104static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
105 size_t size, enum dma_data_direction dir)
106{
107 if (dir != DMA_TO_DEVICE)
108 mvebu_hwcc_sync_io_barrier();
109}
110
111static struct dma_map_ops mvebu_hwcc_dma_ops = {
112 .alloc = arm_dma_alloc,
113 .free = arm_dma_free,
114 .mmap = arm_dma_mmap,
115 .map_page = mvebu_hwcc_dma_map_page,
116 .unmap_page = mvebu_hwcc_dma_unmap_page,
117 .get_sgtable = arm_dma_get_sgtable,
118 .map_sg = arm_dma_map_sg,
119 .unmap_sg = arm_dma_unmap_sg,
120 .sync_single_for_cpu = mvebu_hwcc_dma_sync,
121 .sync_single_for_device = mvebu_hwcc_dma_sync,
122 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
123 .sync_sg_for_device = arm_dma_sync_sg_for_device,
124 .set_dma_mask = arm_dma_set_mask,
125};
126
127static int mvebu_hwcc_notifier(struct notifier_block *nb, 80static int mvebu_hwcc_notifier(struct notifier_block *nb,
128 unsigned long event, void *__dev) 81 unsigned long event, void *__dev)
129{ 82{
@@ -131,7 +84,7 @@ static int mvebu_hwcc_notifier(struct notifier_block *nb,
131 84
132 if (event != BUS_NOTIFY_ADD_DEVICE) 85 if (event != BUS_NOTIFY_ADD_DEVICE)
133 return NOTIFY_DONE; 86 return NOTIFY_DONE;
134 set_dma_ops(dev, &mvebu_hwcc_dma_ops); 87 set_dma_ops(dev, &arm_coherent_dma_ops);
135 88
136 return NOTIFY_OK; 89 return NOTIFY_OK;
137} 90}
@@ -246,14 +199,9 @@ static int coherency_type(void)
246 return type; 199 return type;
247} 200}
248 201
249/*
250 * As a precaution, we currently completely disable hardware I/O
251 * coherency, until enough testing is done with automatic I/O
252 * synchronization barriers to validate that it is a proper solution.
253 */
254int coherency_available(void) 202int coherency_available(void)
255{ 203{
256 return false; 204 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
257} 205}
258 206
259int __init coherency_init(void) 207int __init coherency_init(void)