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-rw-r--r--arch/arm/mach-mvebu/pmsu.c17
1 files changed, 6 insertions, 11 deletions
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 53a55c8520bf..9c819d65b337 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -148,13 +148,13 @@ static void armada_370_xp_cpu_resume(void)
148} 148}
149 149
150/* No locking is needed because we only access per-CPU registers */ 150/* No locking is needed because we only access per-CPU registers */
151void armada_370_xp_pmsu_idle_prepare(bool deepidle) 151int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
152{ 152{
153 unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); 153 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
154 u32 reg; 154 u32 reg;
155 155
156 if (pmsu_mp_base == NULL) 156 if (pmsu_mp_base == NULL)
157 return; 157 return -EINVAL;
158 158
159 /* 159 /*
160 * Adjust the PMSU configuration to wait for WFI signal, enable 160 * Adjust the PMSU configuration to wait for WFI signal, enable
@@ -183,11 +183,6 @@ void armada_370_xp_pmsu_idle_prepare(bool deepidle)
183 reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); 183 reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
184 reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; 184 reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
185 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); 185 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
186}
187
188static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
189{
190 armada_370_xp_pmsu_idle_prepare(deepidle);
191 186
192 v7_exit_coherency_flush(all); 187 v7_exit_coherency_flush(all);
193 188
@@ -220,11 +215,11 @@ static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
220 215
221static int armada_370_xp_cpu_suspend(unsigned long deepidle) 216static int armada_370_xp_cpu_suspend(unsigned long deepidle)
222{ 217{
223 return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend); 218 return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
224} 219}
225 220
226/* No locking is needed because we only access per-CPU registers */ 221/* No locking is needed because we only access per-CPU registers */
227static noinline void armada_370_xp_pmsu_idle_restore(void) 222void armada_370_xp_pmsu_idle_exit(void)
228{ 223{
229 unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); 224 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
230 u32 reg; 225 u32 reg;
@@ -253,7 +248,7 @@ static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
253 unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); 248 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
254 mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume); 249 mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
255 } else if (action == CPU_PM_EXIT) { 250 } else if (action == CPU_PM_EXIT) {
256 armada_370_xp_pmsu_idle_restore(); 251 armada_370_xp_pmsu_idle_exit();
257 } 252 }
258 253
259 return NOTIFY_OK; 254 return NOTIFY_OK;
@@ -263,7 +258,7 @@ static struct notifier_block armada_370_xp_cpu_pm_notifier = {
263 .notifier_call = armada_370_xp_cpu_pm_notify, 258 .notifier_call = armada_370_xp_cpu_pm_notify,
264}; 259};
265 260
266int __init armada_370_xp_cpu_pm_init(void) 261static int __init armada_370_xp_cpu_pm_init(void)
267{ 262{
268 struct device_node *np; 263 struct device_node *np;
269 264