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-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c296
1 files changed, 0 insertions, 296 deletions
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
deleted file mode 100644
index 274ff58271de..000000000000
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/irqdomain.h>
25#include <asm/mach/arch.h>
26#include <asm/exception.h>
27#include <asm/smp_plat.h>
28#include <asm/hardware/cache-l2x0.h>
29
30/* Interrupt Controller Registers Map */
31#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
32#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
33
34#define ARMADA_370_XP_INT_CONTROL (0x00)
35#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
36#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
37#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
38
39#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
40
41#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
42#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
43#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
44
45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
46
47#define ACTIVE_DOORBELLS (8)
48
49static DEFINE_RAW_SPINLOCK(irq_controller_lock);
50
51static void __iomem *per_cpu_int_base;
52static void __iomem *main_int_base;
53static struct irq_domain *armada_370_xp_mpic_domain;
54
55/*
56 * In SMP mode:
57 * For shared global interrupts, mask/unmask global enable bit
58 * For CPU interrtups, mask/unmask the calling CPU's bit
59 */
60static void armada_370_xp_irq_mask(struct irq_data *d)
61{
62#ifdef CONFIG_SMP
63 irq_hw_number_t hwirq = irqd_to_hwirq(d);
64
65 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
66 writel(hwirq, main_int_base +
67 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
68 else
69 writel(hwirq, per_cpu_int_base +
70 ARMADA_370_XP_INT_SET_MASK_OFFS);
71#else
72 writel(irqd_to_hwirq(d),
73 per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
74#endif
75}
76
77static void armada_370_xp_irq_unmask(struct irq_data *d)
78{
79#ifdef CONFIG_SMP
80 irq_hw_number_t hwirq = irqd_to_hwirq(d);
81
82 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
83 writel(hwirq, main_int_base +
84 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
85 else
86 writel(hwirq, per_cpu_int_base +
87 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
88#else
89 writel(irqd_to_hwirq(d),
90 per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
91#endif
92}
93
94#ifdef CONFIG_SMP
95static int armada_xp_set_affinity(struct irq_data *d,
96 const struct cpumask *mask_val, bool force)
97{
98 unsigned long reg;
99 unsigned long new_mask = 0;
100 unsigned long online_mask = 0;
101 unsigned long count = 0;
102 irq_hw_number_t hwirq = irqd_to_hwirq(d);
103 int cpu;
104
105 for_each_cpu(cpu, mask_val) {
106 new_mask |= 1 << cpu_logical_map(cpu);
107 count++;
108 }
109
110 /*
111 * Forbid mutlicore interrupt affinity
112 * This is required since the MPIC HW doesn't limit
113 * several CPUs from acknowledging the same interrupt.
114 */
115 if (count > 1)
116 return -EINVAL;
117
118 for_each_cpu(cpu, cpu_online_mask)
119 online_mask |= 1 << cpu_logical_map(cpu);
120
121 raw_spin_lock(&irq_controller_lock);
122
123 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
124 reg = (reg & (~online_mask)) | new_mask;
125 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
126
127 raw_spin_unlock(&irq_controller_lock);
128
129 return 0;
130}
131#endif
132
133static struct irq_chip armada_370_xp_irq_chip = {
134 .name = "armada_370_xp_irq",
135 .irq_mask = armada_370_xp_irq_mask,
136 .irq_mask_ack = armada_370_xp_irq_mask,
137 .irq_unmask = armada_370_xp_irq_unmask,
138#ifdef CONFIG_SMP
139 .irq_set_affinity = armada_xp_set_affinity,
140#endif
141};
142
143static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
144 unsigned int virq, irq_hw_number_t hw)
145{
146 armada_370_xp_irq_mask(irq_get_irq_data(virq));
147 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
148 irq_set_status_flags(virq, IRQ_LEVEL);
149
150 if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
151 irq_set_percpu_devid(virq);
152 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
153 handle_percpu_devid_irq);
154
155 } else {
156 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
157 handle_level_irq);
158 }
159 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
160
161 return 0;
162}
163
164#ifdef CONFIG_SMP
165void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
166{
167 int cpu;
168 unsigned long map = 0;
169
170 /* Convert our logical CPU mask into a physical one. */
171 for_each_cpu(cpu, mask)
172 map |= 1 << cpu_logical_map(cpu);
173
174 /*
175 * Ensure that stores to Normal memory are visible to the
176 * other CPUs before issuing the IPI.
177 */
178 dsb();
179
180 /* submit softirq */
181 writel((map << 8) | irq, main_int_base +
182 ARMADA_370_XP_SW_TRIG_INT_OFFS);
183}
184
185void armada_xp_mpic_smp_cpu_init(void)
186{
187 /* Clear pending IPIs */
188 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
189
190 /* Enable first 8 IPIs */
191 writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
192 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
193
194 /* Unmask IPI interrupt */
195 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
196}
197#endif /* CONFIG_SMP */
198
199static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
200 .map = armada_370_xp_mpic_irq_map,
201 .xlate = irq_domain_xlate_onecell,
202};
203
204static int __init armada_370_xp_mpic_of_init(struct device_node *node,
205 struct device_node *parent)
206{
207 u32 control;
208
209 main_int_base = of_iomap(node, 0);
210 per_cpu_int_base = of_iomap(node, 1);
211
212 BUG_ON(!main_int_base);
213 BUG_ON(!per_cpu_int_base);
214
215 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
216
217 armada_370_xp_mpic_domain =
218 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
219 &armada_370_xp_mpic_irq_ops, NULL);
220
221 if (!armada_370_xp_mpic_domain)
222 panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
223
224 irq_set_default_host(armada_370_xp_mpic_domain);
225
226#ifdef CONFIG_SMP
227 armada_xp_mpic_smp_cpu_init();
228
229 /*
230 * Set the default affinity from all CPUs to the boot cpu.
231 * This is required since the MPIC doesn't limit several CPUs
232 * from acknowledging the same interrupt.
233 */
234 cpumask_clear(irq_default_affinity);
235 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
236
237#endif
238
239 return 0;
240}
241
242asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
243 *regs)
244{
245 u32 irqstat, irqnr;
246
247 do {
248 irqstat = readl_relaxed(per_cpu_int_base +
249 ARMADA_370_XP_CPU_INTACK_OFFS);
250 irqnr = irqstat & 0x3FF;
251
252 if (irqnr > 1022)
253 break;
254
255 if (irqnr > 0) {
256 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
257 irqnr);
258 handle_IRQ(irqnr, regs);
259 continue;
260 }
261#ifdef CONFIG_SMP
262 /* IPI Handling */
263 if (irqnr == 0) {
264 u32 ipimask, ipinr;
265
266 ipimask = readl_relaxed(per_cpu_int_base +
267 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
268 & 0xFF;
269
270 writel(0x0, per_cpu_int_base +
271 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
272
273 /* Handle all pending doorbells */
274 for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
275 if (ipimask & (0x1 << ipinr))
276 handle_IPI(ipinr, regs);
277 }
278 continue;
279 }
280#endif
281
282 } while (1);
283}
284
285static const struct of_device_id mpic_of_match[] __initconst = {
286 {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
287 {},
288};
289
290void __init armada_370_xp_init_irq(void)
291{
292 of_irq_init(mpic_of_match);
293#ifdef CONFIG_CACHE_L2X0
294 l2x0_of_init(0, ~0UL);
295#endif
296}
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