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Diffstat (limited to 'arch/arm/mach-mvebu/irq-armada-370-xp.c')
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 274ff58271de..6a9195e10579 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -44,6 +44,8 @@
44 44
45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
46 46
47#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
48
47#define ACTIVE_DOORBELLS (8) 49#define ACTIVE_DOORBELLS (8)
48 50
49static DEFINE_RAW_SPINLOCK(irq_controller_lock); 51static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
62#ifdef CONFIG_SMP 64#ifdef CONFIG_SMP
63 irq_hw_number_t hwirq = irqd_to_hwirq(d); 65 irq_hw_number_t hwirq = irqd_to_hwirq(d);
64 66
65 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 67 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
66 writel(hwirq, main_int_base + 68 writel(hwirq, main_int_base +
67 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 69 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
68 else 70 else
@@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
79#ifdef CONFIG_SMP 81#ifdef CONFIG_SMP
80 irq_hw_number_t hwirq = irqd_to_hwirq(d); 82 irq_hw_number_t hwirq = irqd_to_hwirq(d);
81 83
82 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 84 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
83 writel(hwirq, main_int_base + 85 writel(hwirq, main_int_base +
84 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 86 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
85 else 87 else
@@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
147 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 149 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
148 irq_set_status_flags(virq, IRQ_LEVEL); 150 irq_set_status_flags(virq, IRQ_LEVEL);
149 151
150 if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { 152 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
151 irq_set_percpu_devid(virq); 153 irq_set_percpu_devid(virq);
152 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 154 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
153 handle_percpu_devid_irq); 155 handle_percpu_devid_irq);