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-rw-r--r--arch/arm/mach-msm/board-msm8960.c2
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c2
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c10
-rw-r--r--arch/arm/mach-msm/board-trout-mmc.c2
-rw-r--r--arch/arm/mach-msm/gpio-v2.c49
-rw-r--r--arch/arm/mach-msm/gpio.c18
-rw-r--r--arch/arm/mach-msm/irq-vic.c7
-rw-r--r--arch/arm/mach-msm/irq.c7
-rw-r--r--arch/arm/mach-msm/sirc.c11
9 files changed, 53 insertions, 55 deletions
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 1993721d472e..35c7ceeb3f29 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
53 */ 53 */
54 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { 54 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
55 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) 55 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
56 set_irq_handler(i, handle_percpu_irq); 56 irq_set_handler(i, handle_percpu_irq);
57 } 57 }
58} 58}
59 59
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index b3c55f138fce..1163b6fd05d2 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
56 */ 56 */
57 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { 57 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
58 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) 58 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
59 set_irq_handler(i, handle_percpu_irq); 59 irq_set_handler(i, handle_percpu_irq);
60 } 60 }
61} 61}
62 62
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 31117a4499c4..87e1d01edecc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
214{ 214{
215 int i; 215 int i;
216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { 216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
217 set_irq_chip(i, &trout_gpio_irq_chip); 217 irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
218 set_irq_handler(i, handle_edge_irq); 218 handle_edge_irq);
219 set_irq_flags(i, IRQF_VALID); 219 set_irq_flags(i, IRQF_VALID);
220 } 220 }
221 221
222 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) 222 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
223 gpiochip_add(&msm_gpio_banks[i].chip); 223 gpiochip_add(&msm_gpio_banks[i].chip);
224 224
225 set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); 225 irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
226 set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); 226 irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
227 set_irq_wake(MSM_GPIO_TO_INT(17), 1); 227 irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
228 228
229 return 0; 229 return 0;
230} 230}
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
index 44be8464657b..f7a9724788b0 100644
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ b/arch/arm/mach-msm/board-trout-mmc.c
@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
174 if (IS_ERR(vreg_sdslot)) 174 if (IS_ERR(vreg_sdslot))
175 return PTR_ERR(vreg_sdslot); 175 return PTR_ERR(vreg_sdslot);
176 176
177 set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); 177 irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
178 178
179 if (!opt_disable_sdcard) 179 if (!opt_disable_sdcard)
180 msm_add_sdcc(2, &trout_sdslot_data, 180 msm_add_sdcc(2, &trout_sdslot_data,
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 0de19ec74e34..56a964e52ad3 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
230 val, val2); 230 val, val2);
231} 231}
232 232
233static void msm_gpio_irq_ack(unsigned int irq) 233static void msm_gpio_irq_ack(struct irq_data *d)
234{ 234{
235 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 235 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
236 236
237 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); 237 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
238 if (test_bit(gpio, msm_gpio.dual_edge_irqs)) 238 if (test_bit(gpio, msm_gpio.dual_edge_irqs))
239 msm_gpio_update_dual_edge_pos(gpio); 239 msm_gpio_update_dual_edge_pos(gpio);
240} 240}
241 241
242static void msm_gpio_irq_mask(unsigned int irq) 242static void msm_gpio_irq_mask(struct irq_data *d)
243{ 243{
244 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 244 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
245 unsigned long irq_flags; 245 unsigned long irq_flags;
246 246
247 spin_lock_irqsave(&tlmm_lock, irq_flags); 247 spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq)
251 spin_unlock_irqrestore(&tlmm_lock, irq_flags); 251 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
252} 252}
253 253
254static void msm_gpio_irq_unmask(unsigned int irq) 254static void msm_gpio_irq_unmask(struct irq_data *d)
255{ 255{
256 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 256 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
257 unsigned long irq_flags; 257 unsigned long irq_flags;
258 258
259 spin_lock_irqsave(&tlmm_lock, irq_flags); 259 spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq)
263 spin_unlock_irqrestore(&tlmm_lock, irq_flags); 263 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
264} 264}
265 265
266static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) 266static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
267{ 267{
268 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 268 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
269 unsigned long irq_flags; 269 unsigned long irq_flags;
270 uint32_t bits; 270 uint32_t bits;
271 271
@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
275 275
276 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 276 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
277 bits |= BIT(INTR_DECT_CTL); 277 bits |= BIT(INTR_DECT_CTL);
278 irq_desc[irq].handle_irq = handle_edge_irq; 278 __irq_set_handler_locked(d->irq, handle_edge_irq);
279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
280 __set_bit(gpio, msm_gpio.dual_edge_irqs); 280 __set_bit(gpio, msm_gpio.dual_edge_irqs);
281 else 281 else
282 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 282 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
283 } else { 283 } else {
284 bits &= ~BIT(INTR_DECT_CTL); 284 bits &= ~BIT(INTR_DECT_CTL);
285 irq_desc[irq].handle_irq = handle_level_irq; 285 __irq_set_handler_locked(d->irq, handle_level_irq);
286 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 286 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
287 } 287 }
288 288
@@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
309 */ 309 */
310static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) 310static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
311{ 311{
312 struct irq_data *data = irq_desc_get_irq_data(desc);
312 unsigned long i; 313 unsigned long i;
313 314
314 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); 315 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
@@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
318 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, 319 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
319 i)); 320 i));
320 } 321 }
321 desc->chip->ack(irq); 322 data->chip->irq_ack(data);
322} 323}
323 324
324static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) 325static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
325{ 326{
326 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 327 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
327 328
328 if (on) { 329 if (on) {
329 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) 330 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
330 set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); 331 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
331 set_bit(gpio, msm_gpio.wake_irqs); 332 set_bit(gpio, msm_gpio.wake_irqs);
332 } else { 333 } else {
333 clear_bit(gpio, msm_gpio.wake_irqs); 334 clear_bit(gpio, msm_gpio.wake_irqs);
334 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) 335 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
335 set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); 336 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
336 } 337 }
337 338
338 return 0; 339 return 0;
@@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
340 341
341static struct irq_chip msm_gpio_irq_chip = { 342static struct irq_chip msm_gpio_irq_chip = {
342 .name = "msmgpio", 343 .name = "msmgpio",
343 .mask = msm_gpio_irq_mask, 344 .irq_mask = msm_gpio_irq_mask,
344 .unmask = msm_gpio_irq_unmask, 345 .irq_unmask = msm_gpio_irq_unmask,
345 .ack = msm_gpio_irq_ack, 346 .irq_ack = msm_gpio_irq_ack,
346 .set_type = msm_gpio_irq_set_type, 347 .irq_set_type = msm_gpio_irq_set_type,
347 .set_wake = msm_gpio_irq_set_wake, 348 .irq_set_wake = msm_gpio_irq_set_wake,
348}; 349};
349 350
350static int __devinit msm_gpio_probe(struct platform_device *dev) 351static int __devinit msm_gpio_probe(struct platform_device *dev)
@@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
361 362
362 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { 363 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
363 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); 364 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
364 set_irq_chip(irq, &msm_gpio_irq_chip); 365 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
365 set_irq_handler(irq, handle_level_irq); 366 handle_level_irq);
366 set_irq_flags(irq, IRQF_VALID); 367 set_irq_flags(irq, IRQF_VALID);
367 } 368 }
368 369
369 set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, 370 irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
370 msm_summary_irq_handler); 371 msm_summary_irq_handler);
371 return 0; 372 return 0;
372} 373}
@@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
378 if (ret < 0) 379 if (ret < 0)
379 return ret; 380 return ret;
380 381
381 set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); 382 irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
382 383
383 return 0; 384 return 0;
384} 385}
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index 176af9dcb8ee..5ea273b00da8 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
293 val = readl(msm_chip->regs.int_edge); 293 val = readl(msm_chip->regs.int_edge);
294 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 294 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295 writel(val | mask, msm_chip->regs.int_edge); 295 writel(val | mask, msm_chip->regs.int_edge);
296 irq_desc[d->irq].handle_irq = handle_edge_irq; 296 __irq_set_handler_locked(d->irq, handle_edge_irq);
297 } else { 297 } else {
298 writel(val & ~mask, msm_chip->regs.int_edge); 298 writel(val & ~mask, msm_chip->regs.int_edge);
299 irq_desc[d->irq].handle_irq = handle_level_irq; 299 __irq_set_handler_locked(d->irq, handle_level_irq);
300 } 300 }
301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302 msm_chip->both_edge_detect |= mask; 302 msm_chip->both_edge_detect |= mask;
@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void)
354 msm_gpio_chips[j].chip.base + 354 msm_gpio_chips[j].chip.base +
355 msm_gpio_chips[j].chip.ngpio) 355 msm_gpio_chips[j].chip.ngpio)
356 j++; 356 j++;
357 set_irq_chip_data(i, &msm_gpio_chips[j]); 357 irq_set_chip_data(i, &msm_gpio_chips[j]);
358 set_irq_chip(i, &msm_gpio_irq_chip); 358 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
359 set_irq_handler(i, handle_edge_irq); 359 handle_edge_irq);
360 set_irq_flags(i, IRQF_VALID); 360 set_irq_flags(i, IRQF_VALID);
361 } 361 }
362 362
@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void)
366 gpiochip_add(&msm_gpio_chips[i].chip); 366 gpiochip_add(&msm_gpio_chips[i].chip);
367 } 367 }
368 368
369 set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); 369 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370 set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); 370 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371 set_irq_wake(INT_GPIO_GROUP1, 1); 371 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
372 set_irq_wake(INT_GPIO_GROUP2, 2); 372 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
373 return 0; 373 return 0;
374} 374}
375 375
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 68c28bbdc969..1b54f807c2d0 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
313 type = msm_irq_shadow_reg[index].int_type; 313 type = msm_irq_shadow_reg[index].int_type;
314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315 type |= b; 315 type |= b;
316 irq_desc[d->irq].handle_irq = handle_edge_irq; 316 __irq_set_handler_locked(d->irq, handle_edge_irq);
317 } 317 }
318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
319 type &= ~b; 319 type &= ~b;
320 irq_desc[d->irq].handle_irq = handle_level_irq; 320 __irq_set_handler_locked(d->irq, handle_level_irq);
321 } 321 }
322 writel(type, treg); 322 writel(type, treg);
323 msm_irq_shadow_reg[index].int_type = type; 323 msm_irq_shadow_reg[index].int_type = type;
@@ -357,8 +357,7 @@ void __init msm_init_irq(void)
357 writel(3, VIC_INT_MASTEREN); 357 writel(3, VIC_INT_MASTEREN);
358 358
359 for (n = 0; n < NR_MSM_IRQS; n++) { 359 for (n = 0; n < NR_MSM_IRQS; n++) {
360 set_irq_chip(n, &msm_irq_chip); 360 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
361 set_irq_handler(n, handle_level_irq);
362 set_irq_flags(n, IRQF_VALID); 361 set_irq_flags(n, IRQF_VALID);
363 } 362 }
364} 363}
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 0b27d899f40e..ea514be390c6 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
100 100
101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
102 writel(readl(treg) | b, treg); 102 writel(readl(treg) | b, treg);
103 irq_desc[d->irq].handle_irq = handle_edge_irq; 103 __irq_set_handler_locked(d->irq, handle_edge_irq);
104 } 104 }
105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
106 writel(readl(treg) & (~b), treg); 106 writel(readl(treg) & (~b), treg);
107 irq_desc[d->irq].handle_irq = handle_level_irq; 107 __irq_set_handler_locked(d->irq, handle_level_irq);
108 } 108 }
109 return 0; 109 return 0;
110} 110}
@@ -145,8 +145,7 @@ void __init msm_init_irq(void)
145 writel(1, VIC_INT_MASTEREN); 145 writel(1, VIC_INT_MASTEREN);
146 146
147 for (n = 0; n < NR_MSM_IRQS; n++) { 147 for (n = 0; n < NR_MSM_IRQS; n++) {
148 set_irq_chip(n, &msm_irq_chip); 148 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
149 set_irq_handler(n, handle_level_irq);
150 set_irq_flags(n, IRQF_VALID); 149 set_irq_flags(n, IRQF_VALID);
151 } 150 }
152} 151}
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 11b54c7aeb09..689e78c95f38 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
105 val = readl(sirc_regs.int_type); 105 val = readl(sirc_regs.int_type);
106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
107 val |= mask; 107 val |= mask;
108 irq_desc[d->irq].handle_irq = handle_edge_irq; 108 __irq_set_handler_locked(d->irq, handle_edge_irq);
109 } else { 109 } else {
110 val &= ~mask; 110 val &= ~mask;
111 irq_desc[d->irq].handle_irq = handle_level_irq; 111 __irq_set_handler_locked(d->irq, handle_level_irq);
112 } 112 }
113 113
114 writel(val, sirc_regs.int_type); 114 writel(val, sirc_regs.int_type);
@@ -158,15 +158,14 @@ void __init msm_init_sirc(void)
158 wake_enable = 0; 158 wake_enable = 0;
159 159
160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { 160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
161 set_irq_chip(i, &sirc_irq_chip); 161 irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
162 set_irq_handler(i, handle_edge_irq);
163 set_irq_flags(i, IRQF_VALID); 162 set_irq_flags(i, IRQF_VALID);
164 } 163 }
165 164
166 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { 165 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
167 set_irq_chained_handler(sirc_reg_table[i].cascade_irq, 166 irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
168 sirc_irq_handler); 167 sirc_irq_handler);
169 set_irq_wake(sirc_reg_table[i].cascade_irq, 1); 168 irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
170 } 169 }
171 return; 170 return;
172} 171}