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-rw-r--r--arch/arm/mach-msm/Kconfig13
-rw-r--r--arch/arm/mach-msm/Makefile3
-rw-r--r--arch/arm/mach-msm/board-dt-8660.c48
-rw-r--r--arch/arm/mach-msm/board-dt.c (renamed from arch/arm/mach-msm/board-dt-8960.c)17
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8960.h277
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x60.h258
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h5
7 files changed, 18 insertions, 603 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 905efc8cac79..2586c2865874 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,12 +1,12 @@
1if ARCH_MSM 1if ARCH_MSM
2 2
3comment "Qualcomm MSM SoC Type" 3comment "Qualcomm MSM SoC Type"
4 depends on (ARCH_MSM8X60 || ARCH_MSM8960) 4 depends on ARCH_MSM_DT
5 5
6choice 6choice
7 prompt "Qualcomm MSM SoC Type" 7 prompt "Qualcomm MSM SoC Type"
8 default ARCH_MSM7X00A 8 default ARCH_MSM7X00A
9 depends on !(ARCH_MSM8X60 || ARCH_MSM8960) 9 depends on !ARCH_MSM_DT
10 10
11config ARCH_MSM7X00A 11config ARCH_MSM7X00A
12 bool "MSM7x00A / MSM7x01A" 12 bool "MSM7x00A / MSM7x01A"
@@ -49,7 +49,6 @@ config ARCH_MSM8X60
49 select GPIO_MSM_V2 49 select GPIO_MSM_V2
50 select HAVE_SMP 50 select HAVE_SMP
51 select MSM_SCM if SMP 51 select MSM_SCM if SMP
52 select USE_OF
53 52
54config ARCH_MSM8960 53config ARCH_MSM8960
55 bool "MSM8960" 54 bool "MSM8960"
@@ -58,6 +57,11 @@ config ARCH_MSM8960
58 select HAVE_SMP 57 select HAVE_SMP
59 select GPIO_MSM_V2 58 select GPIO_MSM_V2
60 select MSM_SCM if SMP 59 select MSM_SCM if SMP
60
61config ARCH_MSM_DT
62 def_bool y
63 depends on (ARCH_MSM8X60 || ARCH_MSM8960)
64 select SPARSE_IRQ
61 select USE_OF 65 select USE_OF
62 66
63config MSM_HAS_DEBUG_UART_HS 67config MSM_HAS_DEBUG_UART_HS
@@ -68,6 +72,7 @@ config MSM_SOC_REV_A
68 72
69config ARCH_MSM_ARM11 73config ARCH_MSM_ARM11
70 bool 74 bool
75
71config ARCH_MSM_SCORPION 76config ARCH_MSM_SCORPION
72 bool 77 bool
73 78
@@ -75,6 +80,7 @@ config MSM_VIC
75 bool 80 bool
76 81
77menu "Qualcomm MSM Board Type" 82menu "Qualcomm MSM Board Type"
83 depends on !ARCH_MSM_DT
78 84
79config MACH_HALIBUT 85config MACH_HALIBUT
80 depends on ARCH_MSM 86 depends on ARCH_MSM
@@ -122,6 +128,7 @@ config MSM_SMD
122 128
123config MSM_GPIOMUX 129config MSM_GPIOMUX
124 bool 130 bool
131 depends on !ARCH_MSM_DT
125 help 132 help
126 Support for MSM V1 TLMM GPIOMUX architecture. 133 Support for MSM V1 TLMM GPIOMUX architecture.
127 134
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index d872634c2f85..7ed4c1b2bdd2 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
26obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 26obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
27obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 27obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
28obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 28obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
29obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o 29obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
30obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
31obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o 30obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
32obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o 31obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
deleted file mode 100644
index c2946892f5e3..000000000000
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19
20#include "common.h"
21
22static void __init msm8x60_init_late(void)
23{
24 smd_debugfs_init();
25}
26
27static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
28 {}
29};
30
31static void __init msm8x60_dt_init(void)
32{
33 of_platform_populate(NULL, of_default_bus_match_table,
34 msm_auxdata_lookup, NULL);
35}
36
37static const char *msm8x60_fluid_match[] __initdata = {
38 "qcom,msm8660-fluid",
39 "qcom,msm8660-surf",
40 NULL
41};
42
43DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
44 .smp = smp_ops(msm_smp_ops),
45 .init_machine = msm8x60_dt_init,
46 .init_late = msm8x60_init_late,
47 .dt_compat = msm8x60_fluid_match,
48MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt.c
index d4ca52c45111..16e6183ac9f1 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt.c
@@ -1,4 +1,4 @@
1/* Copyright (c) 2012, The Linux Foundation. All rights reserved. 1/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/of.h>
14#include <linux/of_platform.h> 15#include <linux/of_platform.h>
15 16
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
@@ -18,18 +19,14 @@
18 19
19#include "common.h" 20#include "common.h"
20 21
21static void __init msm_dt_init(void) 22static const char * const msm_dt_match[] __initconst = {
22{ 23 "qcom,msm8660-fluid",
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 24 "qcom,msm8660-surf",
24}
25
26static const char * const msm8960_dt_match[] __initconst = {
27 "qcom,msm8960-cdp", 25 "qcom,msm8960-cdp",
28 NULL 26 NULL
29}; 27};
30 28
31DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") 29DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
32 .smp = smp_ops(msm_smp_ops), 30 .smp = smp_ops(msm_smp_ops),
33 .init_machine = msm_dt_init, 31 .dt_compat = msm_dt_match,
34 .dt_compat = msm8960_dt_match,
35MACHINE_END 32MACHINE_END
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
deleted file mode 100644
index 81ab2a6792bd..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ /dev/null
@@ -1,277 +0,0 @@
1/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_8960_H
14#define __ASM_ARCH_MSM_IRQS_8960_H
15
16/* MSM ACPU Interrupt Numbers */
17
18/* 0-15: STI/SGI (software triggered/generated interrupts)
19 16-31: PPI (private peripheral interrupts)
20 32+: SPI (shared peripheral interrupts) */
21
22#define GIC_PPI_START 16
23#define GIC_SPI_START 32
24
25#define INT_VGIC (GIC_PPI_START + 0)
26#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
27#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
28#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
29#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
30#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
31#define AVS_SVICINT (GIC_PPI_START + 6)
32#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
33#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
34#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
35#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
36#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
37#define SC_AVSCPUXUP (GIC_PPI_START + 12)
38#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
39#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
40/* PPI 15 is unused */
41
42#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
43#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
44#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
45#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
46#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
47#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
48#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
49#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
50#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
51#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
52#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
53#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
54#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
55#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
56#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
57#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
58#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
59#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
60#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
61#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
62#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
63#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
64#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
65#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
66#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
67#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
68#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
69#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
70#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
71#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
72#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
73#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
74#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
75#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
76#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
77#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
78#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
79#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
80#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
81#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
82#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
83#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
84#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
85#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
86#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
87#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
88#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
89#define VPE_IRQ (GIC_SPI_START + 47)
90#define VFE_IRQ (GIC_SPI_START + 48)
91#define VCODEC_IRQ (GIC_SPI_START + 49)
92#define TV_ENC_IRQ (GIC_SPI_START + 50)
93#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
94#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
95#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
96#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
97#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
98#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
99#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
100#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
101#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
102#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
103#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
104#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
105#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
106#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
107#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
108#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
109#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
110#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
111#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
112#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
113#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
114#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
115#define ROT_IRQ (GIC_SPI_START + 73)
116#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
117#define MDP_IRQ (GIC_SPI_START + 75)
118#define JPEGD_IRQ (GIC_SPI_START + 76)
119#define JPEG_IRQ (GIC_SPI_START + 77)
120#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
121#define HDMI_IRQ (GIC_SPI_START + 79)
122#define GFX3D_IRQ (GIC_SPI_START + 80)
123#define GFX2D0_IRQ (GIC_SPI_START + 81)
124#define DSI1_IRQ (GIC_SPI_START + 82)
125#define CSI_1_IRQ (GIC_SPI_START + 83)
126#define CSI_0_IRQ (GIC_SPI_START + 84)
127#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
128#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
129#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
130#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
131#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
132#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
133#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
134#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
135#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
136#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
137#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
138#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
139#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
140#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
141#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
142#define USB1_HS_IRQ (GIC_SPI_START + 100)
143#define SDC4_IRQ_0 (GIC_SPI_START + 101)
144#define SDC3_IRQ_0 (GIC_SPI_START + 102)
145#define SDC2_IRQ_0 (GIC_SPI_START + 103)
146#define SDC1_IRQ_0 (GIC_SPI_START + 104)
147#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
148#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
149#define SPS_MTI_0 (GIC_SPI_START + 107)
150#define SPS_MTI_1 (GIC_SPI_START + 108)
151#define SPS_MTI_2 (GIC_SPI_START + 109)
152#define SPS_MTI_3 (GIC_SPI_START + 110)
153#define SPS_MTI_4 (GIC_SPI_START + 111)
154#define SPS_MTI_5 (GIC_SPI_START + 112)
155#define SPS_MTI_6 (GIC_SPI_START + 113)
156#define SPS_MTI_7 (GIC_SPI_START + 114)
157#define SPS_MTI_8 (GIC_SPI_START + 115)
158#define SPS_MTI_9 (GIC_SPI_START + 116)
159#define SPS_MTI_10 (GIC_SPI_START + 117)
160#define SPS_MTI_11 (GIC_SPI_START + 118)
161#define SPS_MTI_12 (GIC_SPI_START + 119)
162#define SPS_MTI_13 (GIC_SPI_START + 120)
163#define SPS_MTI_14 (GIC_SPI_START + 121)
164#define SPS_MTI_15 (GIC_SPI_START + 122)
165#define SPS_MTI_16 (GIC_SPI_START + 123)
166#define SPS_MTI_17 (GIC_SPI_START + 124)
167#define SPS_MTI_18 (GIC_SPI_START + 125)
168#define SPS_MTI_19 (GIC_SPI_START + 126)
169#define SPS_MTI_20 (GIC_SPI_START + 127)
170#define SPS_MTI_21 (GIC_SPI_START + 128)
171#define SPS_MTI_22 (GIC_SPI_START + 129)
172#define SPS_MTI_23 (GIC_SPI_START + 130)
173#define SPS_MTI_24 (GIC_SPI_START + 131)
174#define SPS_MTI_25 (GIC_SPI_START + 132)
175#define SPS_MTI_26 (GIC_SPI_START + 133)
176#define SPS_MTI_27 (GIC_SPI_START + 134)
177#define SPS_MTI_28 (GIC_SPI_START + 135)
178#define SPS_MTI_29 (GIC_SPI_START + 136)
179#define SPS_MTI_30 (GIC_SPI_START + 137)
180#define SPS_MTI_31 (GIC_SPI_START + 138)
181#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
182#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
183#define USB2_IRQ (GIC_SPI_START + 141)
184#define USB1_IRQ (GIC_SPI_START + 142)
185#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
186#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
187#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
188#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
189#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
190#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
191#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
192#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
193#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
194#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
195#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
196#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
197#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
198#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
199#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
200#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
201#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
202#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
203#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
204#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
205#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
206#define TSIF2_IRQ (GIC_SPI_START + 164)
207#define TSIF1_IRQ (GIC_SPI_START + 165)
208#define DSI2_IRQ (GIC_SPI_START + 166)
209#define ISPIF_IRQ (GIC_SPI_START + 167)
210#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
211#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
212#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
213#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
214#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
215#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
216#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
217#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
218#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
219#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
220#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
221#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
222#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
223#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
224#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
225#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
226#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
227#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
228#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
229#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
230#define SDC5_IRQ_0 (GIC_SPI_START + 188)
231#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
232#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
233#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
234#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
235#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
236#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
237#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
238#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
239#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
240#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
241#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
242#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
243#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
244#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
245#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
246#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
247#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
248#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
249#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
250#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
251#define A2_BAM_IRQ (GIC_SPI_START + 209)
252#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
253#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
254#define GFX2D1_IRQ (GIC_SPI_START + 212)
255#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
256#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
257#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
258#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
259#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
260#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
261#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
262#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
263#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
264#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
265#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
266#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
267#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
268#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
269
270/* For now, use the maximum number of interrupts until a pending GIC issue
271 * is sorted out */
272#define NR_MSM_IRQS 1020
273#define NR_BOARD_IRQS 0
274#define NR_GPIO_IRQS 0
275
276#endif
277
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
deleted file mode 100644
index f65841c74c0b..000000000000
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
2 *
3 * This software is licensed under the terms of the GNU General Public
4 * License version 2, as published by the Free Software Foundation, and
5 * may be copied, distributed, and modified under those terms.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
15#define __ASM_ARCH_MSM_IRQS_8X60_H
16
17/* MSM ACPU Interrupt Numbers */
18
19/* 0-15: STI/SGI (software triggered/generated interrupts)
20 * 16-31: PPI (private peripheral interrupts)
21 * 32+: SPI (shared peripheral interrupts)
22 */
23
24#define GIC_PPI_START 16
25#define GIC_SPI_START 32
26
27#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
28#define INT_GP_TIMER_EXP (GIC_PPI_START + 1)
29#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2)
30#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3)
31#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
32#define AVS_SVICINT (GIC_PPI_START + 5)
33#define AVS_SVICINTSWDONE (GIC_PPI_START + 6)
34#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7)
35#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8)
36#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9)
37#define SC_AVSCPUXDOWN (GIC_PPI_START + 10)
38#define SC_AVSCPUXUP (GIC_PPI_START + 11)
39#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12)
40/* PPI 13 to 15 are unused */
41
42
43#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
44#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
45#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2)
46#define NC (GIC_SPI_START + 3)
47#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
48#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
49#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
50#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
51#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
52#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
53#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
54#define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
55#define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
56#define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
57#define PM8058_SEC_IRQ_N (GIC_SPI_START + 14)
58#define PM8901_SEC_IRQ_N (GIC_SPI_START + 15)
59#define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16)
60#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
61#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
62#define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
63#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
64#define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
65#define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
66#define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
67#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
68#define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
69#define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
70#define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27)
71#define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28)
72#define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29)
73#define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30)
74#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
75#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
76#define MARM_FIQ (GIC_SPI_START + 33)
77#define MARM_IRQ (GIC_SPI_START + 34)
78#define MARM_L2CC_IRQ (GIC_SPI_START + 35)
79#define MARM_WDOG_EXPIRED (GIC_SPI_START + 36)
80#define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37)
81#define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38)
82#define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39)
83#define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40)
84#define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41)
85#define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42)
86#define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43)
87#define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44)
88#define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45)
89#define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46)
90#define VPE_IRQ (GIC_SPI_START + 47)
91#define VFE_IRQ (GIC_SPI_START + 48)
92#define VCODEC_IRQ (GIC_SPI_START + 49)
93#define TV_ENC_IRQ (GIC_SPI_START + 50)
94#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
95#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
96#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
97#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
98#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
99#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
100#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
101#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
102#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
103#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
104#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
105#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
106#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
107#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
108#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
109#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
110#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
111#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
112#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
113#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
114#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
115#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
116#define ROT_IRQ (GIC_SPI_START + 73)
117#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
118#define MDP_IRQ (GIC_SPI_START + 75)
119#define JPEGD_IRQ (GIC_SPI_START + 76)
120#define JPEG_IRQ (GIC_SPI_START + 77)
121#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
122#define HDMI_IRQ (GIC_SPI_START + 79)
123#define GFX3D_IRQ (GIC_SPI_START + 80)
124#define GFX2D0_IRQ (GIC_SPI_START + 81)
125#define DSI_IRQ (GIC_SPI_START + 82)
126#define CSI_1_IRQ (GIC_SPI_START + 83)
127#define CSI_0_IRQ (GIC_SPI_START + 84)
128#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
129#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
130#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
131#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
132#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
133#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
134#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
135#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
136#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
137#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
138#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
139#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
140#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
141#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
142#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
143#define USB1_HS_IRQ (GIC_SPI_START + 100)
144#define SDC4_IRQ_0 (GIC_SPI_START + 101)
145#define SDC3_IRQ_0 (GIC_SPI_START + 102)
146#define SDC2_IRQ_0 (GIC_SPI_START + 103)
147#define SDC1_IRQ_0 (GIC_SPI_START + 104)
148#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
149#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
150#define SPS_MTI_0 (GIC_SPI_START + 107)
151#define SPS_MTI_1 (GIC_SPI_START + 108)
152#define SPS_MTI_2 (GIC_SPI_START + 109)
153#define SPS_MTI_3 (GIC_SPI_START + 110)
154#define SPS_MTI_4 (GIC_SPI_START + 111)
155#define SPS_MTI_5 (GIC_SPI_START + 112)
156#define SPS_MTI_6 (GIC_SPI_START + 113)
157#define SPS_MTI_7 (GIC_SPI_START + 114)
158#define SPS_MTI_8 (GIC_SPI_START + 115)
159#define SPS_MTI_9 (GIC_SPI_START + 116)
160#define SPS_MTI_10 (GIC_SPI_START + 117)
161#define SPS_MTI_11 (GIC_SPI_START + 118)
162#define SPS_MTI_12 (GIC_SPI_START + 119)
163#define SPS_MTI_13 (GIC_SPI_START + 120)
164#define SPS_MTI_14 (GIC_SPI_START + 121)
165#define SPS_MTI_15 (GIC_SPI_START + 122)
166#define SPS_MTI_16 (GIC_SPI_START + 123)
167#define SPS_MTI_17 (GIC_SPI_START + 124)
168#define SPS_MTI_18 (GIC_SPI_START + 125)
169#define SPS_MTI_19 (GIC_SPI_START + 126)
170#define SPS_MTI_20 (GIC_SPI_START + 127)
171#define SPS_MTI_21 (GIC_SPI_START + 128)
172#define SPS_MTI_22 (GIC_SPI_START + 129)
173#define SPS_MTI_23 (GIC_SPI_START + 130)
174#define SPS_MTI_24 (GIC_SPI_START + 131)
175#define SPS_MTI_25 (GIC_SPI_START + 132)
176#define SPS_MTI_26 (GIC_SPI_START + 133)
177#define SPS_MTI_27 (GIC_SPI_START + 134)
178#define SPS_MTI_28 (GIC_SPI_START + 135)
179#define SPS_MTI_29 (GIC_SPI_START + 136)
180#define SPS_MTI_30 (GIC_SPI_START + 137)
181#define SPS_MTI_31 (GIC_SPI_START + 138)
182#define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139)
183#define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140)
184#define USB2_IRQ (GIC_SPI_START + 141)
185#define USB1_IRQ (GIC_SPI_START + 142)
186#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
187#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
188#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
189#define INT_UART1DM_IRQ (GIC_SPI_START + 146)
190#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
191#define INT_UART2DM_IRQ (GIC_SPI_START + 148)
192#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
193#define INT_UART3DM_IRQ (GIC_SPI_START + 150)
194#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
195#define INT_UART4DM_IRQ (GIC_SPI_START + 152)
196#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
197#define INT_UART5DM_IRQ (GIC_SPI_START + 154)
198#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
199#define INT_UART6DM_IRQ (GIC_SPI_START + 156)
200#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
201#define INT_UART7DM_IRQ (GIC_SPI_START + 158)
202#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
203#define INT_UART8DM_IRQ (GIC_SPI_START + 160)
204#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
205#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
206#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
207#define TSIF2_IRQ (GIC_SPI_START + 164)
208#define TSIF1_IRQ (GIC_SPI_START + 165)
209#define INT_ADM1_MASTER (GIC_SPI_START + 166)
210#define INT_ADM1_AARM (GIC_SPI_START + 167)
211#define INT_ADM1_SD2 (GIC_SPI_START + 168)
212#define INT_ADM1_SD3 (GIC_SPI_START + 169)
213#define INT_ADM0_MASTER (GIC_SPI_START + 170)
214#define INT_ADM0_AARM (GIC_SPI_START + 171)
215#define INT_ADM0_SD2 (GIC_SPI_START + 172)
216#define INT_ADM0_SD3 (GIC_SPI_START + 173)
217#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
218#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
219#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
220#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
221#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
222#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
223#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
224#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
225#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
226#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
227#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
228#define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185)
229#define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186)
230#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
231#define SDC5_IRQ_0 (GIC_SPI_START + 188)
232#define INT_UART9DM_IRQ (GIC_SPI_START + 189)
233#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
234#define INT_UART10DM_IRQ (GIC_SPI_START + 191)
235#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
236#define INT_UART11DM_IRQ (GIC_SPI_START + 193)
237#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
238#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
239#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
240
241/*SPI 197 to 209 arent used in 8x60*/
242#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
243#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
244
245/*SPI 212 to 216 arent used in 8x60*/
246#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
247#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
248#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
249#define SMPSS_SPARE_4 (GIC_SPI_START + 220)
250#define SMPSS_SPARE_5 (GIC_SPI_START + 221)
251#define SMPSS_SPARE_6 (GIC_SPI_START + 222)
252#define SMPSS_SPARE_7 (GIC_SPI_START + 223)
253
254#define NR_GPIO_IRQS 173
255#define NR_MSM_IRQS 256
256#define NR_BOARD_IRQS 0
257
258#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 3cd78b165abb..164d355c96ea 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -24,11 +24,6 @@
24#elif defined(CONFIG_ARCH_QSD8X50) 24#elif defined(CONFIG_ARCH_QSD8X50)
25#include "irqs-8x50.h" 25#include "irqs-8x50.h"
26#include "sirc.h" 26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM8X60)
28#include "irqs-8x60.h"
29#elif defined(CONFIG_ARCH_MSM8960)
30/* TODO: Make these not generic. */
31#include "irqs-8960.h"
32#elif defined(CONFIG_ARCH_MSM_ARM11) 27#elif defined(CONFIG_ARCH_MSM_ARM11)
33#include "irqs-7x00.h" 28#include "irqs-7x00.h"
34#else 29#else
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 06:01:56 -0500