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-rw-r--r--arch/arm/mach-msm/Makefile9
-rw-r--r--arch/arm/mach-msm/board-dt-8660.c4
-rw-r--r--arch/arm/mach-msm/board-dt-8960.c3
-rw-r--r--arch/arm/mach-msm/board-halibut.c1
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c2
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c1
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c1
-rw-r--r--arch/arm/mach-msm/board-sapphire.c2
-rw-r--r--arch/arm/mach-msm/board-trout.c1
-rw-r--r--arch/arm/mach-msm/board-trout.h2
-rw-r--r--arch/arm/mach-msm/common.h18
-rw-r--r--arch/arm/mach-msm/devices-iommu.c912
-rw-r--r--arch/arm/mach-msm/devices-msm7x30.c2
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c2
-rw-r--r--arch/arm/mach-msm/include/mach/board.h38
-rw-r--r--arch/arm/mach-msm/include/mach/debug-macro.S65
-rw-r--r--arch/arm/mach-msm/include/mach/iommu.h120
-rw-r--r--arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h1865
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h46
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h53
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h17
-rw-r--r--arch/arm/mach-msm/include/mach/uncompress.h63
-rw-r--r--arch/arm/mach-msm/io.c67
-rw-r--r--arch/arm/mach-msm/timer.c141
24 files changed, 120 insertions, 3315 deletions
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index d257ff40e16b..d872634c2f85 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,17 +1,16 @@
1obj-y += io.o timer.o 1obj-y += timer.o
2obj-y += clock.o 2obj-y += clock.o
3 3
4obj-$(CONFIG_MSM_VIC) += irq-vic.o 4obj-$(CONFIG_MSM_VIC) += irq-vic.o
5obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
6 5
7obj-$(CONFIG_ARCH_MSM7X00A) += irq.o 6obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
8obj-$(CONFIG_ARCH_QSD8X50) += sirc.o 7obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
9 8
10obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o 9obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
11 10
12obj-$(CONFIG_ARCH_MSM7X00A) += dma.o 11obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
13obj-$(CONFIG_ARCH_MSM7X30) += dma.o 12obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
14obj-$(CONFIG_ARCH_QSD8X50) += dma.o 13obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
15 14
16obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
17obj-$(CONFIG_MSM_SMD) += last_radio_log.o 16obj-$(CONFIG_MSM_SMD) += last_radio_log.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 492f5cd87b0a..c2946892f5e3 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -15,8 +15,8 @@
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
18 19
19#include <mach/board.h>
20#include "common.h" 20#include "common.h"
21 21
22static void __init msm8x60_init_late(void) 22static void __init msm8x60_init_late(void)
@@ -42,9 +42,7 @@ static const char *msm8x60_fluid_match[] __initdata = {
42 42
43DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") 43DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
44 .smp = smp_ops(msm_smp_ops), 44 .smp = smp_ops(msm_smp_ops),
45 .map_io = msm_map_msm8x60_io,
46 .init_machine = msm8x60_dt_init, 45 .init_machine = msm8x60_dt_init,
47 .init_late = msm8x60_init_late, 46 .init_late = msm8x60_init_late,
48 .init_time = msm_dt_timer_init,
49 .dt_compat = msm8x60_fluid_match, 47 .dt_compat = msm8x60_fluid_match,
50MACHINE_END 48MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index bb5530957c4f..d4ca52c45111 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -14,6 +14,7 @@
14#include <linux/of_platform.h> 14#include <linux/of_platform.h>
15 15
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
17 18
18#include "common.h" 19#include "common.h"
19 20
@@ -29,8 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
29 30
30DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") 31DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
31 .smp = smp_ops(msm_smp_ops), 32 .smp = smp_ops(msm_smp_ops),
32 .map_io = msm_map_msm8960_io,
33 .init_time = msm_dt_timer_init,
34 .init_machine = msm_dt_init, 33 .init_machine = msm_dt_init,
35 .dt_compat = msm8960_dt_match, 34 .dt_compat = msm8960_dt_match,
36MACHINE_END 35MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 803651ad4f62..a77529887cbc 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -29,7 +29,6 @@
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/irqs.h> 31#include <mach/irqs.h>
32#include <mach/board.h>
33#include <mach/msm_iomap.h> 32#include <mach/msm_iomap.h>
34 33
35#include <linux/mtd/nand.h> 34#include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 30c3496db593..7d9981cb400e 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -28,12 +28,12 @@
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/board.h>
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33 32
34#include "board-mahimahi.h" 33#include "board-mahimahi.h"
35#include "devices.h" 34#include "devices.h"
36#include "proc_comm.h" 35#include "proc_comm.h"
36#include "common.h"
37 37
38static uint debug_uart; 38static uint debug_uart;
39 39
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index db3d8c0bc8a4..f9af5a46e8b6 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -30,7 +30,6 @@
30#include <asm/memory.h> 30#include <asm/memory.h>
31#include <asm/setup.h> 31#include <asm/setup.h>
32 32
33#include <mach/board.h>
34#include <mach/msm_iomap.h> 33#include <mach/msm_iomap.h>
35#include <mach/dma.h> 34#include <mach/dma.h>
36 35
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index f14a73d86bc0..5f933bc50783 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -28,7 +28,6 @@
28#include <asm/io.h> 28#include <asm/io.h>
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/board.h>
32#include <mach/irqs.h> 31#include <mach/irqs.h>
33#include <mach/sirc.h> 32#include <mach/sirc.h>
34#include <mach/vreg.h> 33#include <mach/vreg.h>
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 70730111b37c..327605174d63 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -28,7 +28,6 @@
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30#include <mach/vreg.h> 30#include <mach/vreg.h>
31#include <mach/board.h>
32 31
33#include <asm/io.h> 32#include <asm/io.h>
34#include <asm/delay.h> 33#include <asm/delay.h>
@@ -41,6 +40,7 @@
41#include "board-sapphire.h" 40#include "board-sapphire.h"
42#include "proc_comm.h" 41#include "proc_comm.h"
43#include "devices.h" 42#include "devices.h"
43#include "common.h"
44 44
45void msm_init_irq(void); 45void msm_init_irq(void);
46void msm_init_gpio(void); 46void msm_init_gpio(void);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 64a46eb4fc49..ccf6621bc664 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -25,7 +25,6 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/setup.h> 26#include <asm/setup.h>
27 27
28#include <mach/board.h>
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30#include <mach/msm_iomap.h> 29#include <mach/msm_iomap.h>
31 30
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 651851c3e1dd..b2379ede43bc 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -4,7 +4,7 @@
4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H 4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H 5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
6 6
7#include <mach/board.h> 7#include "common.h"
8 8
9#define MSM_SMI_BASE 0x00000000 9#define MSM_SMI_BASE 0x00000000
10#define MSM_SMI_SIZE 0x00800000 10#define MSM_SMI_SIZE 0x00800000
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 421cf7751a80..33c7725adae2 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -14,13 +14,10 @@
14 14
15extern void msm7x01_timer_init(void); 15extern void msm7x01_timer_init(void);
16extern void msm7x30_timer_init(void); 16extern void msm7x30_timer_init(void);
17extern void msm_dt_timer_init(void);
18extern void qsd8x50_timer_init(void); 17extern void qsd8x50_timer_init(void);
19 18
20extern void msm_map_common_io(void); 19extern void msm_map_common_io(void);
21extern void msm_map_msm7x30_io(void); 20extern void msm_map_msm7x30_io(void);
22extern void msm_map_msm8x60_io(void);
23extern void msm_map_msm8960_io(void);
24extern void msm_map_qsd8x50_io(void); 21extern void msm_map_qsd8x50_io(void);
25 22
26extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, 23extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
@@ -29,4 +26,19 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
29extern struct smp_operations msm_smp_ops; 26extern struct smp_operations msm_smp_ops;
30extern void msm_cpu_die(unsigned int cpu); 27extern void msm_cpu_die(unsigned int cpu);
31 28
29struct msm_mmc_platform_data;
30
31extern void msm_add_devices(void);
32extern void msm_init_irq(void);
33extern void msm_init_gpio(void);
34extern int msm_add_sdcc(unsigned int controller,
35 struct msm_mmc_platform_data *plat,
36 unsigned int stat_irq, unsigned long stat_irq_flags);
37
38#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
39extern int smd_debugfs_init(void);
40#else
41static inline int smd_debugfs_init(void) { return 0; }
42#endif
43
32#endif 44#endif
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
deleted file mode 100644
index 0fb7a17df398..000000000000
--- a/arch/arm/mach-msm/devices-iommu.c
+++ /dev/null
@@ -1,912 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/bootmem.h>
21#include <linux/module.h>
22#include <mach/irqs.h>
23#include <mach/iommu.h>
24
25static struct resource msm_iommu_jpegd_resources[] = {
26 {
27 .start = 0x07300000,
28 .end = 0x07300000 + SZ_1M - 1,
29 .name = "physbase",
30 .flags = IORESOURCE_MEM,
31 },
32 {
33 .name = "nonsecure_irq",
34 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
35 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
36 .flags = IORESOURCE_IRQ,
37 },
38 {
39 .name = "secure_irq",
40 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
41 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct resource msm_iommu_vpe_resources[] = {
47 {
48 .start = 0x07400000,
49 .end = 0x07400000 + SZ_1M - 1,
50 .name = "physbase",
51 .flags = IORESOURCE_MEM,
52 },
53 {
54 .name = "nonsecure_irq",
55 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
56 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
57 .flags = IORESOURCE_IRQ,
58 },
59 {
60 .name = "secure_irq",
61 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
62 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
63 .flags = IORESOURCE_IRQ,
64 },
65};
66
67static struct resource msm_iommu_mdp0_resources[] = {
68 {
69 .start = 0x07500000,
70 .end = 0x07500000 + SZ_1M - 1,
71 .name = "physbase",
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "nonsecure_irq",
76 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
77 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
78 .flags = IORESOURCE_IRQ,
79 },
80 {
81 .name = "secure_irq",
82 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
83 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct resource msm_iommu_mdp1_resources[] = {
89 {
90 .start = 0x07600000,
91 .end = 0x07600000 + SZ_1M - 1,
92 .name = "physbase",
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "nonsecure_irq",
97 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
98 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
99 .flags = IORESOURCE_IRQ,
100 },
101 {
102 .name = "secure_irq",
103 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
104 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct resource msm_iommu_rot_resources[] = {
110 {
111 .start = 0x07700000,
112 .end = 0x07700000 + SZ_1M - 1,
113 .name = "physbase",
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "nonsecure_irq",
118 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
119 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
120 .flags = IORESOURCE_IRQ,
121 },
122 {
123 .name = "secure_irq",
124 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
125 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct resource msm_iommu_ijpeg_resources[] = {
131 {
132 .start = 0x07800000,
133 .end = 0x07800000 + SZ_1M - 1,
134 .name = "physbase",
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 .name = "nonsecure_irq",
139 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
140 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
141 .flags = IORESOURCE_IRQ,
142 },
143 {
144 .name = "secure_irq",
145 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
146 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151static struct resource msm_iommu_vfe_resources[] = {
152 {
153 .start = 0x07900000,
154 .end = 0x07900000 + SZ_1M - 1,
155 .name = "physbase",
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 .name = "nonsecure_irq",
160 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
161 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
162 .flags = IORESOURCE_IRQ,
163 },
164 {
165 .name = "secure_irq",
166 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
167 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172static struct resource msm_iommu_vcodec_a_resources[] = {
173 {
174 .start = 0x07A00000,
175 .end = 0x07A00000 + SZ_1M - 1,
176 .name = "physbase",
177 .flags = IORESOURCE_MEM,
178 },
179 {
180 .name = "nonsecure_irq",
181 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
182 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
183 .flags = IORESOURCE_IRQ,
184 },
185 {
186 .name = "secure_irq",
187 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
188 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct resource msm_iommu_vcodec_b_resources[] = {
194 {
195 .start = 0x07B00000,
196 .end = 0x07B00000 + SZ_1M - 1,
197 .name = "physbase",
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .name = "nonsecure_irq",
202 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
203 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
204 .flags = IORESOURCE_IRQ,
205 },
206 {
207 .name = "secure_irq",
208 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
209 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
210 .flags = IORESOURCE_IRQ,
211 },
212};
213
214static struct resource msm_iommu_gfx3d_resources[] = {
215 {
216 .start = 0x07C00000,
217 .end = 0x07C00000 + SZ_1M - 1,
218 .name = "physbase",
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "nonsecure_irq",
223 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
224 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
225 .flags = IORESOURCE_IRQ,
226 },
227 {
228 .name = "secure_irq",
229 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
230 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct resource msm_iommu_gfx2d0_resources[] = {
236 {
237 .start = 0x07D00000,
238 .end = 0x07D00000 + SZ_1M - 1,
239 .name = "physbase",
240 .flags = IORESOURCE_MEM,
241 },
242 {
243 .name = "nonsecure_irq",
244 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
245 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .name = "secure_irq",
250 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
251 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
252 .flags = IORESOURCE_IRQ,
253 },
254};
255
256static struct resource msm_iommu_gfx2d1_resources[] = {
257 {
258 .start = 0x07E00000,
259 .end = 0x07E00000 + SZ_1M - 1,
260 .name = "physbase",
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "nonsecure_irq",
265 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
266 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .name = "secure_irq",
271 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
272 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
273 .flags = IORESOURCE_IRQ,
274 },
275};
276
277static struct platform_device msm_root_iommu_dev = {
278 .name = "msm_iommu",
279 .id = -1,
280};
281
282static struct msm_iommu_dev jpegd_iommu = {
283 .name = "jpegd",
284 .ncb = 2,
285};
286
287static struct msm_iommu_dev vpe_iommu = {
288 .name = "vpe",
289 .ncb = 2,
290};
291
292static struct msm_iommu_dev mdp0_iommu = {
293 .name = "mdp0",
294 .ncb = 2,
295};
296
297static struct msm_iommu_dev mdp1_iommu = {
298 .name = "mdp1",
299 .ncb = 2,
300};
301
302static struct msm_iommu_dev rot_iommu = {
303 .name = "rot",
304 .ncb = 2,
305};
306
307static struct msm_iommu_dev ijpeg_iommu = {
308 .name = "ijpeg",
309 .ncb = 2,
310};
311
312static struct msm_iommu_dev vfe_iommu = {
313 .name = "vfe",
314 .ncb = 2,
315};
316
317static struct msm_iommu_dev vcodec_a_iommu = {
318 .name = "vcodec_a",
319 .ncb = 2,
320};
321
322static struct msm_iommu_dev vcodec_b_iommu = {
323 .name = "vcodec_b",
324 .ncb = 2,
325};
326
327static struct msm_iommu_dev gfx3d_iommu = {
328 .name = "gfx3d",
329 .ncb = 3,
330};
331
332static struct msm_iommu_dev gfx2d0_iommu = {
333 .name = "gfx2d0",
334 .ncb = 2,
335};
336
337static struct msm_iommu_dev gfx2d1_iommu = {
338 .name = "gfx2d1",
339 .ncb = 2,
340};
341
342static struct platform_device msm_device_iommu_jpegd = {
343 .name = "msm_iommu",
344 .id = 0,
345 .dev = {
346 .parent = &msm_root_iommu_dev.dev,
347 },
348 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
349 .resource = msm_iommu_jpegd_resources,
350};
351
352static struct platform_device msm_device_iommu_vpe = {
353 .name = "msm_iommu",
354 .id = 1,
355 .dev = {
356 .parent = &msm_root_iommu_dev.dev,
357 },
358 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
359 .resource = msm_iommu_vpe_resources,
360};
361
362static struct platform_device msm_device_iommu_mdp0 = {
363 .name = "msm_iommu",
364 .id = 2,
365 .dev = {
366 .parent = &msm_root_iommu_dev.dev,
367 },
368 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
369 .resource = msm_iommu_mdp0_resources,
370};
371
372static struct platform_device msm_device_iommu_mdp1 = {
373 .name = "msm_iommu",
374 .id = 3,
375 .dev = {
376 .parent = &msm_root_iommu_dev.dev,
377 },
378 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
379 .resource = msm_iommu_mdp1_resources,
380};
381
382static struct platform_device msm_device_iommu_rot = {
383 .name = "msm_iommu",
384 .id = 4,
385 .dev = {
386 .parent = &msm_root_iommu_dev.dev,
387 },
388 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
389 .resource = msm_iommu_rot_resources,
390};
391
392static struct platform_device msm_device_iommu_ijpeg = {
393 .name = "msm_iommu",
394 .id = 5,
395 .dev = {
396 .parent = &msm_root_iommu_dev.dev,
397 },
398 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
399 .resource = msm_iommu_ijpeg_resources,
400};
401
402static struct platform_device msm_device_iommu_vfe = {
403 .name = "msm_iommu",
404 .id = 6,
405 .dev = {
406 .parent = &msm_root_iommu_dev.dev,
407 },
408 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
409 .resource = msm_iommu_vfe_resources,
410};
411
412static struct platform_device msm_device_iommu_vcodec_a = {
413 .name = "msm_iommu",
414 .id = 7,
415 .dev = {
416 .parent = &msm_root_iommu_dev.dev,
417 },
418 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
419 .resource = msm_iommu_vcodec_a_resources,
420};
421
422static struct platform_device msm_device_iommu_vcodec_b = {
423 .name = "msm_iommu",
424 .id = 8,
425 .dev = {
426 .parent = &msm_root_iommu_dev.dev,
427 },
428 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
429 .resource = msm_iommu_vcodec_b_resources,
430};
431
432static struct platform_device msm_device_iommu_gfx3d = {
433 .name = "msm_iommu",
434 .id = 9,
435 .dev = {
436 .parent = &msm_root_iommu_dev.dev,
437 },
438 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
439 .resource = msm_iommu_gfx3d_resources,
440};
441
442static struct platform_device msm_device_iommu_gfx2d0 = {
443 .name = "msm_iommu",
444 .id = 10,
445 .dev = {
446 .parent = &msm_root_iommu_dev.dev,
447 },
448 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
449 .resource = msm_iommu_gfx2d0_resources,
450};
451
452struct platform_device msm_device_iommu_gfx2d1 = {
453 .name = "msm_iommu",
454 .id = 11,
455 .dev = {
456 .parent = &msm_root_iommu_dev.dev,
457 },
458 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
459 .resource = msm_iommu_gfx2d1_resources,
460};
461
462static struct msm_iommu_ctx_dev jpegd_src_ctx = {
463 .name = "jpegd_src",
464 .num = 0,
465 .mids = {0, -1}
466};
467
468static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
469 .name = "jpegd_dst",
470 .num = 1,
471 .mids = {1, -1}
472};
473
474static struct msm_iommu_ctx_dev vpe_src_ctx = {
475 .name = "vpe_src",
476 .num = 0,
477 .mids = {0, -1}
478};
479
480static struct msm_iommu_ctx_dev vpe_dst_ctx = {
481 .name = "vpe_dst",
482 .num = 1,
483 .mids = {1, -1}
484};
485
486static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
487 .name = "mdp_vg1",
488 .num = 0,
489 .mids = {0, 2, -1}
490};
491
492static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
493 .name = "mdp_rgb1",
494 .num = 1,
495 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
496};
497
498static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
499 .name = "mdp_vg2",
500 .num = 0,
501 .mids = {0, 2, -1}
502};
503
504static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
505 .name = "mdp_rgb2",
506 .num = 1,
507 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
508};
509
510static struct msm_iommu_ctx_dev rot_src_ctx = {
511 .name = "rot_src",
512 .num = 0,
513 .mids = {0, -1}
514};
515
516static struct msm_iommu_ctx_dev rot_dst_ctx = {
517 .name = "rot_dst",
518 .num = 1,
519 .mids = {1, -1}
520};
521
522static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
523 .name = "ijpeg_src",
524 .num = 0,
525 .mids = {0, -1}
526};
527
528static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
529 .name = "ijpeg_dst",
530 .num = 1,
531 .mids = {1, -1}
532};
533
534static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
535 .name = "vfe_imgwr",
536 .num = 0,
537 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
538};
539
540static struct msm_iommu_ctx_dev vfe_misc_ctx = {
541 .name = "vfe_misc",
542 .num = 1,
543 .mids = {0, 1, 9, -1}
544};
545
546static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
547 .name = "vcodec_a_stream",
548 .num = 0,
549 .mids = {2, 5, -1}
550};
551
552static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
553 .name = "vcodec_a_mm1",
554 .num = 1,
555 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
556};
557
558static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
559 .name = "vcodec_b_mm2",
560 .num = 0,
561 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
562};
563
564static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
565 .name = "gfx3d_user",
566 .num = 0,
567 .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
568};
569
570static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
571 .name = "gfx3d_priv",
572 .num = 1,
573 .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
574 31, -1}
575};
576
577static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
578 .name = "gfx2d0_2d0",
579 .num = 0,
580 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
581};
582
583static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
584 .name = "gfx2d1_2d1",
585 .num = 0,
586 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
587};
588
589static struct platform_device msm_device_jpegd_src_ctx = {
590 .name = "msm_iommu_ctx",
591 .id = 0,
592 .dev = {
593 .parent = &msm_device_iommu_jpegd.dev,
594 },
595};
596
597static struct platform_device msm_device_jpegd_dst_ctx = {
598 .name = "msm_iommu_ctx",
599 .id = 1,
600 .dev = {
601 .parent = &msm_device_iommu_jpegd.dev,
602 },
603};
604
605static struct platform_device msm_device_vpe_src_ctx = {
606 .name = "msm_iommu_ctx",
607 .id = 2,
608 .dev = {
609 .parent = &msm_device_iommu_vpe.dev,
610 },
611};
612
613static struct platform_device msm_device_vpe_dst_ctx = {
614 .name = "msm_iommu_ctx",
615 .id = 3,
616 .dev = {
617 .parent = &msm_device_iommu_vpe.dev,
618 },
619};
620
621static struct platform_device msm_device_mdp_vg1_ctx = {
622 .name = "msm_iommu_ctx",
623 .id = 4,
624 .dev = {
625 .parent = &msm_device_iommu_mdp0.dev,
626 },
627};
628
629static struct platform_device msm_device_mdp_rgb1_ctx = {
630 .name = "msm_iommu_ctx",
631 .id = 5,
632 .dev = {
633 .parent = &msm_device_iommu_mdp0.dev,
634 },
635};
636
637static struct platform_device msm_device_mdp_vg2_ctx = {
638 .name = "msm_iommu_ctx",
639 .id = 6,
640 .dev = {
641 .parent = &msm_device_iommu_mdp1.dev,
642 },
643};
644
645static struct platform_device msm_device_mdp_rgb2_ctx = {
646 .name = "msm_iommu_ctx",
647 .id = 7,
648 .dev = {
649 .parent = &msm_device_iommu_mdp1.dev,
650 },
651};
652
653static struct platform_device msm_device_rot_src_ctx = {
654 .name = "msm_iommu_ctx",
655 .id = 8,
656 .dev = {
657 .parent = &msm_device_iommu_rot.dev,
658 },
659};
660
661static struct platform_device msm_device_rot_dst_ctx = {
662 .name = "msm_iommu_ctx",
663 .id = 9,
664 .dev = {
665 .parent = &msm_device_iommu_rot.dev,
666 },
667};
668
669static struct platform_device msm_device_ijpeg_src_ctx = {
670 .name = "msm_iommu_ctx",
671 .id = 10,
672 .dev = {
673 .parent = &msm_device_iommu_ijpeg.dev,
674 },
675};
676
677static struct platform_device msm_device_ijpeg_dst_ctx = {
678 .name = "msm_iommu_ctx",
679 .id = 11,
680 .dev = {
681 .parent = &msm_device_iommu_ijpeg.dev,
682 },
683};
684
685static struct platform_device msm_device_vfe_imgwr_ctx = {
686 .name = "msm_iommu_ctx",
687 .id = 12,
688 .dev = {
689 .parent = &msm_device_iommu_vfe.dev,
690 },
691};
692
693static struct platform_device msm_device_vfe_misc_ctx = {
694 .name = "msm_iommu_ctx",
695 .id = 13,
696 .dev = {
697 .parent = &msm_device_iommu_vfe.dev,
698 },
699};
700
701static struct platform_device msm_device_vcodec_a_stream_ctx = {
702 .name = "msm_iommu_ctx",
703 .id = 14,
704 .dev = {
705 .parent = &msm_device_iommu_vcodec_a.dev,
706 },
707};
708
709static struct platform_device msm_device_vcodec_a_mm1_ctx = {
710 .name = "msm_iommu_ctx",
711 .id = 15,
712 .dev = {
713 .parent = &msm_device_iommu_vcodec_a.dev,
714 },
715};
716
717static struct platform_device msm_device_vcodec_b_mm2_ctx = {
718 .name = "msm_iommu_ctx",
719 .id = 16,
720 .dev = {
721 .parent = &msm_device_iommu_vcodec_b.dev,
722 },
723};
724
725static struct platform_device msm_device_gfx3d_user_ctx = {
726 .name = "msm_iommu_ctx",
727 .id = 17,
728 .dev = {
729 .parent = &msm_device_iommu_gfx3d.dev,
730 },
731};
732
733static struct platform_device msm_device_gfx3d_priv_ctx = {
734 .name = "msm_iommu_ctx",
735 .id = 18,
736 .dev = {
737 .parent = &msm_device_iommu_gfx3d.dev,
738 },
739};
740
741static struct platform_device msm_device_gfx2d0_2d0_ctx = {
742 .name = "msm_iommu_ctx",
743 .id = 19,
744 .dev = {
745 .parent = &msm_device_iommu_gfx2d0.dev,
746 },
747};
748
749static struct platform_device msm_device_gfx2d1_2d1_ctx = {
750 .name = "msm_iommu_ctx",
751 .id = 20,
752 .dev = {
753 .parent = &msm_device_iommu_gfx2d1.dev,
754 },
755};
756
757static struct platform_device *msm_iommu_devs[] = {
758 &msm_device_iommu_jpegd,
759 &msm_device_iommu_vpe,
760 &msm_device_iommu_mdp0,
761 &msm_device_iommu_mdp1,
762 &msm_device_iommu_rot,
763 &msm_device_iommu_ijpeg,
764 &msm_device_iommu_vfe,
765 &msm_device_iommu_vcodec_a,
766 &msm_device_iommu_vcodec_b,
767 &msm_device_iommu_gfx3d,
768 &msm_device_iommu_gfx2d0,
769 &msm_device_iommu_gfx2d1,
770};
771
772static struct msm_iommu_dev *msm_iommu_data[] = {
773 &jpegd_iommu,
774 &vpe_iommu,
775 &mdp0_iommu,
776 &mdp1_iommu,
777 &rot_iommu,
778 &ijpeg_iommu,
779 &vfe_iommu,
780 &vcodec_a_iommu,
781 &vcodec_b_iommu,
782 &gfx3d_iommu,
783 &gfx2d0_iommu,
784 &gfx2d1_iommu,
785};
786
787static struct platform_device *msm_iommu_ctx_devs[] = {
788 &msm_device_jpegd_src_ctx,
789 &msm_device_jpegd_dst_ctx,
790 &msm_device_vpe_src_ctx,
791 &msm_device_vpe_dst_ctx,
792 &msm_device_mdp_vg1_ctx,
793 &msm_device_mdp_rgb1_ctx,
794 &msm_device_mdp_vg2_ctx,
795 &msm_device_mdp_rgb2_ctx,
796 &msm_device_rot_src_ctx,
797 &msm_device_rot_dst_ctx,
798 &msm_device_ijpeg_src_ctx,
799 &msm_device_ijpeg_dst_ctx,
800 &msm_device_vfe_imgwr_ctx,
801 &msm_device_vfe_misc_ctx,
802 &msm_device_vcodec_a_stream_ctx,
803 &msm_device_vcodec_a_mm1_ctx,
804 &msm_device_vcodec_b_mm2_ctx,
805 &msm_device_gfx3d_user_ctx,
806 &msm_device_gfx3d_priv_ctx,
807 &msm_device_gfx2d0_2d0_ctx,
808 &msm_device_gfx2d1_2d1_ctx,
809};
810
811static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
812 &jpegd_src_ctx,
813 &jpegd_dst_ctx,
814 &vpe_src_ctx,
815 &vpe_dst_ctx,
816 &mdp_vg1_ctx,
817 &mdp_rgb1_ctx,
818 &mdp_vg2_ctx,
819 &mdp_rgb2_ctx,
820 &rot_src_ctx,
821 &rot_dst_ctx,
822 &ijpeg_src_ctx,
823 &ijpeg_dst_ctx,
824 &vfe_imgwr_ctx,
825 &vfe_misc_ctx,
826 &vcodec_a_stream_ctx,
827 &vcodec_a_mm1_ctx,
828 &vcodec_b_mm2_ctx,
829 &gfx3d_user_ctx,
830 &gfx3d_priv_ctx,
831 &gfx2d0_2d0_ctx,
832 &gfx2d1_2d1_ctx,
833};
834
835static int __init msm8x60_iommu_init(void)
836{
837 int ret, i;
838
839 ret = platform_device_register(&msm_root_iommu_dev);
840 if (ret != 0) {
841 pr_err("Failed to register root IOMMU device!\n");
842 goto failure;
843 }
844
845 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
846 ret = platform_device_add_data(msm_iommu_devs[i],
847 msm_iommu_data[i],
848 sizeof(struct msm_iommu_dev));
849 if (ret != 0) {
850 pr_err("platform_device_add_data failed, "
851 "i = %d\n", i);
852 goto failure_unwind;
853 }
854
855 ret = platform_device_register(msm_iommu_devs[i]);
856
857 if (ret != 0) {
858 pr_err("platform_device_register iommu failed, "
859 "i = %d\n", i);
860 goto failure_unwind;
861 }
862 }
863
864 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
865 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
866 msm_iommu_ctx_data[i],
867 sizeof(*msm_iommu_ctx_devs[i]));
868 if (ret != 0) {
869 pr_err("platform_device_add_data iommu failed, "
870 "i = %d\n", i);
871 goto failure_unwind2;
872 }
873
874 ret = platform_device_register(msm_iommu_ctx_devs[i]);
875 if (ret != 0) {
876 pr_err("platform_device_register ctx failed, "
877 "i = %d\n", i);
878 goto failure_unwind2;
879 }
880 }
881 return 0;
882
883failure_unwind2:
884 while (--i >= 0)
885 platform_device_unregister(msm_iommu_ctx_devs[i]);
886failure_unwind:
887 while (--i >= 0)
888 platform_device_unregister(msm_iommu_devs[i]);
889
890 platform_device_unregister(&msm_root_iommu_dev);
891failure:
892 return ret;
893}
894
895static void __exit msm8x60_iommu_exit(void)
896{
897 int i;
898
899 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
900 platform_device_unregister(msm_iommu_ctx_devs[i]);
901
902 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
903 platform_device_unregister(msm_iommu_devs[i]);
904
905 platform_device_unregister(&msm_root_iommu_dev);
906}
907
908subsys_initcall(msm8x60_iommu_init);
909module_exit(msm8x60_iommu_exit);
910
911MODULE_LICENSE("GPL v2");
912MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 14e286948f69..c15ea8ab20a7 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -21,10 +21,10 @@
21#include <mach/irqs.h> 21#include <mach/irqs.h>
22#include <mach/msm_iomap.h> 22#include <mach/msm_iomap.h>
23#include <mach/dma.h> 23#include <mach/dma.h>
24#include <mach/board.h>
25 24
26#include "devices.h" 25#include "devices.h"
27#include "smd_private.h" 26#include "smd_private.h"
27#include "common.h"
28 28
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30 30
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2ed89b25d304..9e1e9ce07b1a 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -21,9 +21,9 @@
21#include <mach/irqs.h> 21#include <mach/irqs.h>
22#include <mach/msm_iomap.h> 22#include <mach/msm_iomap.h>
23#include <mach/dma.h> 23#include <mach/dma.h>
24#include <mach/board.h>
25 24
26#include "devices.h" 25#include "devices.h"
26#include "common.h"
27 27
28#include <asm/mach/flash.h> 28#include <asm/mach/flash.h>
29 29
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
deleted file mode 100644
index c34e246a3e07..000000000000
--- a/arch/arm/mach-msm/include/mach/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/mach-msm/include/mach/board.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_BOARD_H
18#define __ASM_ARCH_MSM_BOARD_H
19
20#include <linux/types.h>
21#include <linux/platform_data/mmc-msm_sdcc.h>
22
23/* common init routines for use by arch/arm/mach-msm/board-*.c */
24
25void __init msm_add_devices(void);
26void __init msm_init_irq(void);
27void __init msm_init_gpio(void);
28int __init msm_add_sdcc(unsigned int controller,
29 struct msm_mmc_platform_data *plat,
30 unsigned int stat_irq, unsigned long stat_irq_flags);
31
32#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
33int smd_debugfs_init(void);
34#else
35static inline int smd_debugfs_init(void) { return 0; }
36#endif
37
38#endif
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
deleted file mode 100644
index 0e05f88abcd5..000000000000
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <mach/hardware.h>
19#include <mach/msm_iomap.h>
20
21 .macro addruart, rp, rv, tmp
22#ifdef MSM_DEBUG_UART_PHYS
23 ldr \rp, =MSM_DEBUG_UART_PHYS
24 ldr \rv, =MSM_DEBUG_UART_BASE
25#endif
26 .endm
27
28 .macro senduart, rd, rx
29#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
30 @ Write the 1 character to UARTDM_TF
31 str \rd, [\rx, #0x70]
32#else
33 str \rd, [\rx, #0x0C]
34#endif
35 .endm
36
37 .macro waituart, rd, rx
38#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
39 @ check for TX_EMT in UARTDM_SR
40 ldr \rd, [\rx, #0x08]
41 tst \rd, #0x08
42 bne 1002f
43 @ wait for TXREADY in UARTDM_ISR
441001: ldr \rd, [\rx, #0x14]
45 tst \rd, #0x80
46 beq 1001b
471002:
48 @ Clear TX_READY by writing to the UARTDM_CR register
49 mov \rd, #0x300
50 str \rd, [\rx, #0x10]
51 @ Write 0x1 to NCF register
52 mov \rd, #0x1
53 str \rd, [\rx, #0x40]
54 @ UARTDM reg. Read to induce delay
55 ldr \rd, [\rx, #0x08]
56#else
57 @ wait for TX_READY
581001: ldr \rd, [\rx, #0x08]
59 tst \rd, #0x04
60 beq 1001b
61#endif
62 .endm
63
64 .macro busyuart, rd, rx
65 .endm
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
deleted file mode 100644
index 5c7c955e6d25..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef MSM_IOMMU_H
19#define MSM_IOMMU_H
20
21#include <linux/interrupt.h>
22#include <linux/clk.h>
23
24/* Sharability attributes of MSM IOMMU mappings */
25#define MSM_IOMMU_ATTR_NON_SH 0x0
26#define MSM_IOMMU_ATTR_SH 0x4
27
28/* Cacheability attributes of MSM IOMMU mappings */
29#define MSM_IOMMU_ATTR_NONCACHED 0x0
30#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
31#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
32#define MSM_IOMMU_ATTR_CACHED_WT 0x3
33
34/* Mask for the cache policy attribute */
35#define MSM_IOMMU_CP_MASK 0x03
36
37/* Maximum number of Machine IDs that we are allowing to be mapped to the same
38 * context bank. The number of MIDs mapped to the same CB does not affect
39 * performance, but there is a practical limit on how many distinct MIDs may
40 * be present. These mappings are typically determined at design time and are
41 * not expected to change at run time.
42 */
43#define MAX_NUM_MIDS 32
44
45/**
46 * struct msm_iommu_dev - a single IOMMU hardware instance
47 * name Human-readable name given to this IOMMU HW instance
48 * ncb Number of context banks present on this IOMMU HW instance
49 */
50struct msm_iommu_dev {
51 const char *name;
52 int ncb;
53};
54
55/**
56 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
57 * name Human-readable name given to this context bank
58 * num Index of this context bank within the hardware
59 * mids List of Machine IDs that are to be mapped into this context
60 * bank, terminated by -1. The MID is a set of signals on the
61 * AXI bus that identifies the function associated with a specific
62 * memory request. (See ARM spec).
63 */
64struct msm_iommu_ctx_dev {
65 const char *name;
66 int num;
67 int mids[MAX_NUM_MIDS];
68};
69
70
71/**
72 * struct msm_iommu_drvdata - A single IOMMU hardware instance
73 * @base: IOMMU config port base address (VA)
74 * @ncb The number of contexts on this IOMMU
75 * @irq: Interrupt number
76 * @clk: The bus clock for this IOMMU hardware instance
77 * @pclk: The clock for the IOMMU bus interconnect
78 *
79 * A msm_iommu_drvdata holds the global driver data about a single piece
80 * of an IOMMU hardware instance.
81 */
82struct msm_iommu_drvdata {
83 void __iomem *base;
84 int irq;
85 int ncb;
86 struct clk *clk;
87 struct clk *pclk;
88};
89
90/**
91 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
92 * @num: Hardware context number of this context
93 * @pdev: Platform device associated wit this HW instance
94 * @attached_elm: List element for domains to track which devices are
95 * attached to them
96 *
97 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
98 * within each IOMMU hardware instance
99 */
100struct msm_iommu_ctx_drvdata {
101 int num;
102 struct platform_device *pdev;
103 struct list_head attached_elm;
104};
105
106/*
107 * Look up an IOMMU context device by its context name. NULL if none found.
108 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
109 * their platform devices.
110 */
111struct device *msm_iommu_get_ctx(const char *ctx_name);
112
113/*
114 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
115 * interrupt is not supported in the API yet, but this will print an error
116 * message and dump useful IOMMU registers.
117 */
118irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
119
120#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
deleted file mode 100644
index fc160101dead..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ /dev/null
@@ -1,1865 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
19#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
20
21#define CTX_SHIFT 12
22
23#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
24#define GET_CTX_REG(reg, base, ctx) \
25 (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
26
27#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
28
29#define SET_CTX_REG(reg, base, ctx, val) \
30 writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
31
32/* Wrappers for numbered registers */
33#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
34#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2)))
35
36/* Field wrappers */
37#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
38#define GET_CONTEXT_FIELD(b, c, r, F) \
39 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
40
41#define SET_GLOBAL_FIELD(b, r, F, v) \
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43#define SET_CONTEXT_FIELD(b, c, r, F, v) \
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
45
46#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask))
47
48#define SET_FIELD(addr, mask, shift, v) \
49do { \
50 int t = readl(addr); \
51 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
52} while (0)
53
54
55#define NUM_FL_PTE 4096
56#define NUM_SL_PTE 256
57#define NUM_TEX_CLASS 8
58
59/* First-level page table bits */
60#define FL_BASE_MASK 0xFFFFFC00
61#define FL_TYPE_TABLE (1 << 0)
62#define FL_TYPE_SECT (2 << 0)
63#define FL_SUPERSECTION (1 << 18)
64#define FL_AP_WRITE (1 << 10)
65#define FL_AP_READ (1 << 11)
66#define FL_SHARED (1 << 16)
67#define FL_BUFFERABLE (1 << 2)
68#define FL_CACHEABLE (1 << 3)
69#define FL_TEX0 (1 << 12)
70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
71#define FL_NG (1 << 17)
72
73/* Second-level page table bits */
74#define SL_BASE_MASK_LARGE 0xFFFF0000
75#define SL_BASE_MASK_SMALL 0xFFFFF000
76#define SL_TYPE_LARGE (1 << 0)
77#define SL_TYPE_SMALL (2 << 0)
78#define SL_AP0 (1 << 4)
79#define SL_AP1 (2 << 4)
80#define SL_SHARED (1 << 10)
81#define SL_BUFFERABLE (1 << 2)
82#define SL_CACHEABLE (1 << 3)
83#define SL_TEX0 (1 << 6)
84#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
85#define SL_NG (1 << 11)
86
87/* Memory type and cache policy attributes */
88#define MT_SO 0
89#define MT_DEV 1
90#define MT_NORMAL 2
91#define CP_NONCACHED 0
92#define CP_WB_WA 1
93#define CP_WT 2
94#define CP_WB_NWA 3
95
96/* Global register setters / getters */
97#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
98#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
99#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
100#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
101#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
102#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
103#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
104#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
105#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
106#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
107#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
108#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
109#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
110#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
111#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
112#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
113
114#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
115#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b))
116#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b))
117#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b))
118#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b))
119#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b))
120#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
121#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b))
122#define GET_CR(b) GET_GLOBAL_REG(CR, (b))
123#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b))
124#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b))
125#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b))
126#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b))
127#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b))
128#define GET_REV(b) GET_GLOBAL_REG(REV, (b))
129#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
130#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b))
131
132
133/* Context register setters/getters */
134#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
135#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
136#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
137#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
138#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
139#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
140#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
141#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
142#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
143#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
144#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
145#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
146#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
147#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
148#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
149#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
150#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
151#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
152#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
153#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
154#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
155#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
156#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
157#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
158#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
159#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
160#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
161#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
162
163#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c))
164#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c))
165#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c))
166#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c))
167#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c))
168#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c))
169#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c))
170#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
171#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c))
172#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c))
173#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c))
174#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c))
175#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c))
176#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c))
177#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c))
178#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c))
179#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c))
180#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c))
181#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c))
182#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c))
183#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c))
184#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c))
185#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c))
186#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c))
187#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c))
188#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c))
189#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c))
190#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c))
191
192
193/* Global field setters / getters */
194/* Global Field Setters: */
195/* CBACR_N */
196#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
197#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
198#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
199#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
200#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
201
202
203/* M2VCBR_N */
204#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
205#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
206#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
207#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
208#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
209#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
210#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
211#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
212#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
213#define SET_BPMEMTYPE(b, n, v) \
214 SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
215
216
217/* CR */
218#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
219#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
220#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
221#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
222#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
223#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
224#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
225#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
226#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
227#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
228
229
230/* ESR */
231#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
232#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
233#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
234
235
236/* ESYNR0 */
237#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
238#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
239#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
240#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
241#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
242
243
244/* ESYNR1 */
245#define SET_ESYNR1_AMEMTYPE(b, v) \
246 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
247#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
248#define SET_ESYNR1_AINNERSHARED(b, v) \
249 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
250#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
251#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
252#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
253#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
254#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
255#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
256#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
257#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
258#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
259#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
260#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
261#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
262
263
264/* TESTBUSCR */
265#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
266#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
267#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
268#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
269#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
270#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
271#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
272#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
273#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
274
275
276/* TLBIVMID */
277#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
278
279
280/* TLBRSW */
281#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
282#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
283
284
285/* TLBTR0 */
286#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
287#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
288#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
289#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
290#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
291#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
292#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
293#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
294#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
295#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
296#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
297
298
299/* TLBTR1 */
300#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
301#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
302
303
304/* TLBTR2 */
305#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
306#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
307#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
308#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
309#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
310
311
312/* Global Field Getters */
313/* CBACR_N */
314#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
315#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
316#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
317#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
318#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
319
320
321/* M2VCBR_N */
322#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
323#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
324#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
325#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
326#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
327#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
328#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
329#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
330#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
331#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
332
333
334/* CR */
335#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE)
336#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE)
337#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE)
338#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE)
339#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD)
340#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD)
341#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
342#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
343#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
344#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME)
345
346
347/* ESR */
348#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
349#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
350#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
351
352
353/* ESYNR0 */
354#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
355#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
356#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
357#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
358#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
359
360
361/* ESYNR1 */
362#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
363#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
364#define GET_ESYNR1_AINNERSHARED(b) \
365 GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
366#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
367#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
368#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
369#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
370#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
371#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
372#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
373#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
374#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
375#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
376#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
377#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
378
379
380/* IDR */
381#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
382#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
383#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
384#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
385#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
386#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
387
388
389/* REV */
390#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR)
391#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR)
392
393
394/* TESTBUSCR */
395#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
396#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
397#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
398#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
399#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
400#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
401#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
402#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
403#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
404
405
406/* TLBIVMID */
407#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
408
409
410/* TLBTR0 */
411#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR)
412#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW)
413#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR)
414#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW)
415#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN)
416#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
417#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH)
418#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH)
419#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT)
420#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
421#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
422
423
424/* TLBTR1 */
425#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
426#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
427
428
429/* TLBTR2 */
430#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
431#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
432#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
433#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
434#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
435
436
437/* Context Register setters / getters */
438/* Context Register setters */
439/* ACTLR */
440#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
441#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
442#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
443#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
444#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
445#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
446#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
447#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
448#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
449#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
450#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
451#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
452#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
453#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
454#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
455#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
456
457
458/* BFBCR */
459#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
460#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
461#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
462#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
463#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
464
465
466/* CONTEXTIDR */
467#define SET_CONTEXTIDR_ASID(b, c, v) \
468 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
469#define SET_CONTEXTIDR_PROCID(b, c, v) \
470 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
471
472
473/* FSR */
474#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
475#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
476#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
477#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
478#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
479#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
480#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
481#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
482#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
483#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
484
485
486/* FSYNR0 */
487#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
488#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
489#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
490#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
491
492
493/* FSYNR1 */
494#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
495#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
496#define SET_AINNERSHARED(b, c, v) \
497 SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
498#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
499#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
500#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
501#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
502#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
503#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
504#define SET_FSYNR1_ASIZE(b, c, v) \
505 SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
506#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
507#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
508
509
510/* NMRR */
511#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
512#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
513#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
514#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
515#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
516#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
517#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
518#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
519#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
520#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
521#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
522#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
523#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
524#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
525#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
526#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
527
528
529/* PAR */
530#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
531
532#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
533#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
534#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
535#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
536#define SET_FAULT_HTWDEEF(b, c, v) \
537 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
538#define SET_FAULT_HTWSEEF(b, c, v) \
539 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
540#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
541#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
542#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
543
544#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
545#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
546#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
547#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
548#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
549#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
550
551
552/* PRRR */
553#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
554#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
555#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
556#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
557#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
558#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
559#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
560#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
561#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
562#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
563#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
564#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
565#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
566#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
567#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
568#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
569#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
570#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
571#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
572#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
573
574
575/* RESUME */
576#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
577
578
579/* SCTLR */
580#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
581#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
582#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
583#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
584#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
585#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
586
587
588/* TLBLKCR */
589#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
590#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
591 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
592#define SET_TLBIASIDCFG(b, c, v) \
593 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
594#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
595#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
596#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
597
598
599/* TTBCR */
600#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
601#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
602#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
603
604
605/* TTBR0 */
606#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
607#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
608#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
609#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
610#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
611#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
612
613
614/* TTBR1 */
615#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
616#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
617#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
618#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
619#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
620#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
621
622
623/* V2PSR */
624#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
625#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
626
627
628/* Context Register getters */
629/* ACTLR */
630#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
631#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
632#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
633#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
634#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
635#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
636#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
637#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
638#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
639#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
640#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
641#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
642#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
643#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
644#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
645#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
646
647/* BFBCR */
648#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
649#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
650#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
651#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
652#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
653
654
655/* CONTEXTIDR */
656#define GET_CONTEXTIDR_ASID(b, c) \
657 GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
658#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
659
660
661/* FSR */
662#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF)
663#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF)
664#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF)
665#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
666#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
667#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
668#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF)
669#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL)
670#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
671#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI)
672
673
674/* FSYNR0 */
675#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
676#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
677#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
678#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
679
680
681/* FSYNR1 */
682#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
683#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
684#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
685#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
686#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
687#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
688#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
689#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
690#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
691#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
692#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
693#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
694
695
696/* NMRR */
697#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
698#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
699#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
700#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
701#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
702#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
703#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
704#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
705#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
706#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
707#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
708#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
709#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
710#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
711#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
712#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
713#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
714#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \
715 ((n) * 2 + 16))
716
717/* PAR */
718#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
719
720#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
721#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
722#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
723#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
724#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
725#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
726#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
727#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
728#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
729
730#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
731#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
732#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
733#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
734#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
735#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
736
737
738/* PRRR */
739#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
740#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
741#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
742#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
743#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
744#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
745#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
746#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
747#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
748#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
749#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
750#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
751#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
752#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
753#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
754#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
755#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
756#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
757#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
758#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
759#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
760#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
761
762
763/* RESUME */
764#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR)
765
766
767/* SCTLR */
768#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
769#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
770#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
771#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
772#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE)
773#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
774
775
776/* TLBLKCR */
777#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
778#define GET_TLBLCKR_TLBIALLCFG(b, c) \
779 GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
780#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
781#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
782#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
783#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
784
785
786/* TTBCR */
787#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N)
788#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
789#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
790
791
792/* TTBR0 */
793#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
794#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
795#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
796#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
797#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
798#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
799
800
801/* TTBR1 */
802#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
803#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
804#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
805#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
806#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
807#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
808
809
810/* V2PSR */
811#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
812#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
813
814
815/* Global Registers */
816#define M2VCBR_N (0xFF000)
817#define CBACR_N (0xFF800)
818#define TLBRSW (0xFFE00)
819#define TLBTR0 (0xFFE80)
820#define TLBTR1 (0xFFE84)
821#define TLBTR2 (0xFFE88)
822#define TESTBUSCR (0xFFE8C)
823#define GLOBAL_TLBIALL (0xFFF00)
824#define TLBIVMID (0xFFF04)
825#define CR (0xFFF80)
826#define EAR (0xFFF84)
827#define ESR (0xFFF88)
828#define ESRRESTORE (0xFFF8C)
829#define ESYNR0 (0xFFF90)
830#define ESYNR1 (0xFFF94)
831#define REV (0xFFFF4)
832#define IDR (0xFFFF8)
833#define RPU_ACR (0xFFFFC)
834
835
836/* Context Bank Registers */
837#define SCTLR (0x000)
838#define ACTLR (0x004)
839#define CONTEXTIDR (0x008)
840#define TTBR0 (0x010)
841#define TTBR1 (0x014)
842#define TTBCR (0x018)
843#define PAR (0x01C)
844#define FSR (0x020)
845#define FSRRESTORE (0x024)
846#define FAR (0x028)
847#define FSYNR0 (0x02C)
848#define FSYNR1 (0x030)
849#define PRRR (0x034)
850#define NMRR (0x038)
851#define TLBLCKR (0x03C)
852#define V2PSR (0x040)
853#define TLBFLPTER (0x044)
854#define TLBSLPTER (0x048)
855#define BFBCR (0x04C)
856#define CTX_TLBIALL (0x800)
857#define TLBIASID (0x804)
858#define TLBIVA (0x808)
859#define TLBIVAA (0x80C)
860#define V2PPR (0x810)
861#define V2PPW (0x814)
862#define V2PUR (0x818)
863#define V2PUW (0x81C)
864#define RESUME (0x820)
865
866
867/* Global Register Fields */
868/* CBACRn */
869#define RWVMID (RWVMID_MASK << RWVMID_SHIFT)
870#define RWE (RWE_MASK << RWE_SHIFT)
871#define RWGE (RWGE_MASK << RWGE_SHIFT)
872#define CBVMID (CBVMID_MASK << CBVMID_SHIFT)
873#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT)
874
875
876/* CR */
877#define RPUE (RPUE_MASK << RPUE_SHIFT)
878#define RPUERE (RPUERE_MASK << RPUERE_SHIFT)
879#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT)
880#define DCDEE (DCDEE_MASK << DCDEE_SHIFT)
881#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT)
882#define STALLD (STALLD_MASK << STALLD_SHIFT)
883#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT)
884#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
885#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT)
886#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT)
887
888
889/* ESR */
890#define CFG (CFG_MASK << CFG_SHIFT)
891#define BYPASS (BYPASS_MASK << BYPASS_SHIFT)
892#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT)
893
894
895/* ESYNR0 */
896#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT)
897#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT)
898#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT)
899#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
900#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT)
901
902
903/* ESYNR1 */
904#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT)
905#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT)
906#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \
907 ESYNR1_AINNERSHARED_SHIFT)
908#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT)
909#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT)
910#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT)
911#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT)
912#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT)
913#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT)
914#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT)
915#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT)
916#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT)
917#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT)
918#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT)
919#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT)
920
921
922/* IDR */
923#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT)
924#define HTW (HTW_MASK << HTW_SHIFT)
925#define HUM (HUM_MASK << HUM_SHIFT)
926#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT)
927#define NCB (NCB_MASK << NCB_SHIFT)
928#define NIRPT (NIRPT_MASK << NIRPT_SHIFT)
929
930
931/* M2VCBRn */
932#define VMID (VMID_MASK << VMID_SHIFT)
933#define CBNDX (CBNDX_MASK << CBNDX_SHIFT)
934#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT)
935#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT)
936#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT)
937#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT)
938#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT)
939#define NSCFG (NSCFG_MASK << NSCFG_SHIFT)
940#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT)
941#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT)
942
943
944/* REV */
945#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT)
946#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT)
947
948
949/* TESTBUSCR */
950#define TBE (TBE_MASK << TBE_SHIFT)
951#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT)
952#define WGSEL (WGSEL_MASK << WGSEL_SHIFT)
953#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT)
954#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT)
955#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT)
956#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT)
957#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT)
958#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT)
959
960
961/* TLBIVMID */
962#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
963
964
965/* TLBRSW */
966#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
967#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT)
968
969
970/* TLBTR0 */
971#define PR (PR_MASK << PR_SHIFT)
972#define PW (PW_MASK << PW_SHIFT)
973#define UR (UR_MASK << UR_SHIFT)
974#define UW (UW_MASK << UW_SHIFT)
975#define XN (XN_MASK << XN_SHIFT)
976#define NSDESC (NSDESC_MASK << NSDESC_SHIFT)
977#define ISH (ISH_MASK << ISH_SHIFT)
978#define SH (SH_MASK << SH_SHIFT)
979#define MT (MT_MASK << MT_SHIFT)
980#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT)
981#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT)
982
983
984/* TLBTR1 */
985#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT)
986#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT)
987
988
989/* TLBTR2 */
990#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT)
991#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT)
992#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
993#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT)
994#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT)
995
996
997/* Context Register Fields */
998/* ACTLR */
999#define CFERE (CFERE_MASK << CFERE_SHIFT)
1000#define CFEIE (CFEIE_MASK << CFEIE_SHIFT)
1001#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT)
1002#define RCOSH (RCOSH_MASK << RCOSH_SHIFT)
1003#define RCISH (RCISH_MASK << RCISH_SHIFT)
1004#define RCNSH (RCNSH_MASK << RCNSH_SHIFT)
1005#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT)
1006#define DNA (DNA_MASK << DNA_SHIFT)
1007#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT)
1008#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT)
1009#define CFCFG (CFCFG_MASK << CFCFG_SHIFT)
1010#define TIPCF (TIPCF_MASK << TIPCF_SHIFT)
1011#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT)
1012#define HUME (HUME_MASK << HUME_SHIFT)
1013#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT)
1014#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT)
1015
1016
1017/* BFBCR */
1018#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT)
1019#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT)
1020#define SFVS (SFVS_MASK << SFVS_SHIFT)
1021#define FLVIC (FLVIC_MASK << FLVIC_SHIFT)
1022#define SLVIC (SLVIC_MASK << SLVIC_SHIFT)
1023
1024
1025/* CONTEXTIDR */
1026#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT)
1027#define PROCID (PROCID_MASK << PROCID_SHIFT)
1028
1029
1030/* FSR */
1031#define TF (TF_MASK << TF_SHIFT)
1032#define AFF (AFF_MASK << AFF_SHIFT)
1033#define APF (APF_MASK << APF_SHIFT)
1034#define TLBMF (TLBMF_MASK << TLBMF_SHIFT)
1035#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT)
1036#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT)
1037#define MHF (MHF_MASK << MHF_SHIFT)
1038#define SL (SL_MASK << SL_SHIFT)
1039#define SS (SS_MASK << SS_SHIFT)
1040#define MULTI (MULTI_MASK << MULTI_SHIFT)
1041
1042
1043/* FSYNR0 */
1044#define AMID (AMID_MASK << AMID_SHIFT)
1045#define APID (APID_MASK << APID_SHIFT)
1046#define ABID (ABID_MASK << ABID_SHIFT)
1047#define ATID (ATID_MASK << ATID_SHIFT)
1048
1049
1050/* FSYNR1 */
1051#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT)
1052#define ASHARED (ASHARED_MASK << ASHARED_SHIFT)
1053#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT)
1054#define APRIV (APRIV_MASK << APRIV_SHIFT)
1055#define APROTNS (APROTNS_MASK << APROTNS_SHIFT)
1056#define AINST (AINST_MASK << AINST_SHIFT)
1057#define AWRITE (AWRITE_MASK << AWRITE_SHIFT)
1058#define ABURST (ABURST_MASK << ABURST_SHIFT)
1059#define ALEN (ALEN_MASK << ALEN_SHIFT)
1060#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT)
1061#define ALOCK (ALOCK_MASK << ALOCK_SHIFT)
1062#define AFULL (AFULL_MASK << AFULL_SHIFT)
1063
1064
1065/* NMRR */
1066#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT)
1067#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT)
1068#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT)
1069#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT)
1070#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT)
1071#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT)
1072#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT)
1073#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT)
1074#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT)
1075#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT)
1076#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT)
1077#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT)
1078#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT)
1079#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT)
1080#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT)
1081#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT)
1082
1083
1084/* PAR */
1085#define FAULT (FAULT_MASK << FAULT_SHIFT)
1086/* If a fault is present, these are the
1087same as the fault fields in the FAR */
1088#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT)
1089#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT)
1090#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT)
1091#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT)
1092#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT)
1093#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT)
1094#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT)
1095#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT)
1096#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT)
1097
1098/* If NO fault is present, the following fields are in effect */
1099/* (FAULT remains as before) */
1100#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT)
1101#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT)
1102#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT)
1103#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT)
1104#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT)
1105#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT)
1106
1107
1108/* PRRR */
1109#define MTC0 (MTC0_MASK << MTC0_SHIFT)
1110#define MTC1 (MTC1_MASK << MTC1_SHIFT)
1111#define MTC2 (MTC2_MASK << MTC2_SHIFT)
1112#define MTC3 (MTC3_MASK << MTC3_SHIFT)
1113#define MTC4 (MTC4_MASK << MTC4_SHIFT)
1114#define MTC5 (MTC5_MASK << MTC5_SHIFT)
1115#define MTC6 (MTC6_MASK << MTC6_SHIFT)
1116#define MTC7 (MTC7_MASK << MTC7_SHIFT)
1117#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT)
1118#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT)
1119#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT)
1120#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT)
1121#define NOS0 (NOS0_MASK << NOS0_SHIFT)
1122#define NOS1 (NOS1_MASK << NOS1_SHIFT)
1123#define NOS2 (NOS2_MASK << NOS2_SHIFT)
1124#define NOS3 (NOS3_MASK << NOS3_SHIFT)
1125#define NOS4 (NOS4_MASK << NOS4_SHIFT)
1126#define NOS5 (NOS5_MASK << NOS5_SHIFT)
1127#define NOS6 (NOS6_MASK << NOS6_SHIFT)
1128#define NOS7 (NOS7_MASK << NOS7_SHIFT)
1129
1130
1131/* RESUME */
1132#define TNR (TNR_MASK << TNR_SHIFT)
1133
1134
1135/* SCTLR */
1136#define M (M_MASK << M_SHIFT)
1137#define TRE (TRE_MASK << TRE_SHIFT)
1138#define AFE (AFE_MASK << AFE_SHIFT)
1139#define HAF (HAF_MASK << HAF_SHIFT)
1140#define BE (BE_MASK << BE_SHIFT)
1141#define AFFD (AFFD_MASK << AFFD_SHIFT)
1142
1143
1144/* TLBIASID */
1145#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT)
1146
1147
1148/* TLBIVA */
1149#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT)
1150#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT)
1151
1152
1153/* TLBIVAA */
1154#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT)
1155
1156
1157/* TLBLCKR */
1158#define LKE (LKE_MASK << LKE_SHIFT)
1159#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
1160#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT)
1161#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT)
1162#define FLOOR (FLOOR_MASK << FLOOR_SHIFT)
1163#define VICTIM (VICTIM_MASK << VICTIM_SHIFT)
1164
1165
1166/* TTBCR */
1167#define N (N_MASK << N_SHIFT)
1168#define PD0 (PD0_MASK << PD0_SHIFT)
1169#define PD1 (PD1_MASK << PD1_SHIFT)
1170
1171
1172/* TTBR0 */
1173#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT)
1174#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT)
1175#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT)
1176#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT)
1177#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT)
1178#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT)
1179
1180
1181/* TTBR1 */
1182#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT)
1183#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT)
1184#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT)
1185#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT)
1186#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT)
1187#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT)
1188
1189
1190/* V2PSR */
1191#define HIT (HIT_MASK << HIT_SHIFT)
1192#define INDEX (INDEX_MASK << INDEX_SHIFT)
1193
1194
1195/* V2Pxx */
1196#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT)
1197#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT)
1198
1199
1200/* Global Register Masks */
1201/* CBACRn */
1202#define RWVMID_MASK 0x1F
1203#define RWE_MASK 0x01
1204#define RWGE_MASK 0x01
1205#define CBVMID_MASK 0x1F
1206#define IRPTNDX_MASK 0xFF
1207
1208
1209/* CR */
1210#define RPUE_MASK 0x01
1211#define RPUERE_MASK 0x01
1212#define RPUEIE_MASK 0x01
1213#define DCDEE_MASK 0x01
1214#define CLIENTPD_MASK 0x01
1215#define STALLD_MASK 0x01
1216#define TLBLKCRWE_MASK 0x01
1217#define CR_TLBIALLCFG_MASK 0x01
1218#define TLBIVMIDCFG_MASK 0x01
1219#define CR_HUME_MASK 0x01
1220
1221
1222/* ESR */
1223#define CFG_MASK 0x01
1224#define BYPASS_MASK 0x01
1225#define ESR_MULTI_MASK 0x01
1226
1227
1228/* ESYNR0 */
1229#define ESYNR0_AMID_MASK 0xFF
1230#define ESYNR0_APID_MASK 0x1F
1231#define ESYNR0_ABID_MASK 0x07
1232#define ESYNR0_AVMID_MASK 0x1F
1233#define ESYNR0_ATID_MASK 0xFF
1234
1235
1236/* ESYNR1 */
1237#define ESYNR1_AMEMTYPE_MASK 0x07
1238#define ESYNR1_ASHARED_MASK 0x01
1239#define ESYNR1_AINNERSHARED_MASK 0x01
1240#define ESYNR1_APRIV_MASK 0x01
1241#define ESYNR1_APROTNS_MASK 0x01
1242#define ESYNR1_AINST_MASK 0x01
1243#define ESYNR1_AWRITE_MASK 0x01
1244#define ESYNR1_ABURST_MASK 0x01
1245#define ESYNR1_ALEN_MASK 0x0F
1246#define ESYNR1_ASIZE_MASK 0x01
1247#define ESYNR1_ALOCK_MASK 0x03
1248#define ESYNR1_AOOO_MASK 0x01
1249#define ESYNR1_AFULL_MASK 0x01
1250#define ESYNR1_AC_MASK 0x01
1251#define ESYNR1_DCD_MASK 0x01
1252
1253
1254/* IDR */
1255#define NM2VCBMT_MASK 0x1FF
1256#define HTW_MASK 0x01
1257#define HUM_MASK 0x01
1258#define TLBSIZE_MASK 0x0F
1259#define NCB_MASK 0xFF
1260#define NIRPT_MASK 0xFF
1261
1262
1263/* M2VCBRn */
1264#define VMID_MASK 0x1F
1265#define CBNDX_MASK 0xFF
1266#define BYPASSD_MASK 0x01
1267#define BPRCOSH_MASK 0x01
1268#define BPRCISH_MASK 0x01
1269#define BPRCNSH_MASK 0x01
1270#define BPSHCFG_MASK 0x03
1271#define NSCFG_MASK 0x03
1272#define BPMTCFG_MASK 0x01
1273#define BPMEMTYPE_MASK 0x07
1274
1275
1276/* REV */
1277#define MINOR_MASK 0x0F
1278#define MAJOR_MASK 0x0F
1279
1280
1281/* TESTBUSCR */
1282#define TBE_MASK 0x01
1283#define SPDMBE_MASK 0x01
1284#define WGSEL_MASK 0x03
1285#define TBLSEL_MASK 0x03
1286#define TBHSEL_MASK 0x03
1287#define SPDM0SEL_MASK 0x0F
1288#define SPDM1SEL_MASK 0x0F
1289#define SPDM2SEL_MASK 0x0F
1290#define SPDM3SEL_MASK 0x0F
1291
1292
1293/* TLBIMID */
1294#define TLBIVMID_VMID_MASK 0x1F
1295
1296
1297/* TLBRSW */
1298#define TLBRSW_INDEX_MASK 0xFF
1299#define TLBBFBS_MASK 0x03
1300
1301
1302/* TLBTR0 */
1303#define PR_MASK 0x01
1304#define PW_MASK 0x01
1305#define UR_MASK 0x01
1306#define UW_MASK 0x01
1307#define XN_MASK 0x01
1308#define NSDESC_MASK 0x01
1309#define ISH_MASK 0x01
1310#define SH_MASK 0x01
1311#define MT_MASK 0x07
1312#define DPSIZR_MASK 0x07
1313#define DPSIZC_MASK 0x07
1314
1315
1316/* TLBTR1 */
1317#define TLBTR1_VMID_MASK 0x1F
1318#define TLBTR1_PA_MASK 0x000FFFFF
1319
1320
1321/* TLBTR2 */
1322#define TLBTR2_ASID_MASK 0xFF
1323#define TLBTR2_V_MASK 0x01
1324#define TLBTR2_NSTID_MASK 0x01
1325#define TLBTR2_NV_MASK 0x01
1326#define TLBTR2_VA_MASK 0x000FFFFF
1327
1328
1329/* Global Register Shifts */
1330/* CBACRn */
1331#define RWVMID_SHIFT 0
1332#define RWE_SHIFT 8
1333#define RWGE_SHIFT 9
1334#define CBVMID_SHIFT 16
1335#define IRPTNDX_SHIFT 24
1336
1337
1338/* CR */
1339#define RPUE_SHIFT 0
1340#define RPUERE_SHIFT 1
1341#define RPUEIE_SHIFT 2
1342#define DCDEE_SHIFT 3
1343#define CLIENTPD_SHIFT 4
1344#define STALLD_SHIFT 5
1345#define TLBLKCRWE_SHIFT 6
1346#define CR_TLBIALLCFG_SHIFT 7
1347#define TLBIVMIDCFG_SHIFT 8
1348#define CR_HUME_SHIFT 9
1349
1350
1351/* ESR */
1352#define CFG_SHIFT 0
1353#define BYPASS_SHIFT 1
1354#define ESR_MULTI_SHIFT 31
1355
1356
1357/* ESYNR0 */
1358#define ESYNR0_AMID_SHIFT 0
1359#define ESYNR0_APID_SHIFT 8
1360#define ESYNR0_ABID_SHIFT 13
1361#define ESYNR0_AVMID_SHIFT 16
1362#define ESYNR0_ATID_SHIFT 24
1363
1364
1365/* ESYNR1 */
1366#define ESYNR1_AMEMTYPE_SHIFT 0
1367#define ESYNR1_ASHARED_SHIFT 3
1368#define ESYNR1_AINNERSHARED_SHIFT 4
1369#define ESYNR1_APRIV_SHIFT 5
1370#define ESYNR1_APROTNS_SHIFT 6
1371#define ESYNR1_AINST_SHIFT 7
1372#define ESYNR1_AWRITE_SHIFT 8
1373#define ESYNR1_ABURST_SHIFT 10
1374#define ESYNR1_ALEN_SHIFT 12
1375#define ESYNR1_ASIZE_SHIFT 16
1376#define ESYNR1_ALOCK_SHIFT 20
1377#define ESYNR1_AOOO_SHIFT 22
1378#define ESYNR1_AFULL_SHIFT 24
1379#define ESYNR1_AC_SHIFT 30
1380#define ESYNR1_DCD_SHIFT 31
1381
1382
1383/* IDR */
1384#define NM2VCBMT_SHIFT 0
1385#define HTW_SHIFT 9
1386#define HUM_SHIFT 10
1387#define TLBSIZE_SHIFT 12
1388#define NCB_SHIFT 16
1389#define NIRPT_SHIFT 24
1390
1391
1392/* M2VCBRn */
1393#define VMID_SHIFT 0
1394#define CBNDX_SHIFT 8
1395#define BYPASSD_SHIFT 16
1396#define BPRCOSH_SHIFT 17
1397#define BPRCISH_SHIFT 18
1398#define BPRCNSH_SHIFT 19
1399#define BPSHCFG_SHIFT 20
1400#define NSCFG_SHIFT 22
1401#define BPMTCFG_SHIFT 24
1402#define BPMEMTYPE_SHIFT 25
1403
1404
1405/* REV */
1406#define MINOR_SHIFT 0
1407#define MAJOR_SHIFT 4
1408
1409
1410/* TESTBUSCR */
1411#define TBE_SHIFT 0
1412#define SPDMBE_SHIFT 1
1413#define WGSEL_SHIFT 8
1414#define TBLSEL_SHIFT 12
1415#define TBHSEL_SHIFT 14
1416#define SPDM0SEL_SHIFT 16
1417#define SPDM1SEL_SHIFT 20
1418#define SPDM2SEL_SHIFT 24
1419#define SPDM3SEL_SHIFT 28
1420
1421
1422/* TLBIMID */
1423#define TLBIVMID_VMID_SHIFT 0
1424
1425
1426/* TLBRSW */
1427#define TLBRSW_INDEX_SHIFT 0
1428#define TLBBFBS_SHIFT 8
1429
1430
1431/* TLBTR0 */
1432#define PR_SHIFT 0
1433#define PW_SHIFT 1
1434#define UR_SHIFT 2
1435#define UW_SHIFT 3
1436#define XN_SHIFT 4
1437#define NSDESC_SHIFT 6
1438#define ISH_SHIFT 7
1439#define SH_SHIFT 8
1440#define MT_SHIFT 9
1441#define DPSIZR_SHIFT 16
1442#define DPSIZC_SHIFT 20
1443
1444
1445/* TLBTR1 */
1446#define TLBTR1_VMID_SHIFT 0
1447#define TLBTR1_PA_SHIFT 12
1448
1449
1450/* TLBTR2 */
1451#define TLBTR2_ASID_SHIFT 0
1452#define TLBTR2_V_SHIFT 8
1453#define TLBTR2_NSTID_SHIFT 9
1454#define TLBTR2_NV_SHIFT 10
1455#define TLBTR2_VA_SHIFT 12
1456
1457
1458/* Context Register Masks */
1459/* ACTLR */
1460#define CFERE_MASK 0x01
1461#define CFEIE_MASK 0x01
1462#define PTSHCFG_MASK 0x03
1463#define RCOSH_MASK 0x01
1464#define RCISH_MASK 0x01
1465#define RCNSH_MASK 0x01
1466#define PRIVCFG_MASK 0x03
1467#define DNA_MASK 0x01
1468#define DNLV2PA_MASK 0x01
1469#define TLBMCFG_MASK 0x03
1470#define CFCFG_MASK 0x01
1471#define TIPCF_MASK 0x01
1472#define V2PCFG_MASK 0x03
1473#define HUME_MASK 0x01
1474#define PTMTCFG_MASK 0x01
1475#define PTMEMTYPE_MASK 0x07
1476
1477
1478/* BFBCR */
1479#define BFBDFE_MASK 0x01
1480#define BFBSFE_MASK 0x01
1481#define SFVS_MASK 0x01
1482#define FLVIC_MASK 0x0F
1483#define SLVIC_MASK 0x0F
1484
1485
1486/* CONTEXTIDR */
1487#define CONTEXTIDR_ASID_MASK 0xFF
1488#define PROCID_MASK 0x00FFFFFF
1489
1490
1491/* FSR */
1492#define TF_MASK 0x01
1493#define AFF_MASK 0x01
1494#define APF_MASK 0x01
1495#define TLBMF_MASK 0x01
1496#define HTWDEEF_MASK 0x01
1497#define HTWSEEF_MASK 0x01
1498#define MHF_MASK 0x01
1499#define SL_MASK 0x01
1500#define SS_MASK 0x01
1501#define MULTI_MASK 0x01
1502
1503
1504/* FSYNR0 */
1505#define AMID_MASK 0xFF
1506#define APID_MASK 0x1F
1507#define ABID_MASK 0x07
1508#define ATID_MASK 0xFF
1509
1510
1511/* FSYNR1 */
1512#define AMEMTYPE_MASK 0x07
1513#define ASHARED_MASK 0x01
1514#define AINNERSHARED_MASK 0x01
1515#define APRIV_MASK 0x01
1516#define APROTNS_MASK 0x01
1517#define AINST_MASK 0x01
1518#define AWRITE_MASK 0x01
1519#define ABURST_MASK 0x01
1520#define ALEN_MASK 0x0F
1521#define FSYNR1_ASIZE_MASK 0x07
1522#define ALOCK_MASK 0x03
1523#define AFULL_MASK 0x01
1524
1525
1526/* NMRR */
1527#define ICPC0_MASK 0x03
1528#define ICPC1_MASK 0x03
1529#define ICPC2_MASK 0x03
1530#define ICPC3_MASK 0x03
1531#define ICPC4_MASK 0x03
1532#define ICPC5_MASK 0x03
1533#define ICPC6_MASK 0x03
1534#define ICPC7_MASK 0x03
1535#define OCPC0_MASK 0x03
1536#define OCPC1_MASK 0x03
1537#define OCPC2_MASK 0x03
1538#define OCPC3_MASK 0x03
1539#define OCPC4_MASK 0x03
1540#define OCPC5_MASK 0x03
1541#define OCPC6_MASK 0x03
1542#define OCPC7_MASK 0x03
1543
1544
1545/* PAR */
1546#define FAULT_MASK 0x01
1547/* If a fault is present, these are the
1548same as the fault fields in the FAR */
1549#define FAULT_TF_MASK 0x01
1550#define FAULT_AFF_MASK 0x01
1551#define FAULT_APF_MASK 0x01
1552#define FAULT_TLBMF_MASK 0x01
1553#define FAULT_HTWDEEF_MASK 0x01
1554#define FAULT_HTWSEEF_MASK 0x01
1555#define FAULT_MHF_MASK 0x01
1556#define FAULT_SL_MASK 0x01
1557#define FAULT_SS_MASK 0x01
1558
1559/* If NO fault is present, the following
1560 * fields are in effect
1561 * (FAULT remains as before) */
1562#define PAR_NOFAULT_SS_MASK 0x01
1563#define PAR_NOFAULT_MT_MASK 0x07
1564#define PAR_NOFAULT_SH_MASK 0x01
1565#define PAR_NOFAULT_NS_MASK 0x01
1566#define PAR_NOFAULT_NOS_MASK 0x01
1567#define PAR_NPFAULT_PA_MASK 0x000FFFFF
1568
1569
1570/* PRRR */
1571#define MTC0_MASK 0x03
1572#define MTC1_MASK 0x03
1573#define MTC2_MASK 0x03
1574#define MTC3_MASK 0x03
1575#define MTC4_MASK 0x03
1576#define MTC5_MASK 0x03
1577#define MTC6_MASK 0x03
1578#define MTC7_MASK 0x03
1579#define SHDSH0_MASK 0x01
1580#define SHDSH1_MASK 0x01
1581#define SHNMSH0_MASK 0x01
1582#define SHNMSH1_MASK 0x01
1583#define NOS0_MASK 0x01
1584#define NOS1_MASK 0x01
1585#define NOS2_MASK 0x01
1586#define NOS3_MASK 0x01
1587#define NOS4_MASK 0x01
1588#define NOS5_MASK 0x01
1589#define NOS6_MASK 0x01
1590#define NOS7_MASK 0x01
1591
1592
1593/* RESUME */
1594#define TNR_MASK 0x01
1595
1596
1597/* SCTLR */
1598#define M_MASK 0x01
1599#define TRE_MASK 0x01
1600#define AFE_MASK 0x01
1601#define HAF_MASK 0x01
1602#define BE_MASK 0x01
1603#define AFFD_MASK 0x01
1604
1605
1606/* TLBIASID */
1607#define TLBIASID_ASID_MASK 0xFF
1608
1609
1610/* TLBIVA */
1611#define TLBIVA_ASID_MASK 0xFF
1612#define TLBIVA_VA_MASK 0x000FFFFF
1613
1614
1615/* TLBIVAA */
1616#define TLBIVAA_VA_MASK 0x000FFFFF
1617
1618
1619/* TLBLCKR */
1620#define LKE_MASK 0x01
1621#define TLBLCKR_TLBIALLCFG_MASK 0x01
1622#define TLBIASIDCFG_MASK 0x01
1623#define TLBIVAACFG_MASK 0x01
1624#define FLOOR_MASK 0xFF
1625#define VICTIM_MASK 0xFF
1626
1627
1628/* TTBCR */
1629#define N_MASK 0x07
1630#define PD0_MASK 0x01
1631#define PD1_MASK 0x01
1632
1633
1634/* TTBR0 */
1635#define TTBR0_IRGNH_MASK 0x01
1636#define TTBR0_SH_MASK 0x01
1637#define TTBR0_ORGN_MASK 0x03
1638#define TTBR0_NOS_MASK 0x01
1639#define TTBR0_IRGNL_MASK 0x01
1640#define TTBR0_PA_MASK 0x0003FFFF
1641
1642
1643/* TTBR1 */
1644#define TTBR1_IRGNH_MASK 0x01
1645#define TTBR1_SH_MASK 0x01
1646#define TTBR1_ORGN_MASK 0x03
1647#define TTBR1_NOS_MASK 0x01
1648#define TTBR1_IRGNL_MASK 0x01
1649#define TTBR1_PA_MASK 0x0003FFFF
1650
1651
1652/* V2PSR */
1653#define HIT_MASK 0x01
1654#define INDEX_MASK 0xFF
1655
1656
1657/* V2Pxx */
1658#define V2Pxx_INDEX_MASK 0xFF
1659#define V2Pxx_VA_MASK 0x000FFFFF
1660
1661
1662/* Context Register Shifts */
1663/* ACTLR */
1664#define CFERE_SHIFT 0
1665#define CFEIE_SHIFT 1
1666#define PTSHCFG_SHIFT 2
1667#define RCOSH_SHIFT 4
1668#define RCISH_SHIFT 5
1669#define RCNSH_SHIFT 6
1670#define PRIVCFG_SHIFT 8
1671#define DNA_SHIFT 10
1672#define DNLV2PA_SHIFT 11
1673#define TLBMCFG_SHIFT 12
1674#define CFCFG_SHIFT 14
1675#define TIPCF_SHIFT 15
1676#define V2PCFG_SHIFT 16
1677#define HUME_SHIFT 18
1678#define PTMTCFG_SHIFT 20
1679#define PTMEMTYPE_SHIFT 21
1680
1681
1682/* BFBCR */
1683#define BFBDFE_SHIFT 0
1684#define BFBSFE_SHIFT 1
1685#define SFVS_SHIFT 2
1686#define FLVIC_SHIFT 4
1687#define SLVIC_SHIFT 8
1688
1689
1690/* CONTEXTIDR */
1691#define CONTEXTIDR_ASID_SHIFT 0
1692#define PROCID_SHIFT 8
1693
1694
1695/* FSR */
1696#define TF_SHIFT 1
1697#define AFF_SHIFT 2
1698#define APF_SHIFT 3
1699#define TLBMF_SHIFT 4
1700#define HTWDEEF_SHIFT 5
1701#define HTWSEEF_SHIFT 6
1702#define MHF_SHIFT 7
1703#define SL_SHIFT 16
1704#define SS_SHIFT 30
1705#define MULTI_SHIFT 31
1706
1707
1708/* FSYNR0 */
1709#define AMID_SHIFT 0
1710#define APID_SHIFT 8
1711#define ABID_SHIFT 13
1712#define ATID_SHIFT 24
1713
1714
1715/* FSYNR1 */
1716#define AMEMTYPE_SHIFT 0
1717#define ASHARED_SHIFT 3
1718#define AINNERSHARED_SHIFT 4
1719#define APRIV_SHIFT 5
1720#define APROTNS_SHIFT 6
1721#define AINST_SHIFT 7
1722#define AWRITE_SHIFT 8
1723#define ABURST_SHIFT 10
1724#define ALEN_SHIFT 12
1725#define FSYNR1_ASIZE_SHIFT 16
1726#define ALOCK_SHIFT 20
1727#define AFULL_SHIFT 24
1728
1729
1730/* NMRR */
1731#define ICPC0_SHIFT 0
1732#define ICPC1_SHIFT 2
1733#define ICPC2_SHIFT 4
1734#define ICPC3_SHIFT 6
1735#define ICPC4_SHIFT 8
1736#define ICPC5_SHIFT 10
1737#define ICPC6_SHIFT 12
1738#define ICPC7_SHIFT 14
1739#define OCPC0_SHIFT 16
1740#define OCPC1_SHIFT 18
1741#define OCPC2_SHIFT 20
1742#define OCPC3_SHIFT 22
1743#define OCPC4_SHIFT 24
1744#define OCPC5_SHIFT 26
1745#define OCPC6_SHIFT 28
1746#define OCPC7_SHIFT 30
1747
1748
1749/* PAR */
1750#define FAULT_SHIFT 0
1751/* If a fault is present, these are the
1752same as the fault fields in the FAR */
1753#define FAULT_TF_SHIFT 1
1754#define FAULT_AFF_SHIFT 2
1755#define FAULT_APF_SHIFT 3
1756#define FAULT_TLBMF_SHIFT 4
1757#define FAULT_HTWDEEF_SHIFT 5
1758#define FAULT_HTWSEEF_SHIFT 6
1759#define FAULT_MHF_SHIFT 7
1760#define FAULT_SL_SHIFT 16
1761#define FAULT_SS_SHIFT 30
1762
1763/* If NO fault is present, the following
1764 * fields are in effect
1765 * (FAULT remains as before) */
1766#define PAR_NOFAULT_SS_SHIFT 1
1767#define PAR_NOFAULT_MT_SHIFT 4
1768#define PAR_NOFAULT_SH_SHIFT 7
1769#define PAR_NOFAULT_NS_SHIFT 9
1770#define PAR_NOFAULT_NOS_SHIFT 10
1771#define PAR_NPFAULT_PA_SHIFT 12
1772
1773
1774/* PRRR */
1775#define MTC0_SHIFT 0
1776#define MTC1_SHIFT 2
1777#define MTC2_SHIFT 4
1778#define MTC3_SHIFT 6
1779#define MTC4_SHIFT 8
1780#define MTC5_SHIFT 10
1781#define MTC6_SHIFT 12
1782#define MTC7_SHIFT 14
1783#define SHDSH0_SHIFT 16
1784#define SHDSH1_SHIFT 17
1785#define SHNMSH0_SHIFT 18
1786#define SHNMSH1_SHIFT 19
1787#define NOS0_SHIFT 24
1788#define NOS1_SHIFT 25
1789#define NOS2_SHIFT 26
1790#define NOS3_SHIFT 27
1791#define NOS4_SHIFT 28
1792#define NOS5_SHIFT 29
1793#define NOS6_SHIFT 30
1794#define NOS7_SHIFT 31
1795
1796
1797/* RESUME */
1798#define TNR_SHIFT 0
1799
1800
1801/* SCTLR */
1802#define M_SHIFT 0
1803#define TRE_SHIFT 1
1804#define AFE_SHIFT 2
1805#define HAF_SHIFT 3
1806#define BE_SHIFT 4
1807#define AFFD_SHIFT 5
1808
1809
1810/* TLBIASID */
1811#define TLBIASID_ASID_SHIFT 0
1812
1813
1814/* TLBIVA */
1815#define TLBIVA_ASID_SHIFT 0
1816#define TLBIVA_VA_SHIFT 12
1817
1818
1819/* TLBIVAA */
1820#define TLBIVAA_VA_SHIFT 12
1821
1822
1823/* TLBLCKR */
1824#define LKE_SHIFT 0
1825#define TLBLCKR_TLBIALLCFG_SHIFT 1
1826#define TLBIASIDCFG_SHIFT 2
1827#define TLBIVAACFG_SHIFT 3
1828#define FLOOR_SHIFT 8
1829#define VICTIM_SHIFT 8
1830
1831
1832/* TTBCR */
1833#define N_SHIFT 3
1834#define PD0_SHIFT 4
1835#define PD1_SHIFT 5
1836
1837
1838/* TTBR0 */
1839#define TTBR0_IRGNH_SHIFT 0
1840#define TTBR0_SH_SHIFT 1
1841#define TTBR0_ORGN_SHIFT 3
1842#define TTBR0_NOS_SHIFT 5
1843#define TTBR0_IRGNL_SHIFT 6
1844#define TTBR0_PA_SHIFT 14
1845
1846
1847/* TTBR1 */
1848#define TTBR1_IRGNH_SHIFT 0
1849#define TTBR1_SH_SHIFT 1
1850#define TTBR1_ORGN_SHIFT 3
1851#define TTBR1_NOS_SHIFT 5
1852#define TTBR1_IRGNL_SHIFT 6
1853#define TTBR1_PA_SHIFT 14
1854
1855
1856/* V2PSR */
1857#define HIT_SHIFT 0
1858#define INDEX_SHIFT 8
1859
1860
1861/* V2Pxx */
1862#define V2Pxx_INDEX_SHIFT 0
1863#define V2Pxx_VA_SHIFT 12
1864
1865#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
deleted file mode 100644
index 7bca8d7108d6..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
24#define __ASM_ARCH_MSM_IOMAP_8960_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * If you add or remove entries here, you'll want to edit the
30 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
31 * changes.
32 *
33 */
34
35#define MSM8960_TMR_PHYS 0x0200A000
36#define MSM8960_TMR_SIZE SZ_4K
37
38#define MSM8960_TMR0_PHYS 0x0208A000
39#define MSM8960_TMR0_SIZE SZ_4K
40
41#ifdef CONFIG_DEBUG_MSM8960_UART
42#define MSM_DEBUG_UART_BASE 0xF0040000
43#define MSM_DEBUG_UART_PHYS 0x16440000
44#endif
45
46#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
deleted file mode 100644
index 75a7b62c1c74..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
24#define __ASM_ARCH_MSM_IOMAP_8X60_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_TLMM_BASE IOMEM(0xF0004000)
39#define MSM_TLMM_PHYS 0x00800000
40#define MSM_TLMM_SIZE SZ_16K
41
42#define MSM8X60_TMR_PHYS 0x02000000
43#define MSM8X60_TMR_SIZE SZ_4K
44
45#define MSM8X60_TMR0_PHYS 0x02040000
46#define MSM8X60_TMR0_SIZE SZ_4K
47
48#ifdef CONFIG_DEBUG_MSM8660_UART
49#define MSM_DEBUG_UART_BASE 0xF0040000
50#define MSM_DEBUG_UART_PHYS 0x19C40000
51#endif
52
53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index c56e81ffdcde..0e4f49157684 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -45,25 +45,8 @@
45#include "msm_iomap-7x00.h" 45#include "msm_iomap-7x00.h"
46#endif 46#endif
47 47
48#include "msm_iomap-8x60.h"
49#include "msm_iomap-8960.h"
50
51#define MSM_DEBUG_UART_SIZE SZ_4K
52#if defined(CONFIG_DEBUG_MSM_UART1)
53#define MSM_DEBUG_UART_BASE 0xE1000000
54#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
55#elif defined(CONFIG_DEBUG_MSM_UART2)
56#define MSM_DEBUG_UART_BASE 0xE1000000
57#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
58#elif defined(CONFIG_DEBUG_MSM_UART3)
59#define MSM_DEBUG_UART_BASE 0xE1000000
60#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
61#endif
62
63/* Virtual addresses shared across all MSM targets. */ 48/* Virtual addresses shared across all MSM targets. */
64#define MSM_CSR_BASE IOMEM(0xE0001000) 49#define MSM_CSR_BASE IOMEM(0xE0001000)
65#define MSM_TMR_BASE IOMEM(0xF0200000)
66#define MSM_TMR0_BASE IOMEM(0xF0201000)
67#define MSM_GPIO1_BASE IOMEM(0xE0003000) 50#define MSM_GPIO1_BASE IOMEM(0xE0003000)
68#define MSM_GPIO2_BASE IOMEM(0xE0004000) 51#define MSM_GPIO2_BASE IOMEM(0xE0004000)
69 52
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
deleted file mode 100644
index 94324870fb04..000000000000
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
17#define __ASM_ARCH_MSM_UNCOMPRESS_H
18
19#include <asm/barrier.h>
20#include <asm/processor.h>
21#include <mach/msm_iomap.h>
22
23#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
24#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
25
26#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
27#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
28#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
29#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
30#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
31
32static void putc(int c)
33{
34#if defined(MSM_DEBUG_UART_PHYS)
35#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
36 /*
37 * Wait for TX_READY to be set; but skip it if we have a
38 * TX underrun.
39 */
40 if (!(UART_DM_SR & 0x08))
41 while (!(UART_DM_ISR & 0x80))
42 cpu_relax();
43
44 UART_DM_CR = 0x300;
45 UART_DM_NCHAR = 0x1;
46 UART_DM_TF = c;
47#else
48 while (!(UART_CSR & 0x04))
49 cpu_relax();
50 UART_TF = c;
51#endif
52#endif
53}
54
55static inline void flush(void)
56{
57}
58
59static inline void arch_decomp_setup(void)
60{
61}
62
63#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3dc04ccaf59f..adc8971c7266 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -18,6 +18,7 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/bug.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/export.h> 24#include <linux/export.h>
@@ -27,8 +28,6 @@
27#include <mach/msm_iomap.h> 28#include <mach/msm_iomap.h>
28#include <asm/mach/map.h> 29#include <asm/mach/map.h>
29 30
30#include <mach/board.h>
31
32#include "common.h" 31#include "common.h"
33 32
34#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ 33#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
@@ -52,26 +51,38 @@ static struct map_desc msm_io_desc[] __initdata = {
52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), 51 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), 52 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), 53 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
55#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
56 defined(CONFIG_DEBUG_MSM_UART3)
57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
58#endif
59 { 54 {
60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 55 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
61 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 56 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
62 .length = MSM_SHARED_RAM_SIZE, 57 .length = MSM_SHARED_RAM_SIZE,
63 .type = MT_DEVICE, 58 .type = MT_DEVICE,
64 }, 59 },
60#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
61 defined(CONFIG_DEBUG_MSM_UART3)
62 {
63 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
64 .length = SZ_4K,
65 .type = MT_DEVICE_NONSHARED,
66 }
67#endif
65}; 68};
66 69
67void __init msm_map_common_io(void) 70void __init msm_map_common_io(void)
68{ 71{
72 size_t size = ARRAY_SIZE(msm_io_desc);
73
69 /* Make sure the peripheral register window is closed, since 74 /* Make sure the peripheral register window is closed, since
70 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which 75 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
71 * pages are peripheral interface or not. 76 * pages are peripheral interface or not.
72 */ 77 */
73 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 78 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
74 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); 79#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
80 defined(CONFIG_DEBUG_MSM_UART3)
81 debug_ll_addr(&msm_io_desc[size - 1].pfn,
82 &msm_io_desc[size - 1].virtual);
83 msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
84#endif
85 iotable_init(msm_io_desc, size);
75} 86}
76#endif 87#endif
77 88
@@ -87,10 +98,6 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
87 MSM_DEVICE(SCPLL), 98 MSM_DEVICE(SCPLL),
88 MSM_DEVICE(AD5), 99 MSM_DEVICE(AD5),
89 MSM_DEVICE(MDC), 100 MSM_DEVICE(MDC),
90#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
91 defined(CONFIG_DEBUG_MSM_UART3)
92 MSM_DEVICE(DEBUG_UART),
93#endif
94 { 101 {
95 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 102 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
96 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 103 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -101,40 +108,11 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
101 108
102void __init msm_map_qsd8x50_io(void) 109void __init msm_map_qsd8x50_io(void)
103{ 110{
111 debug_ll_io_init();
104 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); 112 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
105} 113}
106#endif /* CONFIG_ARCH_QSD8X50 */ 114#endif /* CONFIG_ARCH_QSD8X50 */
107 115
108#ifdef CONFIG_ARCH_MSM8X60
109static struct map_desc msm8x60_io_desc[] __initdata = {
110 MSM_CHIP_DEVICE(TMR, MSM8X60),
111 MSM_CHIP_DEVICE(TMR0, MSM8X60),
112#ifdef CONFIG_DEBUG_MSM8660_UART
113 MSM_DEVICE(DEBUG_UART),
114#endif
115};
116
117void __init msm_map_msm8x60_io(void)
118{
119 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
120}
121#endif /* CONFIG_ARCH_MSM8X60 */
122
123#ifdef CONFIG_ARCH_MSM8960
124static struct map_desc msm8960_io_desc[] __initdata = {
125 MSM_CHIP_DEVICE(TMR, MSM8960),
126 MSM_CHIP_DEVICE(TMR0, MSM8960),
127#ifdef CONFIG_DEBUG_MSM8960_UART
128 MSM_DEVICE(DEBUG_UART),
129#endif
130};
131
132void __init msm_map_msm8960_io(void)
133{
134 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
135}
136#endif /* CONFIG_ARCH_MSM8960 */
137
138#ifdef CONFIG_ARCH_MSM7X30 116#ifdef CONFIG_ARCH_MSM7X30
139static struct map_desc msm7x30_io_desc[] __initdata = { 117static struct map_desc msm7x30_io_desc[] __initdata = {
140 MSM_DEVICE(VIC), 118 MSM_DEVICE(VIC),
@@ -150,10 +128,6 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
150 MSM_DEVICE(SAW), 128 MSM_DEVICE(SAW),
151 MSM_DEVICE(GCC), 129 MSM_DEVICE(GCC),
152 MSM_DEVICE(TCSR), 130 MSM_DEVICE(TCSR),
153#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
154 defined(CONFIG_DEBUG_MSM_UART3)
155 MSM_DEVICE(DEBUG_UART),
156#endif
157 { 131 {
158 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 132 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
159 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 133 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -164,10 +138,12 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
164 138
165void __init msm_map_msm7x30_io(void) 139void __init msm_map_msm7x30_io(void)
166{ 140{
141 debug_ll_io_init();
167 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); 142 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
168} 143}
169#endif /* CONFIG_ARCH_MSM7X30 */ 144#endif /* CONFIG_ARCH_MSM7X30 */
170 145
146#ifdef CONFIG_ARCH_MSM7X00A
171void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, 147void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
172 unsigned int mtype, void *caller) 148 unsigned int mtype, void *caller)
173{ 149{
@@ -182,3 +158,4 @@ void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
182 158
183 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 159 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
184} 160}
161#endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 8697cfc0d0b6..696fb73296d0 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/clocksource.h> 17#include <linux/clocksource.h>
18#include <linux/clockchips.h> 18#include <linux/clockchips.h>
19#include <linux/cpu.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
21#include <linux/irq.h> 22#include <linux/irq.h>
@@ -26,7 +27,6 @@
26#include <linux/sched_clock.h> 27#include <linux/sched_clock.h>
27 28
28#include <asm/mach/time.h> 29#include <asm/mach/time.h>
29#include <asm/localtimer.h>
30 30
31#include "common.h" 31#include "common.h"
32 32
@@ -49,7 +49,7 @@ static void __iomem *sts_base;
49 49
50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) 50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
51{ 51{
52 struct clock_event_device *evt = *(struct clock_event_device **)dev_id; 52 struct clock_event_device *evt = dev_id;
53 /* Stop the timer tick */ 53 /* Stop the timer tick */
54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) { 54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
@@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
101 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 101 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
102} 102}
103 103
104static struct clock_event_device msm_clockevent = { 104static struct clock_event_device __percpu *msm_evt;
105 .name = "gp_timer",
106 .features = CLOCK_EVT_FEAT_ONESHOT,
107 .rating = 200,
108 .set_next_event = msm_timer_set_next_event,
109 .set_mode = msm_timer_set_mode,
110};
111
112static union {
113 struct clock_event_device *evt;
114 struct clock_event_device * __percpu *percpu_evt;
115} msm_evt;
116 105
117static void __iomem *source_base; 106static void __iomem *source_base;
118 107
@@ -138,23 +127,34 @@ static struct clocksource msm_clocksource = {
138 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
139}; 128};
140 129
141#ifdef CONFIG_LOCAL_TIMERS 130static int msm_timer_irq;
131static int msm_timer_has_ppi;
132
142static int msm_local_timer_setup(struct clock_event_device *evt) 133static int msm_local_timer_setup(struct clock_event_device *evt)
143{ 134{
144 /* Use existing clock_event for cpu 0 */ 135 int cpu = smp_processor_id();
145 if (!smp_processor_id()) 136 int err;
146 return 0; 137
147 138 evt->irq = msm_timer_irq;
148 evt->irq = msm_clockevent.irq; 139 evt->name = "msm_timer";
149 evt->name = "local_timer"; 140 evt->features = CLOCK_EVT_FEAT_ONESHOT;
150 evt->features = msm_clockevent.features; 141 evt->rating = 200;
151 evt->rating = msm_clockevent.rating;
152 evt->set_mode = msm_timer_set_mode; 142 evt->set_mode = msm_timer_set_mode;
153 evt->set_next_event = msm_timer_set_next_event; 143 evt->set_next_event = msm_timer_set_next_event;
144 evt->cpumask = cpumask_of(cpu);
145
146 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
147
148 if (msm_timer_has_ppi) {
149 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
150 } else {
151 err = request_irq(evt->irq, msm_timer_interrupt,
152 IRQF_TIMER | IRQF_NOBALANCING |
153 IRQF_TRIGGER_RISING, "gp_timer", evt);
154 if (err)
155 pr_err("request_irq failed\n");
156 }
154 157
155 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
156 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
157 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
158 return 0; 158 return 0;
159} 159}
160 160
@@ -164,11 +164,28 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
164 disable_percpu_irq(evt->irq); 164 disable_percpu_irq(evt->irq);
165} 165}
166 166
167static struct local_timer_ops msm_local_timer_ops = { 167static int msm_timer_cpu_notify(struct notifier_block *self,
168 .setup = msm_local_timer_setup, 168 unsigned long action, void *hcpu)
169 .stop = msm_local_timer_stop, 169{
170 /*
171 * Grab cpu pointer in each case to avoid spurious
172 * preemptible warnings
173 */
174 switch (action & ~CPU_TASKS_FROZEN) {
175 case CPU_STARTING:
176 msm_local_timer_setup(this_cpu_ptr(msm_evt));
177 break;
178 case CPU_DYING:
179 msm_local_timer_stop(this_cpu_ptr(msm_evt));
180 break;
181 }
182
183 return NOTIFY_OK;
184}
185
186static struct notifier_block msm_timer_cpu_nb = {
187 .notifier_call = msm_timer_cpu_notify,
170}; 188};
171#endif /* CONFIG_LOCAL_TIMERS */
172 189
173static notrace u32 msm_sched_clock_read(void) 190static notrace u32 msm_sched_clock_read(void)
174{ 191{
@@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void)
178static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, 195static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
179 bool percpu) 196 bool percpu)
180{ 197{
181 struct clock_event_device *ce = &msm_clockevent;
182 struct clocksource *cs = &msm_clocksource; 198 struct clocksource *cs = &msm_clocksource;
183 int res; 199 int res = 0;
200
201 msm_timer_irq = irq;
202 msm_timer_has_ppi = percpu;
203
204 msm_evt = alloc_percpu(struct clock_event_device);
205 if (!msm_evt) {
206 pr_err("memory allocation failed for clockevents\n");
207 goto err;
208 }
184 209
185 ce->cpumask = cpumask_of(0); 210 if (percpu)
186 ce->irq = irq; 211 res = request_percpu_irq(irq, msm_timer_interrupt,
212 "gp_timer", msm_evt);
187 213
188 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); 214 if (res) {
189 if (percpu) { 215 pr_err("request_percpu_irq failed\n");
190 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); 216 } else {
191 if (!msm_evt.percpu_evt) { 217 res = register_cpu_notifier(&msm_timer_cpu_nb);
192 pr_err("memory allocation failed for %s\n", ce->name); 218 if (res) {
219 free_percpu_irq(irq, msm_evt);
193 goto err; 220 goto err;
194 } 221 }
195 *__this_cpu_ptr(msm_evt.percpu_evt) = ce; 222
196 res = request_percpu_irq(ce->irq, msm_timer_interrupt, 223 /* Immediately configure the timer on the boot CPU */
197 ce->name, msm_evt.percpu_evt); 224 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
198 if (!res) {
199 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
200#ifdef CONFIG_LOCAL_TIMERS
201 local_timer_register(&msm_local_timer_ops);
202#endif
203 }
204 } else {
205 msm_evt.evt = ce;
206 res = request_irq(ce->irq, msm_timer_interrupt,
207 IRQF_TIMER | IRQF_NOBALANCING |
208 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
209 } 225 }
210 226
211 if (res)
212 pr_err("request_irq failed for %s\n", ce->name);
213err: 227err:
214 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); 228 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
215 res = clocksource_register_hz(cs, dgt_hz); 229 res = clocksource_register_hz(cs, dgt_hz);
@@ -219,15 +233,8 @@ err:
219} 233}
220 234
221#ifdef CONFIG_OF 235#ifdef CONFIG_OF
222static const struct of_device_id msm_timer_match[] __initconst = { 236static void __init msm_dt_timer_init(struct device_node *np)
223 { .compatible = "qcom,kpss-timer" },
224 { .compatible = "qcom,scss-timer" },
225 { },
226};
227
228void __init msm_dt_timer_init(void)
229{ 237{
230 struct device_node *np;
231 u32 freq; 238 u32 freq;
232 int irq; 239 int irq;
233 struct resource res; 240 struct resource res;
@@ -235,12 +242,6 @@ void __init msm_dt_timer_init(void)
235 void __iomem *base; 242 void __iomem *base;
236 void __iomem *cpu0_base; 243 void __iomem *cpu0_base;
237 244
238 np = of_find_matching_node(NULL, msm_timer_match);
239 if (!np) {
240 pr_err("Can't find msm timer DT node\n");
241 return;
242 }
243
244 base = of_iomap(np, 0); 245 base = of_iomap(np, 0);
245 if (!base) { 246 if (!base) {
246 pr_err("Failed to map event base\n"); 247 pr_err("Failed to map event base\n");
@@ -283,6 +284,8 @@ void __init msm_dt_timer_init(void)
283 284
284 msm_timer_init(freq, 32, irq, !!percpu_offset); 285 msm_timer_init(freq, 32, irq, !!percpu_offset);
285} 286}
287CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
288CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
286#endif 289#endif
287 290
288static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, 291static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 09:45:23 -0500