12 files changed, 56 insertions, 162 deletions

diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index f81ef1f9d46f..a60ab6d04ec5 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -93,7 +93,7 @@ static void __init halibut_map_io(void)
 }
 
 MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .fixup          = halibut_fixup,
         .map_io         = halibut_map_io,
         .init_irq       = halibut_init_irq,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 1df15aa3c66d..5a4882fc6f7a 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -74,7 +74,7 @@ static void __init mahimahi_map_io(void)
 extern struct sys_timer msm_timer;
 
 MACHINE_START(MAHIMAHI, "mahimahi")
-        .boot_params    = 0x20000100,
+        .atag_offset    = 0x100,
         .fixup          = mahimahi_fixup,
         .map_io         = mahimahi_map_io,
         .init_irq       = msm_init_irq,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 1a313e10c68a..6d84ee740df4 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -129,7 +129,7 @@ static void __init msm7x2x_map_io(void)
 }
 
 MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -137,7 +137,7 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -145,7 +145,7 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
@@ -153,7 +153,7 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .map_io         = msm7x2x_map_io,
         .init_irq       = msm7x2x_init_irq,
         .init_machine   = msm7x2x_init,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 9043417ea52f..71de5062c71e 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -121,7 +121,7 @@ static void __init msm7x30_map_io(void)
 }
 
 MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .fixup = msm7x30_fixup,
         .reserve = msm7x30_reserve,
         .map_io = msm7x30_map_io,
@@ -131,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .fixup = msm7x30_fixup,
         .reserve = msm7x30_reserve,
         .map_io = msm7x30_map_io,
@@ -141,7 +141,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
 MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .fixup = msm7x30_fixup,
         .reserve = msm7x30_reserve,
         .map_io = msm7x30_map_io,
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 9221f54778be..106170fb1844 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -53,8 +53,6 @@ static void __init msm8x60_map_io(void)
 
 static void __init msm8x60_init_irq(void)
 {
-        unsigned int i;
-
         gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
                  (void *)MSM_QGIC_CPU_BASE);
 
@@ -66,15 +64,6 @@ static void __init msm8x60_init_irq(void)
          */
         if (!machine_is_msm8x60_sim())
                 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-         * as they are configured as level, which does not play nice with
-         * handle_percpu_irq.
-         */
-        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        irq_set_handler(i, handle_percpu_irq);
-        }
 }
 
 static void __init msm8x60_init(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 24e9b89738ef..7e8909c978c3 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -192,7 +192,7 @@ static void __init qsd8x50_init(void)
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
@@ -200,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
 MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
-        .boot_params = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset = 0x100,
         .map_io = qsd8x50_map_io,
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 11c1e75ebb1b..32b465763dbd 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -104,7 +104,7 @@ static void __init sapphire_map_io(void)
 
 MACHINE_START(SAPPHIRE, "sapphire")
 /* Maintainer: Brian Swetland <swetland@google.com> */
-        .boot_params    = PLAT_PHYS_OFFSET + 0x100,
+        .atag_offset    = 0x100,
         .fixup          = sapphire_fixup,
         .map_io         = sapphire_map_io,
         .init_irq       = sapphire_init_irq,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 7acd2021ada9..6b9b227c87c5 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -93,7 +93,7 @@ static void __init trout_map_io(void)
 }
 
 MACHINE_START(TROUT, "HTC Dream")
-        .boot_params    = 0x10000100,
+        .atag_offset    = 0x100,
         .fixup          = trout_fixup,
         .map_io         = trout_map_io,
         .init_irq       = trout_init_irq,
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 646b99ebc773..2dc73ccddb11 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
 #include <mach/msm_iomap.h>
 
 #if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
-        .macro  addruart, rp, rv
+        .macro  addruart, rp, rv, tmp
         ldr     \rp, =MSM_DEBUG_UART_PHYS
         ldr     \rv, =MSM_DEBUG_UART_BASE
         .endm
@@ -37,7 +37,7 @@
         beq     1001b
         .endm
 #else
-        .macro  addruart, rp, rv
+        .macro  addruart, rp, rv, tmp
         mov     \rv, #0xff000000
         orr     \rv, \rv, #0x00f00000
         .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
index 12467157afb9..717076f3ca73 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -8,81 +8,10 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
         .macro  disable_fiq
         .endm
 
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
-
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Migrated the code from ARM MP port to be more consistent
-         * with interrupt processing , the following still holds true
-         * however, all interrupts are treated the same regardless of
-         * if they are local IPI or PPI
-         *
-         * Interrupts 0-15 are IPI
-         * 16-31 are PPI
-         *   (16-18 are the timers)
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * A simple read from the controller will tell us the number of the
-         * highest priority enabled interrupt.  We then just need to check
-         * whether it is in the valid range for an IRQ (0-1020 inclusive).
-         *
-         * Base ARM code assumes that the local (private) peripheral interrupts
-         * are not valid, we treat them differently, in that the privates are
-         * handled like normal shared interrupts with the exception that only
-         * one processor can register the interrupt and the handler must be
-         * the same for all processors.
-         */
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-        ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
-                                                   9-0 =int # */
-
-        bic     \irqnr, \irqstat, #0x1c00       @mask src
-        cmp     \irqnr, #15
-        ldr             \tmp, =1021
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-
-        .endm
-
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    cmp \irqnr, #16
-    strcc   \irqstat, [\base, #GIC_CPU_EOI]
-    cmpcs   \irqnr, \irqnr
-        .endm
-
-        /* As above, this assumes that irqstat and base are preserved.. */
-
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    mov     \tmp, #0
-    cmp \irqnr, #16
-    moveq   \tmp, #1
-    streq   \irqstat, [\base, #GIC_CPU_EOI]
-    cmp \tmp, #0
-        .endm
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
deleted file mode 100644
index 58d5e7eec431..000000000000
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* arch/arm/mach-msm/include/mach/memory.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/* physical offset of RAM */
-#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
-#define PLAT_PHYS_OFFSET                UL(0x00000000)
-#elif defined(CONFIG_ARCH_QSD8X50)
-#define PLAT_PHYS_OFFSET                UL(0x20000000)
-#elif defined(CONFIG_ARCH_MSM7X30)
-#define PLAT_PHYS_OFFSET                UL(0x00000000)
-#elif defined(CONFIG_ARCH_MSM8X60)
-#define PLAT_PHYS_OFFSET                UL(0x40000000)
-#elif defined(CONFIG_ARCH_MSM8960)
-#define PLAT_PHYS_OFFSET                UL(0x40000000)
-#else
-#define PLAT_PHYS_OFFSET                UL(0x10000000)
-#endif
-
-#endif
-
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 63621f152c98..afeeca52fc66 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -71,12 +71,16 @@ enum timer_location {
 struct msm_clock {
         struct clock_event_device   clockevent;
         struct clocksource          clocksource;
-        struct irqaction            irq;
+        unsigned int                irq;
         void __iomem                *regbase;
         uint32_t                    freq;
         uint32_t                    shift;
         void __iomem                *global_counter;
         void __iomem                *local_counter;
+        union {
+                struct clock_event_device               *evt;
+                struct clock_event_device __percpu      **percpu_evt;
+        };              
 };
 
 enum {
@@ -87,13 +91,10 @@ enum {
 
 
 static struct msm_clock msm_clocks[];
-static struct clock_event_device *local_clock_event;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = dev_id;
-        if (smp_processor_id() != 0)
-                evt = local_clock_event;
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
         if (evt->event_handler == NULL)
                 return IRQ_HANDLED;
         evt->event_handler(evt);
@@ -171,13 +172,7 @@ static struct msm_clock msm_clocks[] = {
                         .mask           = CLOCKSOURCE_MASK(32),
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
-                .irq = {
-                        .name    = "gp_timer",
-                        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-                        .handler = msm_timer_interrupt,
-                        .dev_id  = &msm_clocks[0].clockevent,
-                        .irq     = INT_GP_TIMER_EXP
-                },
+                .irq = INT_GP_TIMER_EXP,
                 .freq = GPT_HZ,
         },
         [MSM_CLOCK_DGT] = {
@@ -196,13 +191,7 @@ static struct msm_clock msm_clocks[] = {
                         .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
-                .irq = {
-                        .name    = "dg_timer",
-                        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-                        .handler = msm_timer_interrupt,
-                        .dev_id  = &msm_clocks[1].clockevent,
-                        .irq     = INT_DEBUG_TIMER_EXP
-                },
+                .irq = INT_DEBUG_TIMER_EXP,
                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
                 .shift = MSM_DGT_SHIFT,
         }
@@ -261,10 +250,30 @@ static void __init msm_timer_init(void)
                         printk(KERN_ERR "msm_timer_init: clocksource_register "
                                "failed for %s\n", cs->name);
 
-                res = setup_irq(clock->irq.irq, &clock->irq);
+                ce->irq = clock->irq;
+                if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+                        clock->percpu_evt = alloc_percpu(struct clock_event_device *);
+                        if (!clock->percpu_evt) {
+                                pr_err("msm_timer_init: memory allocation "
+                                       "failed for %s\n", ce->name);
+                                continue;
+                        }
+
+                        *__this_cpu_ptr(clock->percpu_evt) = ce;
+                        res = request_percpu_irq(ce->irq, msm_timer_interrupt,
+                                                 ce->name, clock->percpu_evt);
+                        if (!res)
+                                enable_percpu_irq(ce->irq, 0);
+                } else {
+                        clock->evt = ce;
+                        res = request_irq(ce->irq, msm_timer_interrupt,
+                                          IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
+                                          ce->name, &clock->evt);
+                }
+
                 if (res)
-                        printk(KERN_ERR "msm_timer_init: setup_irq "
-                               "failed for %s\n", cs->name);
+                        pr_err("msm_timer_init: request_irq failed for %s\n",
+                               ce->name);
 
                 clockevents_register_device(ce);
         }
@@ -273,6 +282,7 @@ static void __init msm_timer_init(void)
 #ifdef CONFIG_SMP
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
+        static bool local_timer_inited;
         struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
 
         /* Use existing clock_event for cpu 0 */
@@ -281,12 +291,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 
         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 
-        if (!local_clock_event) {
+        if (!local_timer_inited) {
                 writel(0, clock->regbase  + TIMER_ENABLE);
                 writel(0, clock->regbase + TIMER_CLEAR);
                 writel(~0, clock->regbase + TIMER_MATCH_VAL);
+                local_timer_inited = true;
         }
-        evt->irq = clock->irq.irq;
+        evt->irq = clock->irq;
         evt->name = "local_timer";
         evt->features = CLOCK_EVT_FEAT_ONESHOT;
         evt->rating = clock->clockevent.rating;
@@ -298,17 +309,17 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
                 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 
-        local_clock_event = evt;
-
-        gic_enable_ppi(clock->irq.irq);
+        *__this_cpu_ptr(clock->percpu_evt) = evt;
+        enable_percpu_irq(evt->irq, 0);
 
         clockevents_register_device(evt);
         return 0;
 }
 
-inline int local_timer_ack(void)
+void local_timer_stop(struct clock_event_device *evt)
 {
-        return 1;
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        disable_percpu_irq(evt->irq);
 }
 
 #endif