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-rw-r--r--arch/arm/mach-msm/Kconfig41
-rw-r--r--arch/arm/mach-msm/Makefile8
-rw-r--r--arch/arm/mach-msm/Makefile.boot3
-rw-r--r--arch/arm/mach-msm/acpuclock-arm11.c525
-rw-r--r--arch/arm/mach-msm/acpuclock.h32
-rw-r--r--arch/arm/mach-msm/board-dt-8660.c63
-rw-r--r--arch/arm/mach-msm/board-dt-8960.c49
-rw-r--r--arch/arm/mach-msm/board-halibut.c5
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c1
-rw-r--r--arch/arm/mach-msm/board-msm7x27.c170
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c9
-rw-r--r--arch/arm/mach-msm/board-msm8960.c122
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c166
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c7
-rw-r--r--arch/arm/mach-msm/board-sapphire.c1
-rw-r--r--arch/arm/mach-msm/board-trout.c5
-rw-r--r--arch/arm/mach-msm/clock-pcom.c18
-rw-r--r--arch/arm/mach-msm/common.h30
-rw-r--r--arch/arm/mach-msm/devices-msm8960.c85
-rw-r--r--arch/arm/mach-msm/dma.c3
-rw-r--r--arch/arm/mach-msm/idle.c49
-rw-r--r--arch/arm/mach-msm/include/mach/board.h13
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h7
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h4
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h6
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h4
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h6
-rw-r--r--arch/arm/mach-msm/include/mach/system.h19
-rw-r--r--arch/arm/mach-msm/io.c30
-rw-r--r--arch/arm/mach-msm/platsmp.c8
-rw-r--r--arch/arm/mach-msm/proc_comm.c1
-rw-r--r--arch/arm/mach-msm/smd.c26
-rw-r--r--arch/arm/mach-msm/timer.c188
33 files changed, 349 insertions, 1355 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 03c549369ce3..7902de151cc5 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -44,8 +44,6 @@ endchoice
44 44
45config ARCH_MSM8X60 45config ARCH_MSM8X60
46 bool "MSM8X60" 46 bool "MSM8X60"
47 select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
48 && !MACH_MSM8X60_FFA)
49 select ARCH_MSM_SCORPIONMP 47 select ARCH_MSM_SCORPIONMP
50 select ARM_GIC 48 select ARM_GIC
51 select CPU_V7 49 select CPU_V7
@@ -53,16 +51,17 @@ config ARCH_MSM8X60
53 select GPIO_MSM_V2 51 select GPIO_MSM_V2
54 select MSM_GPIOMUX 52 select MSM_GPIOMUX
55 select MSM_SCM if SMP 53 select MSM_SCM if SMP
54 select USE_OF
56 55
57config ARCH_MSM8960 56config ARCH_MSM8960
58 bool "MSM8960" 57 bool "MSM8960"
59 select ARCH_MSM_SCORPIONMP 58 select ARCH_MSM_SCORPIONMP
60 select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
61 select ARM_GIC 59 select ARM_GIC
62 select CPU_V7 60 select CPU_V7
63 select MSM_V2_TLMM 61 select MSM_V2_TLMM
64 select MSM_GPIOMUX 62 select MSM_GPIOMUX
65 select MSM_SCM if SMP 63 select MSM_SCM if SMP
64 select USE_OF
66 65
67config MSM_HAS_DEBUG_UART_HS 66config MSM_HAS_DEBUG_UART_HS
68 bool 67 bool
@@ -116,42 +115,6 @@ config MACH_QSD8X50A_ST1_5
116 help 115 help
117 Support for the Qualcomm ST1.5. 116 Support for the Qualcomm ST1.5.
118 117
119config MACH_MSM8X60_RUMI3
120 depends on ARCH_MSM8X60
121 bool "MSM8x60 RUMI3"
122 help
123 Support for the Qualcomm MSM8x60 RUMI3 emulator.
124
125config MACH_MSM8X60_SURF
126 depends on ARCH_MSM8X60
127 bool "MSM8x60 SURF"
128 help
129 Support for the Qualcomm MSM8x60 SURF eval board.
130
131config MACH_MSM8X60_SIM
132 depends on ARCH_MSM8X60
133 bool "MSM8x60 Simulator"
134 help
135 Support for the Qualcomm MSM8x60 simulator.
136
137config MACH_MSM8X60_FFA
138 depends on ARCH_MSM8X60
139 bool "MSM8x60 FFA"
140 help
141 Support for the Qualcomm MSM8x60 FFA eval board.
142
143config MACH_MSM8960_SIM
144 depends on ARCH_MSM8960
145 bool "MSM8960 Simulator"
146 help
147 Support for the Qualcomm MSM8960 simulator.
148
149config MACH_MSM8960_RUMI3
150 depends on ARCH_MSM8960
151 bool "MSM8960 RUMI3"
152 help
153 Support for the Qualcomm MSM8960 RUMI3 emulator.
154
155endmenu 118endmenu
156 119
157config MSM_SMD_PKG3 120config MSM_SMD_PKG3
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969b9881..17519faf082f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,11 +1,11 @@
1obj-y += io.o idle.o timer.o 1obj-y += io.o timer.o
2obj-y += clock.o 2obj-y += clock.o
3obj-$(CONFIG_DEBUG_FS) += clock-debug.o 3obj-$(CONFIG_DEBUG_FS) += clock-debug.o
4 4
5obj-$(CONFIG_MSM_VIC) += irq-vic.o 5obj-$(CONFIG_MSM_VIC) += irq-vic.o
6obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o 6obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
7 7
8obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o 8obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
9obj-$(CONFIG_ARCH_MSM7X30) += dma.o 9obj-$(CONFIG_ARCH_MSM7X30) += dma.o
10obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o 10obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
11 11
@@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
25obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 25obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
26obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 26obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
27obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 27obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
28obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o 28obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
29obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o 29obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
30 30
31obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o 31obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
32obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o 32obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index 9b803a578b4d..f7d6ae9c3487 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -1,3 +1,6 @@
1 zreladdr-y += 0x10008000 1 zreladdr-y += 0x10008000
2params_phys-y := 0x10000100 2params_phys-y := 0x10000100
3initrd_phys-y := 0x10800000 3initrd_phys-y := 0x10800000
4
5dtb-$(CONFIG_ARCH_MSM8X60) += msm8660-surf.dtb
6dtb-$(CONFIG_ARCH_MSM8960) += msm8960-cdp.dtb
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644
index 805d4ee53f7e..000000000000
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ /dev/null
@@ -1,525 +0,0 @@
1/* arch/arm/mach-msm/acpuclock.c
2 *
3 * MSM architecture clock driver
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28#include <linux/mutex.h>
29#include <linux/io.h>
30#include <mach/board.h>
31#include <mach/msm_iomap.h>
32
33#include "proc_comm.h"
34#include "acpuclock.h"
35
36
37#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
38#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
39#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
40
41/*
42 * ARM11 clock configuration for specific ACPU speeds
43 */
44
45#define ACPU_PLL_TCXO -1
46#define ACPU_PLL_0 0
47#define ACPU_PLL_1 1
48#define ACPU_PLL_2 2
49#define ACPU_PLL_3 3
50
51#define PERF_SWITCH_DEBUG 0
52#define PERF_SWITCH_STEP_DEBUG 0
53
54struct clock_state
55{
56 struct clkctl_acpu_speed *current_speed;
57 struct mutex lock;
58 uint32_t acpu_switch_time_us;
59 uint32_t max_speed_delta_khz;
60 uint32_t vdd_switch_time_us;
61 unsigned long power_collapse_khz;
62 unsigned long wait_for_irq_khz;
63};
64
65static struct clk *ebi1_clk;
66static struct clock_state drv_state = { 0 };
67
68static void __init acpuclk_init(void);
69
70/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
71enum {
72 VDD_0 = 0,
73 VDD_1 = 1,
74 VDD_2 = 2,
75 VDD_3 = 3,
76 VDD_4 = 3,
77 VDD_5 = 3,
78 VDD_6 = 3,
79 VDD_7 = 7,
80 VDD_END
81};
82
83struct clkctl_acpu_speed {
84 unsigned int a11clk_khz;
85 int pll;
86 unsigned int a11clk_src_sel;
87 unsigned int a11clk_src_div;
88 unsigned int ahbclk_khz;
89 unsigned int ahbclk_div;
90 int vdd;
91 unsigned int axiclk_khz;
92 unsigned long lpj; /* loops_per_jiffy */
93/* Index in acpu_freq_tbl[] for steppings. */
94 short down;
95 short up;
96};
97
98/*
99 * ACPU speed table. Complete table is shown but certain speeds are commented
100 * out to optimized speed switching. Initialize loops_per_jiffy to 0.
101 *
102 * Table stepping up/down is optimized for 256mhz jumps while staying on the
103 * same PLL.
104 */
105#if (0)
106static struct clkctl_acpu_speed acpu_freq_tbl[] = {
107 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
108 { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
109 { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
110 { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
111 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
112 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
113 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
114 { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
115 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
116 { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
117 { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
118 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
119 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
120 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
121 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
122};
123#else /* Table of freq we currently use. */
124static struct clkctl_acpu_speed acpu_freq_tbl[] = {
125 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
126 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
127 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
128 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
129 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
130 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
131 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
132 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
133 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
134};
135#endif
136
137
138#ifdef CONFIG_CPU_FREQ_TABLE
139static struct cpufreq_frequency_table freq_table[] = {
140 { 0, 122880 },
141 { 1, 128000 },
142 { 2, 245760 },
143 { 3, 384000 },
144 { 4, 528000 },
145 { 5, CPUFREQ_TABLE_END },
146};
147#endif
148
149static int pc_pll_request(unsigned id, unsigned on)
150{
151 int res;
152 on = !!on;
153
154#if PERF_SWITCH_DEBUG
155 if (on)
156 printk(KERN_DEBUG "Enabling PLL %d\n", id);
157 else
158 printk(KERN_DEBUG "Disabling PLL %d\n", id);
159#endif
160
161 res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
162 if (res < 0)
163 return res;
164
165#if PERF_SWITCH_DEBUG
166 if (on)
167 printk(KERN_DEBUG "PLL %d enabled\n", id);
168 else
169 printk(KERN_DEBUG "PLL %d disabled\n", id);
170#endif
171 return res;
172}
173
174
175/*----------------------------------------------------------------------------
176 * ARM11 'owned' clock control
177 *---------------------------------------------------------------------------*/
178
179unsigned long acpuclk_power_collapse(void) {
180 int ret = acpuclk_get_rate();
181 ret *= 1000;
182 if (ret > drv_state.power_collapse_khz)
183 acpuclk_set_rate(drv_state.power_collapse_khz, 1);
184 return ret;
185}
186
187unsigned long acpuclk_get_wfi_rate(void)
188{
189 return drv_state.wait_for_irq_khz;
190}
191
192unsigned long acpuclk_wait_for_irq(void) {
193 int ret = acpuclk_get_rate();
194 ret *= 1000;
195 if (ret > drv_state.wait_for_irq_khz)
196 acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
197 return ret;
198}
199
200static int acpuclk_set_vdd_level(int vdd)
201{
202 uint32_t current_vdd;
203
204 current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
205
206#if PERF_SWITCH_DEBUG
207 printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
208 current_vdd, vdd);
209#endif
210 writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
211 udelay(drv_state.vdd_switch_time_us);
212 if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
213#if PERF_SWITCH_DEBUG
214 printk(KERN_ERR "acpuclock: VDD set failed\n");
215#endif
216 return -EIO;
217 }
218
219#if PERF_SWITCH_DEBUG
220 printk(KERN_DEBUG "acpuclock: VDD switched\n");
221#endif
222 return 0;
223}
224
225/* Set proper dividers for the given clock speed. */
226static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
227 uint32_t reg_clkctl, reg_clksel, clk_div;
228
229 /* AHB_CLK_DIV */
230 clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
231 /*
232 * If the new clock divider is higher than the previous, then
233 * program the divider before switching the clock
234 */
235 if (hunt_s->ahbclk_div > clk_div) {
236 reg_clksel = readl(A11S_CLK_SEL_ADDR);
237 reg_clksel &= ~(0x3 << 1);
238 reg_clksel |= (hunt_s->ahbclk_div << 1);
239 writel(reg_clksel, A11S_CLK_SEL_ADDR);
240 }
241 if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
242 /* SRC0 */
243
244 /* Program clock source */
245 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
246 reg_clkctl &= ~(0x07 << 4);
247 reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
248 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
249
250 /* Program clock divider */
251 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
252 reg_clkctl &= ~0xf;
253 reg_clkctl |= hunt_s->a11clk_src_div;
254 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
255
256 /* Program clock source selection */
257 reg_clksel = readl(A11S_CLK_SEL_ADDR);
258 reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
259 writel(reg_clksel, A11S_CLK_SEL_ADDR);
260 } else {
261 /* SRC1 */
262
263 /* Program clock source */
264 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
265 reg_clkctl &= ~(0x07 << 12);
266 reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
267 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
268
269 /* Program clock divider */
270 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
271 reg_clkctl &= ~(0xf << 8);
272 reg_clkctl |= (hunt_s->a11clk_src_div << 8);
273 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
274
275 /* Program clock source selection */
276 reg_clksel = readl(A11S_CLK_SEL_ADDR);
277 reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
278 writel(reg_clksel, A11S_CLK_SEL_ADDR);
279 }
280
281 /*
282 * If the new clock divider is lower than the previous, then
283 * program the divider after switching the clock
284 */
285 if (hunt_s->ahbclk_div < clk_div) {
286 reg_clksel = readl(A11S_CLK_SEL_ADDR);
287 reg_clksel &= ~(0x3 << 1);
288 reg_clksel |= (hunt_s->ahbclk_div << 1);
289 writel(reg_clksel, A11S_CLK_SEL_ADDR);
290 }
291}
292
293int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
294{
295 uint32_t reg_clkctl;
296 struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
297 int rc = 0;
298 unsigned int plls_enabled = 0, pll;
299
300 strt_s = cur_s = drv_state.current_speed;
301
302 WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
303 if (cur_s == NULL)
304 return -ENOENT;
305
306 if (rate == (cur_s->a11clk_khz * 1000))
307 return 0;
308
309 for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
310 if (tgt_s->a11clk_khz == (rate / 1000))
311 break;
312 }
313
314 if (tgt_s->a11clk_khz == 0)
315 return -EINVAL;
316
317 /* Choose the highest speed speed at or below 'rate' with same PLL. */
318 if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
319 while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
320 tgt_s--;
321 }
322
323 if (strt_s->pll != ACPU_PLL_TCXO)
324 plls_enabled |= 1 << strt_s->pll;
325
326 if (!for_power_collapse) {
327 mutex_lock(&drv_state.lock);
328 if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
329 rc = pc_pll_request(tgt_s->pll, 1);
330 if (rc < 0) {
331 pr_err("PLL%d enable failed (%d)\n",
332 tgt_s->pll, rc);
333 goto out;
334 }
335 plls_enabled |= 1 << tgt_s->pll;
336 }
337 /* Increase VDD if needed. */
338 if (tgt_s->vdd > cur_s->vdd) {
339 if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
340 printk(KERN_ERR "Unable to switch ACPU vdd\n");
341 goto out;
342 }
343 }
344 }
345
346 /* Set wait states for CPU between frequency changes */
347 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
348 reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
349 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
350
351#if PERF_SWITCH_DEBUG
352 printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
353 strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
354#endif
355
356 while (cur_s != tgt_s) {
357 /*
358 * Always jump to target freq if within 256mhz, regulardless of
359 * PLL. If differnece is greater, use the predefinied
360 * steppings in the table.
361 */
362 int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
363 if (d > drv_state.max_speed_delta_khz) {
364 /* Step up or down depending on target vs current. */
365 int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
366 cur_s->up : cur_s->down;
367 if (clk_index < 0) { /* This should not happen. */
368 printk(KERN_ERR "cur:%u target: %u\n",
369 cur_s->a11clk_khz, tgt_s->a11clk_khz);
370 rc = -EINVAL;
371 goto out;
372 }
373 cur_s = &acpu_freq_tbl[clk_index];
374 } else {
375 cur_s = tgt_s;
376 }
377#if PERF_SWITCH_STEP_DEBUG
378 printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
379 __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
380#endif
381 if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
382 && !(plls_enabled & (1 << cur_s->pll))) {
383 rc = pc_pll_request(cur_s->pll, 1);
384 if (rc < 0) {
385 pr_err("PLL%d enable failed (%d)\n",
386 cur_s->pll, rc);
387 goto out;
388 }
389 plls_enabled |= 1 << cur_s->pll;
390 }
391
392 acpuclk_set_div(cur_s);
393 drv_state.current_speed = cur_s;
394 /* Re-adjust lpj for the new clock speed. */
395 loops_per_jiffy = cur_s->lpj;
396 udelay(drv_state.acpu_switch_time_us);
397 }
398
399 /* Nothing else to do for power collapse. */
400 if (for_power_collapse)
401 return 0;
402
403 /* Disable PLLs we are not using anymore. */
404 plls_enabled &= ~(1 << tgt_s->pll);
405 for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
406 if (plls_enabled & (1 << pll)) {
407 rc = pc_pll_request(pll, 0);
408 if (rc < 0) {
409 pr_err("PLL%d disable failed (%d)\n", pll, rc);
410 goto out;
411 }
412 }
413
414 /* Change the AXI bus frequency if we can. */
415 if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
416 rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
417 if (rc < 0)
418 pr_err("Setting AXI min rate failed!\n");
419 }
420
421 /* Drop VDD level if we can. */
422 if (tgt_s->vdd < strt_s->vdd) {
423 if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
424 printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
425 }
426
427#if PERF_SWITCH_DEBUG
428 printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
429#endif
430out:
431 if (!for_power_collapse)
432 mutex_unlock(&drv_state.lock);
433 return rc;
434}
435
436static void __init acpuclk_init(void)
437{
438 struct clkctl_acpu_speed *speed;
439 uint32_t div, sel;
440 int rc;
441
442 /*
443 * Determine the rate of ACPU clock
444 */
445
446 if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
447 /* CLK_SRC0_SEL */
448 sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
449 /* CLK_SRC0_DIV */
450 div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
451 } else {
452 /* CLK_SRC1_SEL */
453 sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
454 /* CLK_SRC1_DIV */
455 div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
456 }
457
458 for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
459 if (speed->a11clk_src_sel == sel
460 && (speed->a11clk_src_div == div))
461 break;
462 }
463 if (speed->a11clk_khz == 0) {
464 printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
465 return;
466 }
467
468 drv_state.current_speed = speed;
469
470 rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
471 if (rc < 0)
472 pr_err("Setting AXI min rate failed!\n");
473
474 printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
475}
476
477unsigned long acpuclk_get_rate(void)
478{
479 WARN_ONCE(drv_state.current_speed == NULL,
480 "acpuclk_get_rate: not initialized\n");
481 if (drv_state.current_speed)
482 return drv_state.current_speed->a11clk_khz;
483 else
484 return 0;
485}
486
487uint32_t acpuclk_get_switch_time(void)
488{
489 return drv_state.acpu_switch_time_us;
490}
491
492/*----------------------------------------------------------------------------
493 * Clock driver initialization
494 *---------------------------------------------------------------------------*/
495
496/* Initialize the lpj field in the acpu_freq_tbl. */
497static void __init lpj_init(void)
498{
499 int i;
500 const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
501 for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
502 acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
503 base_clk->a11clk_khz,
504 acpu_freq_tbl[i].a11clk_khz);
505 }
506}
507
508void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
509{
510 pr_info("acpu_clock_init()\n");
511
512 ebi1_clk = clk_get(NULL, "ebi1_clk");
513
514 mutex_init(&drv_state.lock);
515 drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
516 drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
517 drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
518 drv_state.power_collapse_khz = clkdata->power_collapse_khz;
519 drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
520 acpuclk_init();
521 lpj_init();
522#ifdef CONFIG_CPU_FREQ_TABLE
523 cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
524#endif
525}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644
index 415de2eb9a5e..000000000000
--- a/arch/arm/mach-msm/acpuclock.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/* arch/arm/mach-msm/acpuclock.h
2 *
3 * MSM architecture clock driver header
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
21#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
22
23int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
24unsigned long acpuclk_get_rate(void);
25uint32_t acpuclk_get_switch_time(void);
26unsigned long acpuclk_wait_for_irq(void);
27unsigned long acpuclk_power_collapse(void);
28unsigned long acpuclk_get_wfi_rate(void);
29
30
31#endif
32
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
new file mode 100644
index 000000000000..f77f57f39104
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -0,0 +1,63 @@
1/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/of.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17
18#include <asm/mach/arch.h>
19#include <asm/hardware/gic.h>
20
21#include <mach/board.h>
22#include "common.h"
23
24static const struct of_device_id msm_dt_gic_match[] __initconst = {
25 { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
26 {}
27};
28
29static void __init msm8x60_init_irq(void)
30{
31 of_irq_init(msm_dt_gic_match);
32}
33
34static void __init msm8x60_init_late(void)
35{
36 smd_debugfs_init();
37}
38
39static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
40 {}
41};
42
43static void __init msm8x60_dt_init(void)
44{
45 of_platform_populate(NULL, of_default_bus_match_table,
46 msm_auxdata_lookup, NULL);
47}
48
49static const char *msm8x60_fluid_match[] __initdata = {
50 "qcom,msm8660-fluid",
51 "qcom,msm8660-surf",
52 NULL
53};
54
55DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
56 .map_io = msm_map_msm8x60_io,
57 .init_irq = msm8x60_init_irq,
58 .handle_irq = gic_handle_irq,
59 .init_machine = msm8x60_dt_init,
60 .init_late = msm8x60_init_late,
61 .timer = &msm_dt_timer,
62 .dt_compat = msm8x60_fluid_match,
63MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
new file mode 100644
index 000000000000..8df99b8f3c92
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -0,0 +1,49 @@
1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16
17#include <asm/hardware/gic.h>
18#include <asm/mach/arch.h>
19
20#include "common.h"
21
22static const struct of_device_id msm_dt_gic_match[] __initconst = {
23 { .compatible = "qcom,msm-qgic2", .data = gic_of_init },
24 { }
25};
26
27static void __init msm_dt_init_irq(void)
28{
29 of_irq_init(msm_dt_gic_match);
30}
31
32static void __init msm_dt_init(void)
33{
34 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
35}
36
37static const char * const msm8960_dt_match[] __initconst = {
38 "qcom,msm8960-cdp",
39 NULL
40};
41
42DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
43 .map_io = msm_map_msm8960_io,
44 .init_irq = msm_dt_init_irq,
45 .timer = &msm_dt_timer,
46 .init_machine = msm_dt_init,
47 .dt_compat = msm8960_dt_match,
48 .handle_irq = gic_handle_irq,
49MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 4fa3e99d9a62..6ce542e2e21c 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -36,6 +36,7 @@
36#include <linux/mtd/partitions.h> 36#include <linux/mtd/partitions.h>
37 37
38#include "devices.h" 38#include "devices.h"
39#include "common.h"
39 40
40static struct resource smc91x_resources[] = { 41static struct resource smc91x_resources[] = {
41 [0] = { 42 [0] = {
@@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = {
66 &smc91x_device, 67 &smc91x_device,
67}; 68};
68 69
69extern struct sys_timer msm_timer;
70
71static void __init halibut_init_early(void) 70static void __init halibut_init_early(void)
72{ 71{
73 arch_ioremap_caller = __msm_ioremap_caller; 72 arch_ioremap_caller = __msm_ioremap_caller;
@@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
107 .init_irq = halibut_init_irq, 106 .init_irq = halibut_init_irq,
108 .init_machine = halibut_init, 107 .init_machine = halibut_init,
109 .init_late = halibut_init_late, 108 .init_late = halibut_init_late,
110 .timer = &msm_timer, 109 .timer = &msm7x01_timer,
111MACHINE_END 110MACHINE_END
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a5dc62..df00bc03ce74 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
30 30
31#include <mach/board.h> 31#include <mach/board.h>
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/system.h>
34 33
35#include "board-mahimahi.h" 34#include "board-mahimahi.h"
36#include "devices.h" 35#include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644
index 451ab1d43c92..000000000000
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#include <linux/gpio.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/input.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/power_supply.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30#include <asm/setup.h>
31#ifdef CONFIG_CACHE_L2X0
32#include <asm/hardware/cache-l2x0.h>
33#endif
34
35#include <mach/vreg.h>
36#include <mach/mpp.h>
37#include <mach/board.h>
38#include <mach/msm_iomap.h>
39
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
43#include "devices.h"
44#include "socinfo.h"
45#include "clock.h"
46
47static struct resource smc91x_resources[] = {
48 [0] = {
49 .start = 0x9C004300,
50 .end = 0x9C0043ff,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = MSM_GPIO_TO_INT(132),
55 .end = MSM_GPIO_TO_INT(132),
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
60static struct platform_device smc91x_device = {
61 .name = "smc91x",
62 .id = 0,
63 .num_resources = ARRAY_SIZE(smc91x_resources),
64 .resource = smc91x_resources,
65};
66
67static struct platform_device *devices[] __initdata = {
68 &msm_device_uart3,
69 &msm_device_smd,
70 &msm_device_dmov,
71 &msm_device_nand,
72 &smc91x_device,
73};
74
75extern struct sys_timer msm_timer;
76
77static void __init msm7x2x_init_irq(void)
78{
79 msm_init_irq();
80}
81
82static void __init msm7x2x_init(void)
83{
84 if (socinfo_init() < 0)
85 BUG();
86
87 if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
88 smc91x_resources[0].start = 0x98000300;
89 smc91x_resources[0].end = 0x980003ff;
90 smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
91 smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
92 if (gpio_tlmm_config(GPIO_CFG(85, 0,
93 GPIO_INPUT,
94 GPIO_PULL_DOWN,
95 GPIO_2MA),
96 GPIO_ENABLE)) {
97 printk(KERN_ERR
98 "%s: Err: Config GPIO-85 INT\n",
99 __func__);
100 }
101 }
102
103 platform_add_devices(devices, ARRAY_SIZE(devices));
104}
105
106static void __init msm7x2x_map_io(void)
107{
108 msm_map_common_io();
109 /* Technically dependent on the SoC but using machine_is
110 * macros since socinfo is not available this early and there
111 * are plans to restructure the code which will eliminate the
112 * need for socinfo.
113 */
114 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
115 msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
116
117 if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
118 msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
119
120#ifdef CONFIG_CACHE_L2X0
121 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
122 /* 7x27 has 256KB L2 cache:
123 64Kb/Way and 4-Way Associativity;
124 R/W latency: 3 cycles;
125 evmon/parity/share disabled. */
126 l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
127 }
128#endif
129}
130
131static void __init msm7x2x_init_late(void)
132{
133 smd_debugfs_init();
134}
135
136MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
137 .atag_offset = 0x100,
138 .map_io = msm7x2x_map_io,
139 .init_irq = msm7x2x_init_irq,
140 .init_machine = msm7x2x_init,
141 .init_late = msm7x2x_init_late,
142 .timer = &msm_timer,
143MACHINE_END
144
145MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
146 .atag_offset = 0x100,
147 .map_io = msm7x2x_map_io,
148 .init_irq = msm7x2x_init_irq,
149 .init_machine = msm7x2x_init,
150 .init_late = msm7x2x_init_late,
151 .timer = &msm_timer,
152MACHINE_END
153
154MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
155 .atag_offset = 0x100,
156 .map_io = msm7x2x_map_io,
157 .init_irq = msm7x2x_init_irq,
158 .init_machine = msm7x2x_init,
159 .init_late = msm7x2x_init_late,
160 .timer = &msm_timer,
161MACHINE_END
162
163MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
164 .atag_offset = 0x100,
165 .map_io = msm7x2x_map_io,
166 .init_irq = msm7x2x_init_irq,
167 .init_machine = msm7x2x_init,
168 .init_late = msm7x2x_init_late,
169 .timer = &msm_timer,
170MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index a5001378135d..effa6f4336c7 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -38,8 +38,7 @@
38#include "devices.h" 38#include "devices.h"
39#include "gpiomux.h" 39#include "gpiomux.h"
40#include "proc_comm.h" 40#include "proc_comm.h"
41 41#include "common.h"
42extern struct sys_timer msm_timer;
43 42
44static void __init msm7x30_fixup(struct tag *tag, char **cmdline, 43static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
45 struct meminfo *mi) 44 struct meminfo *mi)
@@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
132 .init_irq = msm7x30_init_irq, 131 .init_irq = msm7x30_init_irq,
133 .init_machine = msm7x30_init, 132 .init_machine = msm7x30_init,
134 .init_late = msm7x30_init_late, 133 .init_late = msm7x30_init_late,
135 .timer = &msm_timer, 134 .timer = &msm7x30_timer,
136MACHINE_END 135MACHINE_END
137 136
138MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") 137MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
143 .init_irq = msm7x30_init_irq, 142 .init_irq = msm7x30_init_irq,
144 .init_machine = msm7x30_init, 143 .init_machine = msm7x30_init,
145 .init_late = msm7x30_init_late, 144 .init_late = msm7x30_init_late,
146 .timer = &msm_timer, 145 .timer = &msm7x30_timer,
147MACHINE_END 146MACHINE_END
148 147
149MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") 148MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
154 .init_irq = msm7x30_init_irq, 153 .init_irq = msm7x30_init_irq,
155 .init_machine = msm7x30_init, 154 .init_machine = msm7x30_init,
156 .init_late = msm7x30_init_late, 155 .init_late = msm7x30_init_late,
157 .timer = &msm_timer, 156 .timer = &msm7x30_timer,
158MACHINE_END 157MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
deleted file mode 100644
index 65f4a1daa2e5..000000000000
--- a/arch/arm/mach-msm/board-msm8960.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/clkdev.h>
23#include <linux/memblock.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/hardware/gic.h>
28#include <asm/setup.h>
29
30#include <mach/board.h>
31#include <mach/msm_iomap.h>
32
33#include "devices.h"
34
35static void __init msm8960_fixup(struct tag *tag, char **cmdline,
36 struct meminfo *mi)
37{
38 for (; tag->hdr.size; tag = tag_next(tag))
39 if (tag->hdr.tag == ATAG_MEM &&
40 tag->u.mem.start == 0x40200000) {
41 tag->u.mem.start = 0x40000000;
42 tag->u.mem.size += SZ_2M;
43 }
44}
45
46static void __init msm8960_reserve(void)
47{
48 memblock_remove(0x40000000, SZ_2M);
49}
50
51static void __init msm8960_map_io(void)
52{
53 msm_map_msm8960_io();
54}
55
56static void __init msm8960_init_irq(void)
57{
58 unsigned int i;
59 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
60 (void *)MSM_QGIC_CPU_BASE);
61
62 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
63 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
64
65 if (machine_is_msm8960_rumi3())
66 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
67
68 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
69 * as they are configured as level, which does not play nice with
70 * handle_percpu_irq.
71 */
72 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
73 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
74 irq_set_handler(i, handle_percpu_irq);
75 }
76}
77
78static struct platform_device *sim_devices[] __initdata = {
79 &msm8960_device_uart_gsbi2,
80};
81
82static struct platform_device *rumi3_devices[] __initdata = {
83 &msm8960_device_uart_gsbi5,
84};
85
86static void __init msm8960_sim_init(void)
87{
88 platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
89}
90
91static void __init msm8960_rumi3_init(void)
92{
93 platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
94}
95
96static void __init msm8960_init_late(void)
97{
98 smd_debugfs_init();
99}
100
101MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
102 .fixup = msm8960_fixup,
103 .reserve = msm8960_reserve,
104 .map_io = msm8960_map_io,
105 .init_irq = msm8960_init_irq,
106 .timer = &msm_timer,
107 .handle_irq = gic_handle_irq,
108 .init_machine = msm8960_sim_init,
109 .init_late = msm8960_init_late,
110MACHINE_END
111
112MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
113 .fixup = msm8960_fixup,
114 .reserve = msm8960_reserve,
115 .map_io = msm8960_map_io,
116 .init_irq = msm8960_init_irq,
117 .timer = &msm_timer,
118 .handle_irq = gic_handle_irq,
119 .init_machine = msm8960_rumi3_init,
120 .init_late = msm8960_init_late,
121MACHINE_END
122
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
deleted file mode 100644
index e37a724cd1eb..000000000000
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/memblock.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/hardware/gic.h>
27#include <asm/setup.h>
28
29#include <mach/board.h>
30#include <mach/msm_iomap.h>
31
32static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
33 struct meminfo *mi)
34{
35 for (; tag->hdr.size; tag = tag_next(tag))
36 if (tag->hdr.tag == ATAG_MEM &&
37 tag->u.mem.start == 0x40200000) {
38 tag->u.mem.start = 0x40000000;
39 tag->u.mem.size += SZ_2M;
40 }
41}
42
43static void __init msm8x60_reserve(void)
44{
45 memblock_remove(0x40000000, SZ_2M);
46}
47
48static void __init msm8x60_map_io(void)
49{
50 msm_map_msm8x60_io();
51}
52
53#ifdef CONFIG_OF
54static struct of_device_id msm_dt_gic_match[] __initdata = {
55 { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
56 {}
57};
58#endif
59
60static void __init msm8x60_init_irq(void)
61{
62 if (!of_have_populated_dt())
63 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
64 (void *)MSM_QGIC_CPU_BASE);
65#ifdef CONFIG_OF
66 else
67 of_irq_init(msm_dt_gic_match);
68#endif
69
70 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
71 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
72
73 /* RUMI does not adhere to GIC spec by enabling STIs by default.
74 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
75 */
76 if (!machine_is_msm8x60_sim())
77 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
78}
79
80static void __init msm8x60_init(void)
81{
82}
83
84static void __init msm8x60_init_late(void)
85{
86 smd_debugfs_init();
87}
88
89#ifdef CONFIG_OF
90static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
91 {}
92};
93
94static void __init msm8x60_dt_init(void)
95{
96 if (of_machine_is_compatible("qcom,msm8660-surf")) {
97 printk(KERN_INFO "Init surf UART registers\n");
98 msm8x60_init_uart12dm();
99 }
100
101 of_platform_populate(NULL, of_default_bus_match_table,
102 msm_auxdata_lookup, NULL);
103}
104
105static const char *msm8x60_fluid_match[] __initdata = {
106 "qcom,msm8660-fluid",
107 "qcom,msm8660-surf",
108 NULL
109};
110#endif /* CONFIG_OF */
111
112MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
113 .fixup = msm8x60_fixup,
114 .reserve = msm8x60_reserve,
115 .map_io = msm8x60_map_io,
116 .init_irq = msm8x60_init_irq,
117 .handle_irq = gic_handle_irq,
118 .init_machine = msm8x60_init,
119 .init_late = msm8x60_init_late,
120 .timer = &msm_timer,
121MACHINE_END
122
123MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
124 .fixup = msm8x60_fixup,
125 .reserve = msm8x60_reserve,
126 .map_io = msm8x60_map_io,
127 .init_irq = msm8x60_init_irq,
128 .handle_irq = gic_handle_irq,
129 .init_machine = msm8x60_init,
130 .init_late = msm8x60_init_late,
131 .timer = &msm_timer,
132MACHINE_END
133
134MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
135 .fixup = msm8x60_fixup,
136 .reserve = msm8x60_reserve,
137 .map_io = msm8x60_map_io,
138 .init_irq = msm8x60_init_irq,
139 .handle_irq = gic_handle_irq,
140 .init_machine = msm8x60_init,
141 .init_late = msm8x60_init_late,
142 .timer = &msm_timer,
143MACHINE_END
144
145MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
146 .fixup = msm8x60_fixup,
147 .reserve = msm8x60_reserve,
148 .map_io = msm8x60_map_io,
149 .init_irq = msm8x60_init_irq,
150 .handle_irq = gic_handle_irq,
151 .init_machine = msm8x60_init,
152 .init_late = msm8x60_init_late,
153 .timer = &msm_timer,
154MACHINE_END
155
156#ifdef CONFIG_OF
157/* TODO: General device tree support for all MSM. */
158DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
159 .map_io = msm8x60_map_io,
160 .init_irq = msm8x60_init_irq,
161 .init_machine = msm8x60_dt_init,
162 .init_late = msm8x60_init_late,
163 .timer = &msm_timer,
164 .dt_compat = msm8x60_fluid_match,
165MACHINE_END
166#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index c8fe0edb9761..b16b71abf5f6 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -35,8 +35,7 @@
35#include <mach/mmc.h> 35#include <mach/mmc.h>
36 36
37#include "devices.h" 37#include "devices.h"
38 38#include "common.h"
39extern struct sys_timer msm_timer;
40 39
41static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; 40static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
42static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; 41static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
@@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
201 .init_irq = qsd8x50_init_irq, 200 .init_irq = qsd8x50_init_irq,
202 .init_machine = qsd8x50_init, 201 .init_machine = qsd8x50_init,
203 .init_late = qsd8x50_init_late, 202 .init_late = qsd8x50_init_late,
204 .timer = &msm_timer, 203 .timer = &qsd8x50_timer,
205MACHINE_END 204MACHINE_END
206 205
207MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") 206MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
@@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
210 .init_irq = qsd8x50_init_irq, 209 .init_irq = qsd8x50_init_irq,
211 .init_machine = qsd8x50_init, 210 .init_machine = qsd8x50_init,
212 .init_late = qsd8x50_init_late, 211 .init_late = qsd8x50_init_late,
213 .timer = &msm_timer, 212 .timer = &qsd8x50_timer,
214MACHINE_END 213MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab10eef..b7b0fc7e3278 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
27#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30#include <mach/system.h>
31#include <mach/vreg.h> 30#include <mach/vreg.h>
32#include <mach/board.h> 31#include <mach/board.h>
33 32
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index bbe13f12fa01..4ba0800e243e 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -31,6 +31,7 @@
31 31
32#include "devices.h" 32#include "devices.h"
33#include "board-trout.h" 33#include "board-trout.h"
34#include "common.h"
34 35
35extern int trout_init_mmc(unsigned int); 36extern int trout_init_mmc(unsigned int);
36 37
@@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = {
42 &msm_device_i2c, 43 &msm_device_i2c,
43}; 44};
44 45
45extern struct sys_timer msm_timer;
46
47static void __init trout_init_early(void) 46static void __init trout_init_early(void)
48{ 47{
49 arch_ioremap_caller = __msm_ioremap_caller; 48 arch_ioremap_caller = __msm_ioremap_caller;
@@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream")
111 .init_irq = trout_init_irq, 110 .init_irq = trout_init_irq,
112 .init_machine = trout_init, 111 .init_machine = trout_init,
113 .init_late = trout_init_late, 112 .init_late = trout_init_late,
114 .timer = &msm_timer, 113 .timer = &msm7x01_timer,
115MACHINE_END 114MACHINE_END
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b711311086..a52c970df157 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
25/* 25/*
26 * glue for the proc_comm interface 26 * glue for the proc_comm interface
27 */ 27 */
28int pc_clk_enable(unsigned id) 28static int pc_clk_enable(unsigned id)
29{ 29{
30 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); 30 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
31 if (rc < 0) 31 if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
34 return (int)id < 0 ? -EINVAL : 0; 34 return (int)id < 0 ? -EINVAL : 0;
35} 35}
36 36
37void pc_clk_disable(unsigned id) 37static void pc_clk_disable(unsigned id)
38{ 38{
39 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); 39 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
40} 40}
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
54 return (int)id < 0 ? -EINVAL : 0; 54 return (int)id < 0 ? -EINVAL : 0;
55} 55}
56 56
57int pc_clk_set_rate(unsigned id, unsigned rate) 57static int pc_clk_set_rate(unsigned id, unsigned rate)
58{ 58{
59 /* The rate _might_ be rounded off to the nearest KHz value by the 59 /* The rate _might_ be rounded off to the nearest KHz value by the
60 * remote function. So a return value of 0 doesn't necessarily mean 60 * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
67 return (int)id < 0 ? -EINVAL : 0; 67 return (int)id < 0 ? -EINVAL : 0;
68} 68}
69 69
70int pc_clk_set_min_rate(unsigned id, unsigned rate) 70static int pc_clk_set_min_rate(unsigned id, unsigned rate)
71{ 71{
72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); 72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
73 if (rc < 0) 73 if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
76 return (int)id < 0 ? -EINVAL : 0; 76 return (int)id < 0 ? -EINVAL : 0;
77} 77}
78 78
79int pc_clk_set_max_rate(unsigned id, unsigned rate) 79static int pc_clk_set_max_rate(unsigned id, unsigned rate)
80{ 80{
81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); 81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
82 if (rc < 0) 82 if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
85 return (int)id < 0 ? -EINVAL : 0; 85 return (int)id < 0 ? -EINVAL : 0;
86} 86}
87 87
88int pc_clk_set_flags(unsigned id, unsigned flags) 88static int pc_clk_set_flags(unsigned id, unsigned flags)
89{ 89{
90 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); 90 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
91 if (rc < 0) 91 if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
94 return (int)id < 0 ? -EINVAL : 0; 94 return (int)id < 0 ? -EINVAL : 0;
95} 95}
96 96
97unsigned pc_clk_get_rate(unsigned id) 97static unsigned pc_clk_get_rate(unsigned id)
98{ 98{
99 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) 99 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
100 return 0; 100 return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
102 return id; 102 return id;
103} 103}
104 104
105unsigned pc_clk_is_enabled(unsigned id) 105static unsigned pc_clk_is_enabled(unsigned id)
106{ 106{
107 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) 107 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
108 return 0; 108 return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
110 return id; 110 return id;
111} 111}
112 112
113long pc_clk_round_rate(unsigned id, unsigned rate) 113static long pc_clk_round_rate(unsigned id, unsigned rate)
114{ 114{
115 115
116 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ 116 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
new file mode 100644
index 000000000000..d68e5d7854f5
--- /dev/null
+++ b/arch/arm/mach-msm/common.h
@@ -0,0 +1,30 @@
1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_COMMON_H
13#define __MACH_COMMON_H
14
15extern struct sys_timer msm7x01_timer;
16extern struct sys_timer msm7x30_timer;
17extern struct sys_timer msm_dt_timer;
18extern struct sys_timer qsd8x50_timer;
19
20extern void msm_map_common_io(void);
21extern void msm_map_msm7x30_io(void);
22extern void msm_map_msm8x60_io(void);
23extern void msm_map_msm8960_io(void);
24extern void msm_map_qsd8x50_io(void);
25
26extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
27 unsigned int mtype, void *caller);
28
29
30#endif
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
deleted file mode 100644
index d9e1f26475de..000000000000
--- a/arch/arm/mach-msm/devices-msm8960.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20
21#include <linux/dma-mapping.h>
22#include <mach/irqs-8960.h>
23#include <mach/board.h>
24
25#include "devices.h"
26
27#define MSM_GSBI2_PHYS 0x16100000
28#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000)
29
30#define MSM_GSBI5_PHYS 0x16400000
31#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
32
33static struct resource resources_uart_gsbi2[] = {
34 {
35 .start = GSBI2_UARTDM_IRQ,
36 .end = GSBI2_UARTDM_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39 {
40 .start = MSM_UART2DM_PHYS,
41 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
42 .name = "uart_resource",
43 .flags = IORESOURCE_MEM,
44 },
45 {
46 .start = MSM_GSBI2_PHYS,
47 .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
48 .name = "gsbi_resource",
49 .flags = IORESOURCE_MEM,
50 },
51};
52
53struct platform_device msm8960_device_uart_gsbi2 = {
54 .name = "msm_serial",
55 .id = 0,
56 .num_resources = ARRAY_SIZE(resources_uart_gsbi2),
57 .resource = resources_uart_gsbi2,
58};
59
60static struct resource resources_uart_gsbi5[] = {
61 {
62 .start = GSBI5_UARTDM_IRQ,
63 .end = GSBI5_UARTDM_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = MSM_UART5DM_PHYS,
68 .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
69 .name = "uart_resource",
70 .flags = IORESOURCE_MEM,
71 },
72 {
73 .start = MSM_GSBI5_PHYS,
74 .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
75 .name = "gsbi_resource",
76 .flags = IORESOURCE_MEM,
77 },
78};
79
80struct platform_device msm8960_device_uart_gsbi5 = {
81 .name = "msm_serial",
82 .id = 0,
83 .num_resources = ARRAY_SIZE(resources_uart_gsbi5),
84 .resource = resources_uart_gsbi5,
85};
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 02cae5e2951c..354b91d4c3ac 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
223 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); 223 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
224 if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { 224 if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
225 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); 225 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
226 list_del(&cmd->list); 226 list_move_tail(&cmd->list, &active_commands[id]);
227 list_add_tail(&cmd->list, &active_commands[id]);
228 if (cmd->execute_func) 227 if (cmd->execute_func)
229 cmd->execute_func(cmd); 228 cmd->execute_func(cmd);
230 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); 229 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c65743..000000000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/* arch/arm/mach-msm/idle.c
2 *
3 * Idle processing for MSM7K - work around bugs with SWFI.
4 *
5 * Copyright (c) 2007 QUALCOMM Incorporated.
6 * Copyright (C) 2007 Google, Inc.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/init.h>
20#include <asm/system.h>
21
22static void msm_idle(void)
23{
24#ifdef CONFIG_MSM7X00A_IDLE
25 asm volatile (
26
27 "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
28 "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
29 "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
30 "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
31
32 "mov r0, #0 /* prepare wfi value */ \n\t"
33 "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
34 "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
35 "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
36
37 "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
38
39 : : : "r0","r1" );
40#endif
41}
42
43static int __init msm_idle_init(void)
44{
45 arm_pm_idle = msm_idle;
46 return 0;
47}
48
49arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 435f8edfafd1..0a0c393d8e31 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -22,27 +22,14 @@
22 22
23/* platform device data structures */ 23/* platform device data structures */
24 24
25struct msm_acpu_clock_platform_data
26{
27 uint32_t acpu_switch_time_us;
28 uint32_t max_speed_delta_khz;
29 uint32_t vdd_switch_time_us;
30 unsigned long power_collapse_khz;
31 unsigned long wait_for_irq_khz;
32};
33
34struct clk_lookup; 25struct clk_lookup;
35 26
36extern struct sys_timer msm_timer;
37
38/* common init routines for use by arch/arm/mach-msm/board-*.c */ 27/* common init routines for use by arch/arm/mach-msm/board-*.c */
39 28
40void __init msm_add_devices(void); 29void __init msm_add_devices(void);
41void __init msm_map_common_io(void);
42void __init msm_init_irq(void); 30void __init msm_init_irq(void);
43void __init msm_init_gpio(void); 31void __init msm_init_gpio(void);
44void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); 32void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
45void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
46int __init msm_add_sdcc(unsigned int controller, 33int __init msm_add_sdcc(unsigned int controller,
47 struct msm_mmc_platform_data *plat, 34 struct msm_mmc_platform_data *plat,
48 unsigned int stat_irq, unsigned long stat_irq_flags); 35 unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 6c4046c21296..67dc0e98b958 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -105,11 +105,4 @@
105#define MSM_AD5_PHYS 0xAC000000 105#define MSM_AD5_PHYS 0xAC000000
106#define MSM_AD5_SIZE (SZ_1M*13) 106#define MSM_AD5_SIZE (SZ_1M*13)
107 107
108#ifndef __ASSEMBLY__
109
110extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
111 unsigned int mtype, void *caller);
112
113#endif
114
115#endif 108#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index f944fe65a657..198202c267c8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -100,8 +100,4 @@
100#define MSM_HSUSB_PHYS 0xA3600000 100#define MSM_HSUSB_PHYS 0xA3600000
101#define MSM_HSUSB_SIZE SZ_1K 101#define MSM_HSUSB_SIZE SZ_1K
102 102
103#ifndef __ASSEMBLY__
104extern void msm_map_msm7x30_io(void);
105#endif
106
107#endif 103#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index a1752c0284fc..9819a556acae 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -46,12 +46,8 @@
46#define MSM8960_TMR0_SIZE SZ_4K 46#define MSM8960_TMR0_SIZE SZ_4K
47 47
48#ifdef CONFIG_DEBUG_MSM8960_UART 48#ifdef CONFIG_DEBUG_MSM8960_UART
49#define MSM_DEBUG_UART_BASE 0xE1040000 49#define MSM_DEBUG_UART_BASE 0xF0040000
50#define MSM_DEBUG_UART_PHYS 0x16440000 50#define MSM_DEBUG_UART_PHYS 0x16440000
51#endif 51#endif
52 52
53#ifndef __ASSEMBLY__
54extern void msm_map_msm8960_io(void);
55#endif
56
57#endif 53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index da77cc1d545d..0faa894729b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -122,8 +122,4 @@
122#define MSM_SDC4_PHYS 0xA0600000 122#define MSM_SDC4_PHYS 0xA0600000
123#define MSM_SDC4_SIZE SZ_4K 123#define MSM_SDC4_SIZE SZ_4K
124 124
125#ifndef __ASSEMBLY__
126extern void msm_map_qsd8x50_io(void);
127#endif
128
129#endif 125#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index b51ba8a927b8..199372e62def 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -52,12 +52,8 @@
52#define MSM8X60_TMR0_SIZE SZ_4K 52#define MSM8X60_TMR0_SIZE SZ_4K
53 53
54#ifdef CONFIG_DEBUG_MSM8660_UART 54#ifdef CONFIG_DEBUG_MSM8660_UART
55#define MSM_DEBUG_UART_BASE 0xE1040000 55#define MSM_DEBUG_UART_BASE 0xF0040000
56#define MSM_DEBUG_UART_PHYS 0x19C40000 56#define MSM_DEBUG_UART_PHYS 0x19C40000
57#endif 57#endif
58 58
59#ifndef __ASSEMBLY__
60extern void msm_map_msm8x60_io(void);
61#endif
62
63#endif 59#endif
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec87ffe..000000000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* arch/arm/mach-msm/include/mach/system.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16/* low level hardware reset hook -- for example, hitting the
17 * PSHOLD line on the PMIC to hard reset the system
18 */
19extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index b0016a00ddf2..123ef9cbce1b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -29,30 +29,32 @@
29 29
30#include <mach/board.h> 30#include <mach/board.h>
31 31
32#define MSM_CHIP_DEVICE(name, chip) { \ 32#include "common.h"
33
34#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
33 .virtual = (unsigned long) MSM_##name##_BASE, \ 35 .virtual = (unsigned long) MSM_##name##_BASE, \
34 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ 36 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
35 .length = chip##_##name##_SIZE, \ 37 .length = chip##_##name##_SIZE, \
36 .type = MT_DEVICE_NONSHARED, \ 38 .type = mem_type, \
37 } 39 }
38 40
41#define MSM_DEVICE_TYPE(name, mem_type) \
42 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
43#define MSM_CHIP_DEVICE(name, chip) \
44 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
39#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) 45#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
40 46
41#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ 47#if defined(CONFIG_ARCH_MSM7X00A)
42 || defined(CONFIG_ARCH_MSM7X25)
43static struct map_desc msm_io_desc[] __initdata = { 48static struct map_desc msm_io_desc[] __initdata = {
44 MSM_DEVICE(VIC), 49 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
45 MSM_CHIP_DEVICE(CSR, MSM7X00), 50 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
46 MSM_DEVICE(DMOV), 51 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
47 MSM_CHIP_DEVICE(GPIO1, MSM7X00), 52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
48 MSM_CHIP_DEVICE(GPIO2, MSM7X00), 53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
49 MSM_DEVICE(CLK_CTL), 54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
50#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 55#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
51 defined(CONFIG_DEBUG_MSM_UART3) 56 defined(CONFIG_DEBUG_MSM_UART3)
52 MSM_DEVICE(DEBUG_UART), 57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
53#endif
54#ifdef CONFIG_ARCH_MSM7X30
55 MSM_DEVICE(GCC),
56#endif 58#endif
57 { 59 {
58 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index e012dc8391cf..2d791e6b4ad1 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,17 +22,12 @@
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23#include <asm/smp_plat.h> 23#include <asm/smp_plat.h>
24 24
25#include <mach/msm_iomap.h>
26
27#include "scm-boot.h" 25#include "scm-boot.h"
28 26
29#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 27#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
30#define SCSS_CPU1CORE_RESET 0xD80 28#define SCSS_CPU1CORE_RESET 0xD80
31#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 29#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
32 30
33/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
34#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
35
36extern void msm_secondary_startup(void); 31extern void msm_secondary_startup(void);
37/* 32/*
38 * control for which core is the next to come out of the secondary 33 * control for which core is the next to come out of the secondary
@@ -50,9 +45,6 @@ static inline int get_core_count(void)
50 45
51void __cpuinit platform_secondary_init(unsigned int cpu) 46void __cpuinit platform_secondary_init(unsigned int cpu)
52{ 47{
53 /* Configure edge-triggered PPIs */
54 writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
55
56 /* 48 /*
57 * if any interrupts are already enabled for the primary 49 * if any interrupts are already enabled for the primary
58 * core (e.g. timer irq), then they will not have been enabled 50 * core (e.g. timer irq), then they will not have been enabled
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc736e7b..8f1eecd88186 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <mach/msm_iomap.h> 21#include <mach/msm_iomap.h>
22#include <mach/system.h>
23 22
24#include "proc_comm.h" 23#include "proc_comm.h"
25 24
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73297db..c5a2eddc6cdc 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
30#include <linux/delay.h> 30#include <linux/delay.h>
31 31
32#include <mach/msm_smd.h> 32#include <mach/msm_smd.h>
33#include <mach/system.h>
34 33
35#include "smd_private.h" 34#include "smd_private.h"
36#include "proc_comm.h" 35#include "proc_comm.h"
@@ -39,8 +38,6 @@
39#define CONFIG_QDSP6 1 38#define CONFIG_QDSP6 1
40#endif 39#endif
41 40
42void (*msm_hw_reset_hook)(void);
43
44#define MODULE_NAME "msm_smd" 41#define MODULE_NAME "msm_smd"
45 42
46enum { 43enum {
@@ -52,13 +49,14 @@ static int msm_smd_debug_mask;
52 49
53struct shared_info { 50struct shared_info {
54 int ready; 51 int ready;
55 unsigned state; 52 void __iomem *state;
56}; 53};
57 54
58static unsigned dummy_state[SMSM_STATE_COUNT]; 55static unsigned dummy_state[SMSM_STATE_COUNT];
59 56
60static struct shared_info smd_info = { 57static struct shared_info smd_info = {
61 .state = (unsigned) &dummy_state, 58 /* FIXME: not a real __iomem pointer */
59 .state = &dummy_state,
62}; 60};
63 61
64module_param_named(debug_mask, msm_smd_debug_mask, 62module_param_named(debug_mask, msm_smd_debug_mask,
@@ -101,10 +99,6 @@ static void handle_modem_crash(void)
101 pr_err("ARM9 has CRASHED\n"); 99 pr_err("ARM9 has CRASHED\n");
102 smd_diag(); 100 smd_diag();
103 101
104 /* hard reboot if possible */
105 if (msm_hw_reset_hook)
106 msm_hw_reset_hook();
107
108 /* in this case the modem or watchdog should reboot us */ 102 /* in this case the modem or watchdog should reboot us */
109 for (;;) 103 for (;;)
110 ; 104 ;
@@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
796 return smem_find(id, size); 790 return smem_find(id, size);
797} 791}
798 792
799void *smem_item(unsigned id, unsigned *size) 793void __iomem *smem_item(unsigned id, unsigned *size)
800{ 794{
801 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; 795 struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
802 struct smem_heap_entry *toc = shared->heap_toc; 796 struct smem_heap_entry *toc = shared->heap_toc;
803 797
804 if (id >= SMEM_NUM_ITEMS) 798 if (id >= SMEM_NUM_ITEMS)
805 return 0; 799 return NULL;
806 800
807 if (toc[id].allocated) { 801 if (toc[id].allocated) {
808 *size = toc[id].size; 802 *size = toc[id].size;
809 return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset); 803 return (MSM_SHARED_RAM_BASE + toc[id].offset);
810 } else { 804 } else {
811 *size = 0; 805 *size = 0;
812 } 806 }
813 807
814 return 0; 808 return NULL;
815} 809}
816 810
817void *smem_find(unsigned id, unsigned size_in) 811void *smem_find(unsigned id, unsigned size_in)
@@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
857int smsm_change_state(enum smsm_state_item item, 851int smsm_change_state(enum smsm_state_item item,
858 uint32_t clear_mask, uint32_t set_mask) 852 uint32_t clear_mask, uint32_t set_mask)
859{ 853{
860 unsigned long addr = smd_info.state + item * 4; 854 void __iomem *addr = smd_info.state + item * 4;
861 unsigned long flags; 855 unsigned long flags;
862 unsigned state; 856 unsigned state;
863 857
@@ -943,10 +937,10 @@ int smd_core_init(void)
943 /* wait for essential items to be initialized */ 937 /* wait for essential items to be initialized */
944 for (;;) { 938 for (;;) {
945 unsigned size; 939 unsigned size;
946 void *state; 940 void __iomem *state;
947 state = smem_item(SMEM_SMSM_SHARED_STATE, &size); 941 state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
948 if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) { 942 if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
949 smd_info.state = (unsigned)state; 943 smd_info.state = state;
950 break; 944 break;
951 } 945 }
952 } 946 }
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 812808254936..476549a8a709 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. 4 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -20,15 +20,16 @@
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
23 26
24#include <asm/mach/time.h> 27#include <asm/mach/time.h>
25#include <asm/hardware/gic.h> 28#include <asm/hardware/gic.h>
26#include <asm/localtimer.h> 29#include <asm/localtimer.h>
27#include <asm/sched_clock.h> 30#include <asm/sched_clock.h>
28 31
29#include <mach/msm_iomap.h> 32#include "common.h"
30#include <mach/cpu.h>
31#include <mach/board.h>
32 33
33#define TIMER_MATCH_VAL 0x0000 34#define TIMER_MATCH_VAL 0x0000
34#define TIMER_COUNT_VAL 0x0004 35#define TIMER_COUNT_VAL 0x0004
@@ -36,7 +37,6 @@
36#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) 37#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37#define TIMER_ENABLE_EN BIT(0) 38#define TIMER_ENABLE_EN BIT(0)
38#define TIMER_CLEAR 0x000C 39#define TIMER_CLEAR 0x000C
39#define DGT_CLK_CTL 0x0034
40#define DGT_CLK_CTL_DIV_4 0x3 40#define DGT_CLK_CTL_DIV_4 0x3
41 41
42#define GPT_HZ 32768 42#define GPT_HZ 32768
@@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
101 101
102static union { 102static union {
103 struct clock_event_device *evt; 103 struct clock_event_device *evt;
104 struct clock_event_device __percpu **percpu_evt; 104 struct clock_event_device * __percpu *percpu_evt;
105} msm_evt; 105} msm_evt;
106 106
107static void __iomem *source_base; 107static void __iomem *source_base;
@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
151 151
152 *__this_cpu_ptr(msm_evt.percpu_evt) = evt; 152 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
153 clockevents_register_device(evt); 153 clockevents_register_device(evt);
154 enable_percpu_irq(evt->irq, 0); 154 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
155 return 0; 155 return 0;
156} 156}
157 157
@@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void)
172 return msm_clocksource.read(&msm_clocksource); 172 return msm_clocksource.read(&msm_clocksource);
173} 173}
174 174
175static void __init msm_timer_init(void) 175static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
176 bool percpu)
176{ 177{
177 struct clock_event_device *ce = &msm_clockevent; 178 struct clock_event_device *ce = &msm_clockevent;
178 struct clocksource *cs = &msm_clocksource; 179 struct clocksource *cs = &msm_clocksource;
179 int res; 180 int res;
180 u32 dgt_hz;
181
182 if (cpu_is_msm7x01()) {
183 event_base = MSM_CSR_BASE;
184 source_base = MSM_CSR_BASE + 0x10;
185 dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
186 cs->read = msm_read_timer_count_shift;
187 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
188 } else if (cpu_is_msm7x30()) {
189 event_base = MSM_CSR_BASE + 0x04;
190 source_base = MSM_CSR_BASE + 0x24;
191 dgt_hz = 24576000 / 4;
192 } else if (cpu_is_qsd8x50()) {
193 event_base = MSM_CSR_BASE;
194 source_base = MSM_CSR_BASE + 0x10;
195 dgt_hz = 19200000 / 4;
196 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
197 event_base = MSM_TMR_BASE + 0x04;
198 /* Use CPU0's timer as the global clock source. */
199 source_base = MSM_TMR0_BASE + 0x24;
200 dgt_hz = 27000000 / 4;
201 writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
202 } else
203 BUG();
204 181
205 writel_relaxed(0, event_base + TIMER_ENABLE); 182 writel_relaxed(0, event_base + TIMER_ENABLE);
206 writel_relaxed(0, event_base + TIMER_CLEAR); 183 writel_relaxed(0, event_base + TIMER_CLEAR);
207 writel_relaxed(~0, event_base + TIMER_MATCH_VAL); 184 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
208 ce->cpumask = cpumask_of(0); 185 ce->cpumask = cpumask_of(0);
186 ce->irq = irq;
209 187
210 ce->irq = INT_GP_TIMER_EXP;
211 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); 188 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
212 if (cpu_is_msm8x60() || cpu_is_msm8960()) { 189 if (percpu) {
213 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); 190 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
214 if (!msm_evt.percpu_evt) { 191 if (!msm_evt.percpu_evt) {
215 pr_err("memory allocation failed for %s\n", ce->name); 192 pr_err("memory allocation failed for %s\n", ce->name);
@@ -219,7 +196,7 @@ static void __init msm_timer_init(void)
219 res = request_percpu_irq(ce->irq, msm_timer_interrupt, 196 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
220 ce->name, msm_evt.percpu_evt); 197 ce->name, msm_evt.percpu_evt);
221 if (!res) { 198 if (!res) {
222 enable_percpu_irq(ce->irq, 0); 199 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
223#ifdef CONFIG_LOCAL_TIMERS 200#ifdef CONFIG_LOCAL_TIMERS
224 local_timer_register(&msm_local_timer_ops); 201 local_timer_register(&msm_local_timer_ops);
225#endif 202#endif
@@ -238,10 +215,143 @@ err:
238 res = clocksource_register_hz(cs, dgt_hz); 215 res = clocksource_register_hz(cs, dgt_hz);
239 if (res) 216 if (res)
240 pr_err("clocksource_register failed\n"); 217 pr_err("clocksource_register failed\n");
241 setup_sched_clock(msm_sched_clock_read, 218 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
242 cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
243} 219}
244 220
245struct sys_timer msm_timer = { 221#ifdef CONFIG_OF
246 .init = msm_timer_init 222static const struct of_device_id msm_dgt_match[] __initconst = {
223 { .compatible = "qcom,msm-dgt" },
224 { },
225};
226
227static const struct of_device_id msm_gpt_match[] __initconst = {
228 { .compatible = "qcom,msm-gpt" },
229 { },
230};
231
232static void __init msm_dt_timer_init(void)
233{
234 struct device_node *np;
235 u32 freq;
236 int irq;
237 struct resource res;
238 u32 percpu_offset;
239 void __iomem *dgt_clk_ctl;
240
241 np = of_find_matching_node(NULL, msm_gpt_match);
242 if (!np) {
243 pr_err("Can't find GPT DT node\n");
244 return;
245 }
246
247 event_base = of_iomap(np, 0);
248 if (!event_base) {
249 pr_err("Failed to map event base\n");
250 return;
251 }
252
253 irq = irq_of_parse_and_map(np, 0);
254 if (irq <= 0) {
255 pr_err("Can't get irq\n");
256 return;
257 }
258 of_node_put(np);
259
260 np = of_find_matching_node(NULL, msm_dgt_match);
261 if (!np) {
262 pr_err("Can't find DGT DT node\n");
263 return;
264 }
265
266 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
267 percpu_offset = 0;
268
269 if (of_address_to_resource(np, 0, &res)) {
270 pr_err("Failed to parse DGT resource\n");
271 return;
272 }
273
274 source_base = ioremap(res.start + percpu_offset, resource_size(&res));
275 if (!source_base) {
276 pr_err("Failed to map source base\n");
277 return;
278 }
279
280 if (!of_address_to_resource(np, 1, &res)) {
281 dgt_clk_ctl = ioremap(res.start + percpu_offset,
282 resource_size(&res));
283 if (!dgt_clk_ctl) {
284 pr_err("Failed to map DGT control base\n");
285 return;
286 }
287 writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
288 iounmap(dgt_clk_ctl);
289 }
290
291 if (of_property_read_u32(np, "clock-frequency", &freq)) {
292 pr_err("Unknown frequency\n");
293 return;
294 }
295 of_node_put(np);
296
297 msm_timer_init(freq, 32, irq, !!percpu_offset);
298}
299
300struct sys_timer msm_dt_timer = {
301 .init = msm_dt_timer_init
302};
303#endif
304
305static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
306{
307 event_base = ioremap(event, SZ_64);
308 if (!event_base) {
309 pr_err("Failed to map event base\n");
310 return 1;
311 }
312 source_base = ioremap(source, SZ_64);
313 if (!source_base) {
314 pr_err("Failed to map source base\n");
315 return 1;
316 }
317 return 0;
318}
319
320static void __init msm7x01_timer_init(void)
321{
322 struct clocksource *cs = &msm_clocksource;
323
324 if (msm_timer_map(0xc0100000, 0xc0100010))
325 return;
326 cs->read = msm_read_timer_count_shift;
327 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
328 /* 600 KHz */
329 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
330 false);
331}
332
333struct sys_timer msm7x01_timer = {
334 .init = msm7x01_timer_init
335};
336
337static void __init msm7x30_timer_init(void)
338{
339 if (msm_timer_map(0xc0100004, 0xc0100024))
340 return;
341 msm_timer_init(24576000 / 4, 32, 1, false);
342}
343
344struct sys_timer msm7x30_timer = {
345 .init = msm7x30_timer_init
346};
347
348static void __init qsd8x50_timer_init(void)
349{
350 if (msm_timer_map(0xAC100000, 0xAC100010))
351 return;
352 msm_timer_init(19200000 / 4, 32, 7, false);
353}
354
355struct sys_timer qsd8x50_timer = {
356 .init = qsd8x50_timer_init
247}; 357};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 10:32:41 -0400