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Diffstat (limited to 'arch/arm/mach-msm/sirc.c')
-rw-r--r--arch/arm/mach-msm/sirc.c39
1 files changed, 19 insertions, 20 deletions
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 152eefda3ce6..11b54c7aeb09 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -42,12 +42,11 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
42 42
43/* Mask off the given interrupt. Keep the int_enable mask in sync with 43/* Mask off the given interrupt. Keep the int_enable mask in sync with
44 the enable reg, so it can be restored after power collapse. */ 44 the enable reg, so it can be restored after power collapse. */
45static void sirc_irq_mask(unsigned int irq) 45static void sirc_irq_mask(struct irq_data *d)
46{ 46{
47 unsigned int mask; 47 unsigned int mask;
48 48
49 49 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
50 mask = 1 << (irq - FIRST_SIRC_IRQ);
51 writel(mask, sirc_regs.int_enable_clear); 50 writel(mask, sirc_regs.int_enable_clear);
52 int_enable &= ~mask; 51 int_enable &= ~mask;
53 return; 52 return;
@@ -55,31 +54,31 @@ static void sirc_irq_mask(unsigned int irq)
55 54
56/* Unmask the given interrupt. Keep the int_enable mask in sync with 55/* Unmask the given interrupt. Keep the int_enable mask in sync with
57 the enable reg, so it can be restored after power collapse. */ 56 the enable reg, so it can be restored after power collapse. */
58static void sirc_irq_unmask(unsigned int irq) 57static void sirc_irq_unmask(struct irq_data *d)
59{ 58{
60 unsigned int mask; 59 unsigned int mask;
61 60
62 mask = 1 << (irq - FIRST_SIRC_IRQ); 61 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
63 writel(mask, sirc_regs.int_enable_set); 62 writel(mask, sirc_regs.int_enable_set);
64 int_enable |= mask; 63 int_enable |= mask;
65 return; 64 return;
66} 65}
67 66
68static void sirc_irq_ack(unsigned int irq) 67static void sirc_irq_ack(struct irq_data *d)
69{ 68{
70 unsigned int mask; 69 unsigned int mask;
71 70
72 mask = 1 << (irq - FIRST_SIRC_IRQ); 71 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
73 writel(mask, sirc_regs.int_clear); 72 writel(mask, sirc_regs.int_clear);
74 return; 73 return;
75} 74}
76 75
77static int sirc_irq_set_wake(unsigned int irq, unsigned int on) 76static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
78{ 77{
79 unsigned int mask; 78 unsigned int mask;
80 79
81 /* Used to set the interrupt enable mask during power collapse. */ 80 /* Used to set the interrupt enable mask during power collapse. */
82 mask = 1 << (irq - FIRST_SIRC_IRQ); 81 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
83 if (on) 82 if (on)
84 wake_enable |= mask; 83 wake_enable |= mask;
85 else 84 else
@@ -88,12 +87,12 @@ static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
88 return 0; 87 return 0;
89} 88}
90 89
91static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type) 90static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
92{ 91{
93 unsigned int mask; 92 unsigned int mask;
94 unsigned int val; 93 unsigned int val;
95 94
96 mask = 1 << (irq - FIRST_SIRC_IRQ); 95 mask = 1 << (d->irq - FIRST_SIRC_IRQ);
97 val = readl(sirc_regs.int_polarity); 96 val = readl(sirc_regs.int_polarity);
98 97
99 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING)) 98 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
@@ -106,10 +105,10 @@ static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
106 val = readl(sirc_regs.int_type); 105 val = readl(sirc_regs.int_type);
107 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
108 val |= mask; 107 val |= mask;
109 irq_desc[irq].handle_irq = handle_edge_irq; 108 irq_desc[d->irq].handle_irq = handle_edge_irq;
110 } else { 109 } else {
111 val &= ~mask; 110 val &= ~mask;
112 irq_desc[irq].handle_irq = handle_level_irq; 111 irq_desc[d->irq].handle_irq = handle_level_irq;
113 } 112 }
114 113
115 writel(val, sirc_regs.int_type); 114 writel(val, sirc_regs.int_type);
@@ -139,16 +138,16 @@ static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
139 ; 138 ;
140 generic_handle_irq(sirq+FIRST_SIRC_IRQ); 139 generic_handle_irq(sirq+FIRST_SIRC_IRQ);
141 140
142 desc->chip->ack(irq); 141 desc->irq_data.chip->irq_ack(&desc->irq_data);
143} 142}
144 143
145static struct irq_chip sirc_irq_chip = { 144static struct irq_chip sirc_irq_chip = {
146 .name = "sirc", 145 .name = "sirc",
147 .ack = sirc_irq_ack, 146 .irq_ack = sirc_irq_ack,
148 .mask = sirc_irq_mask, 147 .irq_mask = sirc_irq_mask,
149 .unmask = sirc_irq_unmask, 148 .irq_unmask = sirc_irq_unmask,
150 .set_wake = sirc_irq_set_wake, 149 .irq_set_wake = sirc_irq_set_wake,
151 .set_type = sirc_irq_set_type, 150 .irq_set_type = sirc_irq_set_type,
152}; 151};
153 152
154void __init msm_init_sirc(void) 153void __init msm_init_sirc(void)