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Diffstat (limited to 'arch/arm/mach-msm/irq.c')
-rw-r--r--arch/arm/mach-msm/irq.c45
1 files changed, 22 insertions, 23 deletions
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 6c8d5f8caef3..0b27d899f40e 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -64,35 +64,34 @@
64#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) 64#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
65#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) 65#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
66 66
67static void msm_irq_ack(unsigned int irq) 67static void msm_irq_ack(struct irq_data *d)
68{ 68{
69 void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0); 69 void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
70 irq = 1 << (irq & 31); 70 writel(1 << (d->irq & 31), reg);
71 writel(irq, reg);
72} 71}
73 72
74static void msm_irq_mask(unsigned int irq) 73static void msm_irq_mask(struct irq_data *d)
75{ 74{
76 void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0); 75 void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
77 writel(1 << (irq & 31), reg); 76 writel(1 << (d->irq & 31), reg);
78} 77}
79 78
80static void msm_irq_unmask(unsigned int irq) 79static void msm_irq_unmask(struct irq_data *d)
81{ 80{
82 void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0); 81 void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
83 writel(1 << (irq & 31), reg); 82 writel(1 << (d->irq & 31), reg);
84} 83}
85 84
86static int msm_irq_set_wake(unsigned int irq, unsigned int on) 85static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
87{ 86{
88 return -EINVAL; 87 return -EINVAL;
89} 88}
90 89
91static int msm_irq_set_type(unsigned int irq, unsigned int flow_type) 90static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
92{ 91{
93 void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0); 92 void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
94 void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0); 93 void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
95 int b = 1 << (irq & 31); 94 int b = 1 << (d->irq & 31);
96 95
97 if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) 96 if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
98 writel(readl(preg) | b, preg); 97 writel(readl(preg) | b, preg);
@@ -101,22 +100,22 @@ static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
101 100
102 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
103 writel(readl(treg) | b, treg); 102 writel(readl(treg) | b, treg);
104 irq_desc[irq].handle_irq = handle_edge_irq; 103 irq_desc[d->irq].handle_irq = handle_edge_irq;
105 } 104 }
106 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
107 writel(readl(treg) & (~b), treg); 106 writel(readl(treg) & (~b), treg);
108 irq_desc[irq].handle_irq = handle_level_irq; 107 irq_desc[d->irq].handle_irq = handle_level_irq;
109 } 108 }
110 return 0; 109 return 0;
111} 110}
112 111
113static struct irq_chip msm_irq_chip = { 112static struct irq_chip msm_irq_chip = {
114 .name = "msm", 113 .name = "msm",
115 .ack = msm_irq_ack, 114 .irq_ack = msm_irq_ack,
116 .mask = msm_irq_mask, 115 .irq_mask = msm_irq_mask,
117 .unmask = msm_irq_unmask, 116 .irq_unmask = msm_irq_unmask,
118 .set_wake = msm_irq_set_wake, 117 .irq_set_wake = msm_irq_set_wake,
119 .set_type = msm_irq_set_type, 118 .irq_set_type = msm_irq_set_type,
120}; 119};
121 120
122void __init msm_init_irq(void) 121void __init msm_init_irq(void)