diff options
Diffstat (limited to 'arch/arm/mach-msm/include/mach')
-rw-r--r-- | arch/arm/mach-msm/include/mach/debug-macro.S | 51 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8960.h | 5 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 5 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap.h | 12 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/system.h | 8 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/uncompress.h | 39 |
9 files changed, 85 insertions, 71 deletions
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index 2dc73ccddb11..3ffd8668c9a5 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S | |||
@@ -1,6 +1,7 @@ | |||
1 | /* arch/arm/mach-msm7200/include/mach/debug-macro.S | 1 | /* |
2 | * | 2 | * |
3 | * Copyright (C) 2007 Google, Inc. | 3 | * Copyright (C) 2007 Google, Inc. |
4 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
4 | * Author: Brian Swetland <swetland@google.com> | 5 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 6 | * |
6 | * This software is licensed under the terms of the GNU General Public | 7 | * This software is licensed under the terms of the GNU General Public |
@@ -14,40 +15,52 @@ | |||
14 | * | 15 | * |
15 | */ | 16 | */ |
16 | 17 | ||
17 | |||
18 | |||
19 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
20 | #include <mach/msm_iomap.h> | 19 | #include <mach/msm_iomap.h> |
21 | 20 | ||
22 | #if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE) | ||
23 | .macro addruart, rp, rv, tmp | 21 | .macro addruart, rp, rv, tmp |
22 | #ifdef MSM_DEBUG_UART_PHYS | ||
24 | ldr \rp, =MSM_DEBUG_UART_PHYS | 23 | ldr \rp, =MSM_DEBUG_UART_PHYS |
25 | ldr \rv, =MSM_DEBUG_UART_BASE | 24 | ldr \rv, =MSM_DEBUG_UART_BASE |
25 | #endif | ||
26 | .endm | 26 | .endm |
27 | 27 | ||
28 | .macro senduart,rd,rx | 28 | .macro senduart, rd, rx |
29 | #ifdef CONFIG_MSM_HAS_DEBUG_UART_HS | ||
30 | @ Write the 1 character to UARTDM_TF | ||
31 | str \rd, [\rx, #0x70] | ||
32 | #else | ||
29 | teq \rx, #0 | 33 | teq \rx, #0 |
30 | strne \rd, [\rx, #0x0C] | 34 | strne \rd, [\rx, #0x0C] |
35 | #endif | ||
31 | .endm | 36 | .endm |
32 | 37 | ||
33 | .macro waituart,rd,rx | 38 | .macro waituart, rd, rx |
39 | #ifdef CONFIG_MSM_HAS_DEBUG_UART_HS | ||
40 | @ check for TX_EMT in UARTDM_SR | ||
41 | ldr \rd, [\rx, #0x08] | ||
42 | tst \rd, #0x08 | ||
43 | bne 1002f | ||
44 | @ wait for TXREADY in UARTDM_ISR | ||
45 | 1001: ldr \rd, [\rx, #0x14] | ||
46 | tst \rd, #0x80 | ||
47 | beq 1001b | ||
48 | 1002: | ||
49 | @ Clear TX_READY by writing to the UARTDM_CR register | ||
50 | mov \rd, #0x300 | ||
51 | str \rd, [\rx, #0x10] | ||
52 | @ Write 0x1 to NCF register | ||
53 | mov \rd, #0x1 | ||
54 | str \rd, [\rx, #0x40] | ||
55 | @ UARTDM reg. Read to induce delay | ||
56 | ldr \rd, [\rx, #0x08] | ||
57 | #else | ||
34 | @ wait for TX_READY | 58 | @ wait for TX_READY |
35 | 1001: ldr \rd, [\rx, #0x08] | 59 | 1001: ldr \rd, [\rx, #0x08] |
36 | tst \rd, #0x04 | 60 | tst \rd, #0x04 |
37 | beq 1001b | 61 | beq 1001b |
38 | .endm | ||
39 | #else | ||
40 | .macro addruart, rp, rv, tmp | ||
41 | mov \rv, #0xff000000 | ||
42 | orr \rv, \rv, #0x00f00000 | ||
43 | .endm | ||
44 | |||
45 | .macro senduart,rd,rx | ||
46 | .endm | ||
47 | |||
48 | .macro waituart,rd,rx | ||
49 | .endm | ||
50 | #endif | 62 | #endif |
63 | .endm | ||
51 | 64 | ||
52 | .macro busyuart,rd,rx | 65 | .macro busyuart, rd, rx |
53 | .endm | 66 | .endm |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 94fe9fe6feb3..8af46123dab6 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | |||
@@ -78,18 +78,6 @@ | |||
78 | #define MSM_UART3_PHYS 0xA9C00000 | 78 | #define MSM_UART3_PHYS 0xA9C00000 |
79 | #define MSM_UART3_SIZE SZ_4K | 79 | #define MSM_UART3_SIZE SZ_4K |
80 | 80 | ||
81 | #ifdef CONFIG_MSM_DEBUG_UART | ||
82 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
83 | #if CONFIG_MSM_DEBUG_UART == 1 | ||
84 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
85 | #elif CONFIG_MSM_DEBUG_UART == 2 | ||
86 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
87 | #elif CONFIG_MSM_DEBUG_UART == 3 | ||
88 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
89 | #endif | ||
90 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
91 | #endif | ||
92 | |||
93 | #define MSM_SDC1_PHYS 0xA0400000 | 81 | #define MSM_SDC1_PHYS 0xA0400000 |
94 | #define MSM_SDC1_SIZE SZ_4K | 82 | #define MSM_SDC1_SIZE SZ_4K |
95 | 83 | ||
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 37694442d1bd..198202c267c8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | |||
@@ -89,18 +89,6 @@ | |||
89 | #define MSM_UART3_PHYS 0xACC00000 | 89 | #define MSM_UART3_PHYS 0xACC00000 |
90 | #define MSM_UART3_SIZE SZ_4K | 90 | #define MSM_UART3_SIZE SZ_4K |
91 | 91 | ||
92 | #ifdef CONFIG_MSM_DEBUG_UART | ||
93 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
94 | #if CONFIG_MSM_DEBUG_UART == 1 | ||
95 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
96 | #elif CONFIG_MSM_DEBUG_UART == 2 | ||
97 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
98 | #elif CONFIG_MSM_DEBUG_UART == 3 | ||
99 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
100 | #endif | ||
101 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
102 | #endif | ||
103 | |||
104 | #define MSM_MDC_BASE IOMEM(0xE0200000) | 92 | #define MSM_MDC_BASE IOMEM(0xE0200000) |
105 | #define MSM_MDC_PHYS 0xAA500000 | 93 | #define MSM_MDC_PHYS 0xAA500000 |
106 | #define MSM_MDC_SIZE SZ_1M | 94 | #define MSM_MDC_SIZE SZ_1M |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index 3c9d9602a318..800b55767e6b 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h | |||
@@ -45,4 +45,9 @@ | |||
45 | #define MSM8960_TMR0_PHYS 0x0208A000 | 45 | #define MSM8960_TMR0_PHYS 0x0208A000 |
46 | #define MSM8960_TMR0_SIZE SZ_4K | 46 | #define MSM8960_TMR0_SIZE SZ_4K |
47 | 47 | ||
48 | #ifdef CONFIG_DEBUG_MSM8960_UART | ||
49 | #define MSM_DEBUG_UART_BASE 0xE1040000 | ||
50 | #define MSM_DEBUG_UART_PHYS 0x16440000 | ||
51 | #endif | ||
52 | |||
48 | #endif | 53 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index d67cd73316f4..0faa894729b7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | |||
@@ -83,18 +83,6 @@ | |||
83 | #define MSM_UART3_PHYS 0xA9C00000 | 83 | #define MSM_UART3_PHYS 0xA9C00000 |
84 | #define MSM_UART3_SIZE SZ_4K | 84 | #define MSM_UART3_SIZE SZ_4K |
85 | 85 | ||
86 | #ifdef CONFIG_MSM_DEBUG_UART | ||
87 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
88 | #if CONFIG_MSM_DEBUG_UART == 1 | ||
89 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
90 | #elif CONFIG_MSM_DEBUG_UART == 2 | ||
91 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
92 | #elif CONFIG_MSM_DEBUG_UART == 3 | ||
93 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
94 | #endif | ||
95 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
96 | #endif | ||
97 | |||
98 | #define MSM_MDC_BASE IOMEM(0xE0200000) | 86 | #define MSM_MDC_BASE IOMEM(0xE0200000) |
99 | #define MSM_MDC_PHYS 0xAA500000 | 87 | #define MSM_MDC_PHYS 0xAA500000 |
100 | #define MSM_MDC_SIZE SZ_1M | 88 | #define MSM_MDC_SIZE SZ_1M |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 3b19b8f244b8..54e12caa8d86 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |||
@@ -62,4 +62,9 @@ | |||
62 | #define MSM8X60_TMR0_PHYS 0x02040000 | 62 | #define MSM8X60_TMR0_PHYS 0x02040000 |
63 | #define MSM8X60_TMR0_SIZE SZ_4K | 63 | #define MSM8X60_TMR0_SIZE SZ_4K |
64 | 64 | ||
65 | #ifdef CONFIG_DEBUG_MSM8660_UART | ||
66 | #define MSM_DEBUG_UART_BASE 0xE1040000 | ||
67 | #define MSM_DEBUG_UART_PHYS 0x19C40000 | ||
68 | #endif | ||
69 | |||
65 | #endif | 70 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 4ded15238b60..90682f4599d3 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h | |||
@@ -55,6 +55,18 @@ | |||
55 | 55 | ||
56 | #include "msm_iomap-8960.h" | 56 | #include "msm_iomap-8960.h" |
57 | 57 | ||
58 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
59 | #if defined(CONFIG_DEBUG_MSM_UART1) | ||
60 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
61 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
62 | #elif defined(CONFIG_DEBUG_MSM_UART2) | ||
63 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
64 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
65 | #elif defined(CONFIG_DEBUG_MSM_UART3) | ||
66 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
67 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
68 | #endif | ||
69 | |||
58 | /* Virtual addresses shared across all MSM targets. */ | 70 | /* Virtual addresses shared across all MSM targets. */ |
59 | #define MSM_CSR_BASE IOMEM(0xE0001000) | 71 | #define MSM_CSR_BASE IOMEM(0xE0001000) |
60 | #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) | 72 | #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) |
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h index d2e83f42ba16..311db2b35da0 100644 --- a/arch/arm/mach-msm/include/mach/system.h +++ b/arch/arm/mach-msm/include/mach/system.h | |||
@@ -12,16 +12,8 @@ | |||
12 | * GNU General Public License for more details. | 12 | * GNU General Public License for more details. |
13 | * | 13 | * |
14 | */ | 14 | */ |
15 | |||
16 | #include <mach/hardware.h> | ||
17 | |||
18 | void arch_idle(void); | 15 | void arch_idle(void); |
19 | 16 | ||
20 | static inline void arch_reset(char mode, const char *cmd) | ||
21 | { | ||
22 | for (;;) ; /* depends on IPC w/ other core */ | ||
23 | } | ||
24 | |||
25 | /* low level hardware reset hook -- for example, hitting the | 17 | /* low level hardware reset hook -- for example, hitting the |
26 | * PSHOLD line on the PMIC to hard reset the system | 18 | * PSHOLD line on the PMIC to hard reset the system |
27 | */ | 19 | */ |
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h index d94292c29d8e..169a84007456 100644 --- a/arch/arm/mach-msm/include/mach/uncompress.h +++ b/arch/arm/mach-msm/include/mach/uncompress.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* arch/arm/mach-msm/include/mach/uncompress.h | 1 | /* |
2 | * | ||
3 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
4 | * | 4 | * |
5 | * This software is licensed under the terms of the GNU General Public | 5 | * This software is licensed under the terms of the GNU General Public |
6 | * License version 2, as published by the Free Software Foundation, and | 6 | * License version 2, as published by the Free Software Foundation, and |
@@ -14,17 +14,40 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H | 16 | #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H |
17 | #define __ASM_ARCH_MSM_UNCOMPRESS_H | ||
18 | |||
19 | #include <asm/processor.h> | ||
20 | #include <mach/msm_iomap.h> | ||
21 | |||
22 | #define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)) | ||
23 | #define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c)) | ||
17 | 24 | ||
18 | #include "hardware.h" | 25 | #define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))) |
19 | #include "linux/io.h" | 26 | #define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10))) |
20 | #include "mach/msm_iomap.h" | 27 | #define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14))) |
28 | #define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40))) | ||
29 | #define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70))) | ||
21 | 30 | ||
22 | static void putc(int c) | 31 | static void putc(int c) |
23 | { | 32 | { |
24 | #if defined(MSM_DEBUG_UART_PHYS) | 33 | #if defined(MSM_DEBUG_UART_PHYS) |
25 | unsigned base = MSM_DEBUG_UART_PHYS; | 34 | #ifdef CONFIG_MSM_HAS_DEBUG_UART_HS |
26 | while (!(readl(base + 0x08) & 0x04)) ; | 35 | /* |
27 | writel(c, base + 0x0c); | 36 | * Wait for TX_READY to be set; but skip it if we have a |
37 | * TX underrun. | ||
38 | */ | ||
39 | if (UART_DM_SR & 0x08) | ||
40 | while (!(UART_DM_ISR & 0x80)) | ||
41 | cpu_relax(); | ||
42 | |||
43 | UART_DM_CR = 0x300; | ||
44 | UART_DM_NCHAR = 0x1; | ||
45 | UART_DM_TF = c; | ||
46 | #else | ||
47 | while (!(UART_CSR & 0x04)) | ||
48 | cpu_relax(); | ||
49 | UART_TF = c; | ||
50 | #endif | ||
28 | #endif | 51 | #endif |
29 | } | 52 | } |
30 | 53 | ||