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-rw-r--r--arch/arm/mach-mmp/Kconfig47
-rw-r--r--arch/arm/mach-mmp/Makefile15
-rw-r--r--arch/arm/mach-mmp/Makefile.boot1
-rw-r--r--arch/arm/mach-mmp/aspenite.c117
-rw-r--r--arch/arm/mach-mmp/clock.c83
-rw-r--r--arch/arm/mach-mmp/clock.h71
-rw-r--r--arch/arm/mach-mmp/common.c37
-rw-r--r--arch/arm/mach-mmp/common.h13
-rw-r--r--arch/arm/mach-mmp/devices.c69
-rw-r--r--arch/arm/mach-mmp/include/mach/addr-map.h34
-rw-r--r--arch/arm/mach-mmp/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mmp/include/mach/cputype.h30
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S23
-rw-r--r--arch/arm/mach-mmp/include/mach/devices.h37
-rw-r--r--arch/arm/mach-mmp/include/mach/dma.h13
-rw-r--r--arch/arm/mach-mmp/include/mach/entry-macro.S25
-rw-r--r--arch/arm/mach-mmp/include/mach/gpio.h36
-rw-r--r--arch/arm/mach-mmp/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-mmp/include/mach/io.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h119
-rw-r--r--arch/arm/mach-mmp/include/mach/memory.h14
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa168.h258
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa910.h157
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp.h37
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h23
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h23
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h78
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h36
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-icu.h31
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-timers.h44
-rw-r--r--arch/arm/mach-mmp/include/mach/system.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/timex.h9
-rw-r--r--arch/arm/mach-mmp/include/mach/uncompress.h41
-rw-r--r--arch/arm/mach-mmp/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-mmp/irq.c55
-rw-r--r--arch/arm/mach-mmp/pxa168.c111
-rw-r--r--arch/arm/mach-mmp/pxa910.c158
-rw-r--r--arch/arm/mach-mmp/tavorevb.c109
-rw-r--r--arch/arm/mach-mmp/time.c199
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c47
40 files changed, 2258 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
new file mode 100644
index 000000000000..c6a564fc4a7c
--- /dev/null
+++ b/arch/arm/mach-mmp/Kconfig
@@ -0,0 +1,47 @@
1if ARCH_MMP
2
3menu "Marvell PXA168/910 Implmentations"
4
5config MACH_ASPENITE
6 bool "Marvell's PXA168 Aspenite Development Board"
7 select CPU_PXA168
8 help
9 Say 'Y' here if you want to support the Marvell PXA168-based
10 Aspenite Development Board.
11
12config MACH_ZYLONITE2
13 bool "Marvell's PXA168 Zylonite2 Development Board"
14 select CPU_PXA168
15 help
16 Say 'Y' here if you want to support the Marvell PXA168-based
17 Zylonite2 Development Board.
18
19config MACH_TAVOREVB
20 bool "Marvell's PXA910 TavorEVB Development Board"
21 select CPU_PXA910
22 help
23 Say 'Y' here if you want to support the Marvell PXA910-based
24 TavorEVB Development Board.
25
26config MACH_TTC_DKB
27 bool "Marvell's PXA910 TavorEVB Development Board"
28 select CPU_PXA910
29 help
30 Say 'Y' here if you want to support the Marvell PXA910-based
31 TTC_DKB Development Board.
32
33endmenu
34
35config CPU_PXA168
36 bool
37 select CPU_MOHAWK
38 help
39 Select code specific to PXA168
40
41config CPU_PXA910
42 bool
43 select CPU_MOHAWK
44 help
45 Select code specific to PXA910
46
47endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
new file mode 100644
index 000000000000..6883e6584883
--- /dev/null
+++ b/arch/arm/mach-mmp/Makefile
@@ -0,0 +1,15 @@
1#
2# Makefile for Marvell's PXA168 processors line
3#
4
5obj-y += common.o clock.o devices.o irq.o time.o
6
7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o
9obj-$(CONFIG_CPU_PXA910) += pxa910.o
10
11# board support
12obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
13obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
14obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
15obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot
new file mode 100644
index 000000000000..574a4aa8321a
--- /dev/null
+++ b/arch/arm/mach-mmp/Makefile.boot
@@ -0,0 +1 @@
zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
new file mode 100644
index 000000000000..4562452d4074
--- /dev/null
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -0,0 +1,117 @@
1/*
2 * linux/arch/arm/mach-mmp/aspenite.c
3 *
4 * Support for the Marvell PXA168-based Aspenite and Zylonite2
5 * Development Platform.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * publishhed by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/smc91x.h>
16
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include <mach/addr-map.h>
20#include <mach/mfp-pxa168.h>
21#include <mach/pxa168.h>
22#include <mach/gpio.h>
23
24#include "common.h"
25
26static unsigned long common_pin_config[] __initdata = {
27 /* Data Flash Interface */
28 GPIO0_DFI_D15,
29 GPIO1_DFI_D14,
30 GPIO2_DFI_D13,
31 GPIO3_DFI_D12,
32 GPIO4_DFI_D11,
33 GPIO5_DFI_D10,
34 GPIO6_DFI_D9,
35 GPIO7_DFI_D8,
36 GPIO8_DFI_D7,
37 GPIO9_DFI_D6,
38 GPIO10_DFI_D5,
39 GPIO11_DFI_D4,
40 GPIO12_DFI_D3,
41 GPIO13_DFI_D2,
42 GPIO14_DFI_D1,
43 GPIO15_DFI_D0,
44
45 /* Static Memory Controller */
46 GPIO18_SMC_nCS0,
47 GPIO34_SMC_nCS1,
48 GPIO23_SMC_nLUA,
49 GPIO25_SMC_nLLA,
50 GPIO28_SMC_RDY,
51 GPIO29_SMC_SCLK,
52 GPIO35_SMC_BE1,
53 GPIO36_SMC_BE2,
54 GPIO27_GPIO, /* Ethernet IRQ */
55
56 /* UART1 */
57 GPIO107_UART1_RXD,
58 GPIO108_UART1_TXD,
59};
60
61static struct smc91x_platdata smc91x_info = {
62 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
63};
64
65static struct resource smc91x_resources[] = {
66 [0] = {
67 .start = SMC_CS1_PHYS_BASE + 0x300,
68 .end = SMC_CS1_PHYS_BASE + 0xfffff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = gpio_to_irq(27),
73 .end = gpio_to_irq(27),
74 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
75 }
76};
77
78static struct platform_device smc91x_device = {
79 .name = "smc91x",
80 .id = 0,
81 .dev = {
82 .platform_data = &smc91x_info,
83 },
84 .num_resources = ARRAY_SIZE(smc91x_resources),
85 .resource = smc91x_resources,
86};
87
88static void __init common_init(void)
89{
90 mfp_config(ARRAY_AND_SIZE(common_pin_config));
91
92 /* on-chip devices */
93 pxa168_add_uart(1);
94
95 /* off-chip devices */
96 platform_device_register(&smc91x_device);
97}
98
99MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
100 .phys_io = APB_PHYS_BASE,
101 .boot_params = 0x00000100,
102 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
103 .map_io = pxa_map_io,
104 .init_irq = pxa168_init_irq,
105 .timer = &pxa168_timer,
106 .init_machine = common_init,
107MACHINE_END
108
109MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
110 .phys_io = APB_PHYS_BASE,
111 .boot_params = 0x00000100,
112 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
113 .map_io = pxa_map_io,
114 .init_irq = pxa168_init_irq,
115 .timer = &pxa168_timer,
116 .init_machine = common_init,
117MACHINE_END
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
new file mode 100644
index 000000000000..2d9cc5a7122f
--- /dev/null
+++ b/arch/arm/mach-mmp/clock.c
@@ -0,0 +1,83 @@
1/*
2 * linux/arch/arm/mach-mmp/clock.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/spinlock.h>
13#include <linux/clk.h>
14#include <linux/io.h>
15
16#include <mach/regs-apbc.h>
17#include "clock.h"
18
19static void apbc_clk_enable(struct clk *clk)
20{
21 uint32_t clk_rst;
22
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
24 __raw_writel(clk_rst, clk->clk_rst);
25}
26
27static void apbc_clk_disable(struct clk *clk)
28{
29 __raw_writel(0, clk->clk_rst);
30}
31
32struct clkops apbc_clk_ops = {
33 .enable = apbc_clk_enable,
34 .disable = apbc_clk_disable,
35};
36
37static DEFINE_SPINLOCK(clocks_lock);
38
39int clk_enable(struct clk *clk)
40{
41 unsigned long flags;
42
43 spin_lock_irqsave(&clocks_lock, flags);
44 if (clk->enabled++ == 0)
45 clk->ops->enable(clk);
46 spin_unlock_irqrestore(&clocks_lock, flags);
47 return 0;
48}
49EXPORT_SYMBOL(clk_enable);
50
51void clk_disable(struct clk *clk)
52{
53 unsigned long flags;
54
55 WARN_ON(clk->enabled == 0);
56
57 spin_lock_irqsave(&clocks_lock, flags);
58 if (--clk->enabled == 0)
59 clk->ops->disable(clk);
60 spin_unlock_irqrestore(&clocks_lock, flags);
61}
62EXPORT_SYMBOL(clk_disable);
63
64unsigned long clk_get_rate(struct clk *clk)
65{
66 unsigned long rate;
67
68 if (clk->ops->getrate)
69 rate = clk->ops->getrate(clk);
70 else
71 rate = clk->rate;
72
73 return rate;
74}
75EXPORT_SYMBOL(clk_get_rate);
76
77void clks_register(struct clk_lookup *clks, size_t num)
78{
79 int i;
80
81 for (i = 0; i < num; i++)
82 clkdev_add(&clks[i]);
83}
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
new file mode 100644
index 000000000000..ed967e78e6a8
--- /dev/null
+++ b/arch/arm/mach-mmp/clock.h
@@ -0,0 +1,71 @@
1/*
2 * linux/arch/arm/mach-mmp/clock.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <asm/clkdev.h>
10
11struct clkops {
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14 unsigned long (*getrate)(struct clk *);
15};
16
17struct clk {
18 const struct clkops *ops;
19
20 void __iomem *clk_rst; /* clock reset control register */
21 int fnclksel; /* functional clock select (APBC) */
22 uint32_t enable_val; /* value for clock enable (APMU) */
23 unsigned long rate;
24 int enabled;
25};
26
27extern struct clkops apbc_clk_ops;
28
29#define APBC_CLK(_name, _reg, _fnclksel, _rate) \
30struct clk clk_##_name = { \
31 .clk_rst = (void __iomem *)APBC_##_reg, \
32 .fnclksel = _fnclksel, \
33 .rate = _rate, \
34 .ops = &apbc_clk_ops, \
35}
36
37#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
38struct clk clk_##_name = { \
39 .clk_rst = (void __iomem *)APBC_##_reg, \
40 .fnclksel = _fnclksel, \
41 .rate = _rate, \
42 .ops = _ops, \
43}
44
45#define APMU_CLK(_name, _reg, _eval, _rate) \
46struct clk clk_##_name = { \
47 .clk_rst = (void __iomem *)APMU_##_reg, \
48 .enable_val = _eval, \
49 .rate = _rate, \
50 .ops = &apmu_clk_ops, \
51}
52
53#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
54struct clk clk_##_name = { \
55 .clk_rst = (void __iomem *)APMU_##_reg, \
56 .enable_val = _eval, \
57 .rate = _rate, \
58 .ops = _ops, \
59}
60
61#define INIT_CLKREG(_clk, _devname, _conname) \
62 { \
63 .clk = _clk, \
64 .dev_id = _devname, \
65 .con_id = _conname, \
66 }
67
68extern struct clk clk_pxa168_gpio;
69extern struct clk clk_pxa168_timers;
70
71extern void clks_register(struct clk_lookup *, size_t);
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
new file mode 100644
index 000000000000..e1e66c18b446
--- /dev/null
+++ b/arch/arm/mach-mmp/common.c
@@ -0,0 +1,37 @@
1/*
2 * linux/arch/arm/mach-mmp/common.c
3 *
4 * Code common to PXA168 processor lines
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13
14#include <asm/page.h>
15#include <asm/mach/map.h>
16#include <mach/addr-map.h>
17
18#include "common.h"
19
20static struct map_desc standard_io_desc[] __initdata = {
21 {
22 .pfn = __phys_to_pfn(APB_PHYS_BASE),
23 .virtual = APB_VIRT_BASE,
24 .length = APB_PHYS_SIZE,
25 .type = MT_DEVICE,
26 }, {
27 .pfn = __phys_to_pfn(AXI_PHYS_BASE),
28 .virtual = AXI_VIRT_BASE,
29 .length = AXI_PHYS_SIZE,
30 .type = MT_DEVICE,
31 },
32};
33
34void __init pxa_map_io(void)
35{
36 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
37}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
new file mode 100644
index 000000000000..c33fbbc49417
--- /dev/null
+++ b/arch/arm/mach-mmp/common.h
@@ -0,0 +1,13 @@
1#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
2
3struct sys_timer;
4
5extern void timer_init(int irq);
6
7extern struct sys_timer pxa168_timer;
8extern struct sys_timer pxa910_timer;
9extern void __init pxa168_init_irq(void);
10extern void __init pxa910_init_irq(void);
11
12extern void __init icu_init_irq(void);
13extern void __init pxa_map_io(void);
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
new file mode 100644
index 000000000000..191d9dea8731
--- /dev/null
+++ b/arch/arm/mach-mmp/devices.c
@@ -0,0 +1,69 @@
1/*
2 * linux/arch/arm/mach-mmp/devices.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/dma-mapping.h>
12
13#include <asm/irq.h>
14#include <mach/devices.h>
15
16int __init pxa_register_device(struct pxa_device_desc *desc,
17 void *data, size_t size)
18{
19 struct platform_device *pdev;
20 struct resource res[2 + MAX_RESOURCE_DMA];
21 int i, ret = 0, nres = 0;
22
23 pdev = platform_device_alloc(desc->drv_name, desc->id);
24 if (pdev == NULL)
25 return -ENOMEM;
26
27 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
28
29 memset(res, 0, sizeof(res));
30
31 if (desc->start != -1ul && desc->size > 0) {
32 res[nres].start = desc->start;
33 res[nres].end = desc->start + desc->size - 1;
34 res[nres].flags = IORESOURCE_MEM;
35 nres++;
36 }
37
38 if (desc->irq != NO_IRQ) {
39 res[nres].start = desc->irq;
40 res[nres].end = desc->irq;
41 res[nres].flags = IORESOURCE_IRQ;
42 nres++;
43 }
44
45 for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
46 if (desc->dma[i] == 0)
47 break;
48
49 res[nres].start = desc->dma[i];
50 res[nres].end = desc->dma[i];
51 res[nres].flags = IORESOURCE_DMA;
52 }
53
54 ret = platform_device_add_resources(pdev, res, nres);
55 if (ret) {
56 platform_device_put(pdev);
57 return ret;
58 }
59
60 if (data && size) {
61 ret = platform_device_add_data(pdev, data, size);
62 if (ret) {
63 platform_device_put(pdev);
64 return ret;
65 }
66 }
67
68 return platform_device_add(pdev);
69}
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
new file mode 100644
index 000000000000..3254089a644d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -0,0 +1,34 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/addr-map.h
3 *
4 * Common address map definitions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ADDR_MAP_H
12#define __ASM_MACH_ADDR_MAP_H
13
14/* APB - Application Subsystem Peripheral Bus
15 *
16 * NOTE: the DMA controller registers are actually on the AXI fabric #1
17 * slave port to AHB/APB bridge, due to its close relationship to those
18 * peripherals on APB, let's count it into the ABP mapping area.
19 */
20#define APB_PHYS_BASE 0xd4000000
21#define APB_VIRT_BASE 0xfe000000
22#define APB_PHYS_SIZE 0x00200000
23
24#define AXI_PHYS_BASE 0xd4200000
25#define AXI_VIRT_BASE 0xfe200000
26#define AXI_PHYS_SIZE 0x00200000
27
28/* Static Memory Controller - Chip Select 0 and 1 */
29#define SMC_CS0_PHYS_BASE 0x80000000
30#define SMC_CS0_PHYS_SIZE 0x10000000
31#define SMC_CS1_PHYS_BASE 0x90000000
32#define SMC_CS1_PHYS_SIZE 0x10000000
33
34#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h
new file mode 100644
index 000000000000..2fb354e54e0d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
new file mode 100644
index 000000000000..25e797b09083
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -0,0 +1,30 @@
1#ifndef __ASM_MACH_CPUTYPE_H
2#define __ASM_MACH_CPUTYPE_H
3
4#include <asm/cputype.h>
5
6/*
7 * CPU Stepping OLD_ID CPU_ID CHIP_ID
8 *
9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333
10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910
11 */
12
13#ifdef CONFIG_CPU_PXA168
14# define __cpu_is_pxa168(id) \
15 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
16#else
17# define __cpu_is_pxa168(id) (0)
18#endif
19
20#ifdef CONFIG_CPU_PXA910
21# define __cpu_is_pxa910(id) \
22 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
23#else
24# define __cpu_is_pxa910(id) (0)
25#endif
26
27#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
28#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
29
30#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a850f87de51d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
1/* arch/arm/mach-mmp/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copied from arch/arm/mach-pxa/include/mach/debug.S
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <mach/addr-map.h>
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 ldreq \rx, =APB_PHYS_BASE @ physical
18 ldrne \rx, =APB_VIRT_BASE @ virtual
19 orr \rx, \rx, #0x00017000
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
new file mode 100644
index 000000000000..24585397217e
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -0,0 +1,37 @@
1#include <linux/types.h>
2
3#define MAX_RESOURCE_DMA 2
4
5/* structure for describing the on-chip devices */
6struct pxa_device_desc {
7 const char *dev_name;
8 const char *drv_name;
9 int id;
10 int irq;
11 unsigned long start;
12 unsigned long size;
13 int dma[MAX_RESOURCE_DMA];
14};
15
16#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
17struct pxa_device_desc pxa168_device_##_name __initdata = { \
18 .dev_name = "pxa168-" #_name, \
19 .drv_name = _drv, \
20 .id = _id, \
21 .irq = IRQ_PXA168_##_irq, \
22 .start = _start, \
23 .size = _size, \
24 .dma = { _dma }, \
25};
26
27#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
28struct pxa_device_desc pxa910_device_##_name __initdata = { \
29 .dev_name = "pxa910-" #_name, \
30 .drv_name = _drv, \
31 .id = _id, \
32 .irq = IRQ_PXA910_##_irq, \
33 .start = _start, \
34 .size = _size, \
35 .dma = { _dma }, \
36};
37extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h
new file mode 100644
index 000000000000..1d6914544da4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/dma.h
@@ -0,0 +1,13 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/dma.h
3 */
4
5#ifndef __ASM_MACH_DMA_H
6#define __ASM_MACH_DMA_H
7
8#include <mach/addr-map.h>
9
10#define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000)
11
12#include <plat/dma.h>
13#endif /* __ASM_MACH_DMA_H */
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6d3cd35478b5
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <mach/regs-icu.h>
10
11 .macro disable_fiq
12 .endm
13
14 .macro arch_ret_to_user, tmp1, tmp2
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =ICU_AP_IRQ_SEL_INT_NUM
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 ldr \tmp, [\base, #0]
23 and \irqnr, \tmp, #0x3f
24 tst \tmp, #(1 << 6)
25 .endm
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
new file mode 100644
index 000000000000..ab26d13295c4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -0,0 +1,36 @@
1#ifndef __ASM_MACH_GPIO_H
2#define __ASM_MACH_GPIO_H
3
4#include <mach/addr-map.h>
5#include <mach/irqs.h>
6#include <asm-generic/gpio.h>
7
8#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
9
10#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
11#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
12
13#define NR_BUILTIN_GPIO (128)
14
15#define gpio_to_bank(gpio) ((gpio) >> 5)
16#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio))
17#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START)
18
19
20#define __gpio_is_inverted(gpio) (0)
21#define __gpio_is_occupied(gpio) (0)
22
23/* NOTE: these macros are defined here to make optimization of
24 * gpio_{get,set}_value() to work when 'gpio' is a constant.
25 * Usage of these macros otherwise is no longer recommended,
26 * use generic GPIO API whenever possible.
27 */
28#define GPIO_bit(gpio) (1 << ((gpio) & 0x1f))
29
30#define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00)
31#define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c)
32#define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18)
33#define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24)
34
35#include <plat/gpio.h>
36#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h
new file mode 100644
index 000000000000..99264a5ce5e4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/hardware.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_MACH_HARDWARE_H
2#define __ASM_MACH_HARDWARE_H
3
4#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
new file mode 100644
index 000000000000..e7adf3d012c1
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -0,0 +1,21 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/io.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_IO_H
10#define __ASM_MACH_IO_H
11
12#define IO_SPACE_LIMIT 0xffffffff
13
14/*
15 * We don't actually have real ISA nor PCI buses, but there is so many
16 * drivers out there that might just work if we fake them...
17 */
18#define __io(a) __typesafe_io(a)
19#define __mem_pci(a) (a)
20
21#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
new file mode 100644
index 000000000000..e83e45ebf7a4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -0,0 +1,119 @@
1#ifndef __ASM_MACH_IRQS_H
2#define __ASM_MACH_IRQS_H
3
4/*
5 * Interrupt numbers for PXA168
6 */
7#define IRQ_PXA168_NONE (-1)
8#define IRQ_PXA168_SSP3 0
9#define IRQ_PXA168_SSP2 1
10#define IRQ_PXA168_SSP1 2
11#define IRQ_PXA168_SSP0 3
12#define IRQ_PXA168_PMIC_INT 4
13#define IRQ_PXA168_RTC_INT 5
14#define IRQ_PXA168_RTC_ALARM 6
15#define IRQ_PXA168_TWSI0 7
16#define IRQ_PXA168_GPU 8
17#define IRQ_PXA168_KEYPAD 9
18#define IRQ_PXA168_ONEWIRE 12
19#define IRQ_PXA168_TIMER1 13
20#define IRQ_PXA168_TIMER2 14
21#define IRQ_PXA168_TIMER3 15
22#define IRQ_PXA168_CMU 16
23#define IRQ_PXA168_SSP4 17
24#define IRQ_PXA168_MSP_WAKEUP 19
25#define IRQ_PXA168_CF_WAKEUP 20
26#define IRQ_PXA168_XD_WAKEUP 21
27#define IRQ_PXA168_MFU 22
28#define IRQ_PXA168_MSP 23
29#define IRQ_PXA168_CF 24
30#define IRQ_PXA168_XD 25
31#define IRQ_PXA168_DDR_INT 26
32#define IRQ_PXA168_UART1 27
33#define IRQ_PXA168_UART2 28
34#define IRQ_PXA168_WDT 35
35#define IRQ_PXA168_FRQ_CHANGE 38
36#define IRQ_PXA168_SDH1 39
37#define IRQ_PXA168_SDH2 40
38#define IRQ_PXA168_LCD 41
39#define IRQ_PXA168_CI 42
40#define IRQ_PXA168_USB1 44
41#define IRQ_PXA168_NAND 45
42#define IRQ_PXA168_HIFI_DMA 46
43#define IRQ_PXA168_DMA_INT0 47
44#define IRQ_PXA168_DMA_INT1 48
45#define IRQ_PXA168_GPIOX 49
46#define IRQ_PXA168_USB2 51
47#define IRQ_PXA168_AC97 57
48#define IRQ_PXA168_TWSI1 58
49#define IRQ_PXA168_PMU 60
50#define IRQ_PXA168_SM_INT 63
51
52/*
53 * Interrupt numbers for PXA910
54 */
55#define IRQ_PXA910_AIRQ 0
56#define IRQ_PXA910_SSP3 1
57#define IRQ_PXA910_SSP2 2
58#define IRQ_PXA910_SSP1 3
59#define IRQ_PXA910_PMIC_INT 4
60#define IRQ_PXA910_RTC_INT 5
61#define IRQ_PXA910_RTC_ALARM 6
62#define IRQ_PXA910_TWSI0 7
63#define IRQ_PXA910_GPU 8
64#define IRQ_PXA910_KEYPAD 9
65#define IRQ_PXA910_ROTARY 10
66#define IRQ_PXA910_TRACKBALL 11
67#define IRQ_PXA910_ONEWIRE 12
68#define IRQ_PXA910_AP1_TIMER1 13
69#define IRQ_PXA910_AP1_TIMER2 14
70#define IRQ_PXA910_AP1_TIMER3 15
71#define IRQ_PXA910_IPC_AP0 16
72#define IRQ_PXA910_IPC_AP1 17
73#define IRQ_PXA910_IPC_AP2 18
74#define IRQ_PXA910_IPC_AP3 19
75#define IRQ_PXA910_IPC_AP4 20
76#define IRQ_PXA910_IPC_CP0 21
77#define IRQ_PXA910_IPC_CP1 22
78#define IRQ_PXA910_IPC_CP2 23
79#define IRQ_PXA910_IPC_CP3 24
80#define IRQ_PXA910_IPC_CP4 25
81#define IRQ_PXA910_L2_DDR 26
82#define IRQ_PXA910_UART2 27
83#define IRQ_PXA910_UART3 28
84#define IRQ_PXA910_AP2_TIMER1 29
85#define IRQ_PXA910_AP2_TIMER2 30
86#define IRQ_PXA910_CP2_TIMER1 31
87#define IRQ_PXA910_CP2_TIMER2 32
88#define IRQ_PXA910_CP2_TIMER3 33
89#define IRQ_PXA910_GSSP 34
90#define IRQ_PXA910_CP2_WDT 35
91#define IRQ_PXA910_MAIN_PMU 36
92#define IRQ_PXA910_CP_FREQ_CHG 37
93#define IRQ_PXA910_AP_FREQ_CHG 38
94#define IRQ_PXA910_MMC 39
95#define IRQ_PXA910_AEU 40
96#define IRQ_PXA910_LCD 41
97#define IRQ_PXA910_CCIC 42
98#define IRQ_PXA910_IRE 43
99#define IRQ_PXA910_USB1 44
100#define IRQ_PXA910_NAND 45
101#define IRQ_PXA910_HIFI_DMA 46
102#define IRQ_PXA910_DMA_INT0 47
103#define IRQ_PXA910_DMA_INT1 48
104#define IRQ_PXA910_AP_GPIO 49
105#define IRQ_PXA910_AP2_TIMER3 50
106#define IRQ_PXA910_USB2 51
107#define IRQ_PXA910_TWSI1 54
108#define IRQ_PXA910_CP_GPIO 55
109#define IRQ_PXA910_UART1 59 /* Slow UART */
110#define IRQ_PXA910_AP_PMU 60
111#define IRQ_PXA910_SM_INT 63 /* from PinMux */
112
113#define IRQ_GPIO_START 64
114#define IRQ_GPIO_NUM 128
115#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
116
117#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM)
118
119#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
new file mode 100644
index 000000000000..bdb21d70714c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/memory.h
@@ -0,0 +1,14 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/memory.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_MEMORY_H
10#define __ASM_MACH_MEMORY_H
11
12#define PHYS_OFFSET UL(0x00000000)
13
14#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
new file mode 100644
index 000000000000..d0bdb6e3682b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -0,0 +1,258 @@
1#ifndef __ASM_MACH_MFP_PXA168_H
2#define __ASM_MACH_MFP_PXA168_H
3
4#include <mach/mfp.h>
5
6/* GPIO */
7#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
8#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
9#define GPIO2_GPIO MFP_CFG(GPIO2, AF5)
10#define GPIO3_GPIO MFP_CFG(GPIO3, AF5)
11#define GPIO4_GPIO MFP_CFG(GPIO4, AF5)
12#define GPIO5_GPIO MFP_CFG(GPIO5, AF5)
13#define GPIO6_GPIO MFP_CFG(GPIO6, AF5)
14#define GPIO7_GPIO MFP_CFG(GPIO7, AF5)
15#define GPIO8_GPIO MFP_CFG(GPIO8, AF5)
16#define GPIO9_GPIO MFP_CFG(GPIO9, AF5)
17#define GPIO10_GPIO MFP_CFG(GPIO10, AF5)
18#define GPIO11_GPIO MFP_CFG(GPIO11, AF5)
19#define GPIO12_GPIO MFP_CFG(GPIO12, AF5)
20#define GPIO13_GPIO MFP_CFG(GPIO13, AF5)
21#define GPIO14_GPIO MFP_CFG(GPIO14, AF5)
22#define GPIO15_GPIO MFP_CFG(GPIO15, AF5)
23#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
24#define GPIO17_GPIO MFP_CFG(GPIO17, AF5)
25#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
26#define GPIO19_GPIO MFP_CFG(GPIO19, AF5)
27#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
28#define GPIO21_GPIO MFP_CFG(GPIO21, AF5)
29#define GPIO22_GPIO MFP_CFG(GPIO22, AF5)
30#define GPIO23_GPIO MFP_CFG(GPIO23, AF5)
31#define GPIO24_GPIO MFP_CFG(GPIO24, AF5)
32#define GPIO25_GPIO MFP_CFG(GPIO25, AF5)
33#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
34#define GPIO27_GPIO MFP_CFG(GPIO27, AF5)
35#define GPIO28_GPIO MFP_CFG(GPIO28, AF5)
36#define GPIO29_GPIO MFP_CFG(GPIO29, AF5)
37#define GPIO30_GPIO MFP_CFG(GPIO30, AF5)
38#define GPIO31_GPIO MFP_CFG(GPIO31, AF5)
39#define GPIO32_GPIO MFP_CFG(GPIO32, AF5)
40#define GPIO33_GPIO MFP_CFG(GPIO33, AF5)
41#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
42#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
43#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
44#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
45#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
46#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
47#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
48#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
49#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
50#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
51#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
52#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
53#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
54#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
55#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
56#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
57#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
58#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
59#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
60#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
61#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
62#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
63#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
64#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
65#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
66#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
67#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
68#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
69#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
70#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
71#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
72#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
73#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
74#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
75#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
76#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
77#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
78#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
79#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
80#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
81#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
82#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
83#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
84#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
85#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
86#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
87#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
88#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
89#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
90#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
91#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
92#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
93#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
94#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
95#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
96#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
97#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
98#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
99#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
100#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
101#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
102#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
103#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
104#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
105#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
106#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
107#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
108#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
109#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
110#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
111#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
112#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
113#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
114#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
115#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
116#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
117#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
118#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
119#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
120#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
121#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
122#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
123#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
124#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
125#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
126#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
127#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
128#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
129#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
130
131/* DFI */
132#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0)
133#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0)
134#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0)
135#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0)
136#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0)
137#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0)
138#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0)
139#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0)
140#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0)
141#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0)
142#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0)
143#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0)
144#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0)
145#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0)
146#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0)
147#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0)
148
149#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0)
150#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0)
151#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0)
152#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0)
153
154/* NAND */
155#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1)
156#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0)
157#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0)
158#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0)
159#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0)
160#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1)
161#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1)
162
163/* Static Memory Controller */
164#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3)
165#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2)
166#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2)
167#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3)
168#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0)
169#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2)
170#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0)
171#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0)
172#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0)
173#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0)
174#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0)
175#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2)
176#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2)
177#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2)
178
179/* Compact Flash */
180#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3)
181#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3)
182#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3)
183#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3)
184#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3)
185#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3)
186#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3)
187#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3)
188#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3)
189#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
190
191/* UART1 */
192#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
193#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST)
194#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST)
195#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST)
196#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1)
197#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2)
198#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1)
199#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2)
200#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1)
201#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2)
202#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1)
203#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2)
204
205/* MMC1 */
206#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1)
207#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1)
208#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1)
209#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1)
210#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1)
211#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1)
212#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1)
213#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1)
214#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1)
215#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
216#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
217#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
218
219/* LCD */
220#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
221#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
222#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1)
223#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1)
224#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1)
225#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1)
226#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1)
227#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1)
228#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1)
229#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1)
230#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1)
231#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1)
232#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1)
233#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1)
234#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1)
235#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1)
236#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1)
237#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1)
238#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1)
239#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1)
240#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1)
241#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1)
242#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1)
243#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1)
244#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1)
245#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1)
246#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1)
247#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1)
248#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1)
249#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1)
250
251/* I2S */
252#define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6)
253#define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1)
254#define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1)
255#define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2)
256#define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2)
257
258#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
new file mode 100644
index 000000000000..48a1cbc7c56b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -0,0 +1,157 @@
1#ifndef __ASM_MACH_MFP_PXA910_H
2#define __ASM_MACH_MFP_PXA910_H
3
4#include <mach/mfp.h>
5
6/* UART2 */
7#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
8#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6)
9
10/* UART3 */
11#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4)
12#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4)
13
14/*IRDA*/
15#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0)
16
17/* SMC */
18#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0)
19#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0)
20#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
21#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
22#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1)
23#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1)
24
25/* I2C */
26#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2)
27#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2)
28
29/* SSP1 (I2S) */
30#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
31#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
32#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
33#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
34#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
35#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
36#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
37
38/* DFI */
39#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0)
40#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0)
41#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0)
42#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0)
43#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0)
44#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0)
45#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0)
46#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0)
47#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0)
48#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0)
49#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0)
50#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0)
51#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0)
52#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0)
53#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0)
54#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0)
55#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0)
56#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1)
57#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0)
58#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1)
59#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1)
60#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0)
61
62/*keypad*/
63#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
64#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
65#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
66#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
67#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
68#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
69#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
70#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
71#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
72#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
73#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
74#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
75#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
76#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
77#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
78#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
79#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
80#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
81#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
82#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
83
84/* LCD */
85#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1)
86#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1)
87#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1)
88#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1)
89#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1)
90#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1)
91#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1)
92#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1)
93#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1)
94#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1)
95#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1)
96#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1)
97#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1)
98#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1)
99#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1)
100#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1)
101#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1)
102#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1)
103#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1)
104#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1)
105#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1)
106#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1)
107#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1)
108#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1)
109#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1)
110#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1)
111#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1)
112#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1)
113
114#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3)
115#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3)
116#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3)
117#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3)
118
119#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0)
120
121/*smart panel*/
122#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0)
123#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0)
124#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0)
125
126/*1wire*/
127#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3)
128
129/*CCIC*/
130#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
131#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
132#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
133#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
134#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
135#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
136#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
137#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
138#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
139#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
140#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
141#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
142
143/* MMC1 */
144#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
145#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
146#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
147#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
148#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
149#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
150#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
151#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
152#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
153#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
154#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
155#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
156
157#endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
new file mode 100644
index 000000000000..277ea4cd0f9f
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp.h
@@ -0,0 +1,37 @@
1#ifndef __ASM_MACH_MFP_H
2#define __ASM_MACH_MFP_H
3
4#include <plat/mfp.h>
5
6/*
7 * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
8 * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
9 * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
10 *
11 * To cope with this difference and re-use the pxa3xx mfp code as much as
12 * possible, we make the following compromise:
13 *
14 * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
15 * 2. DRIVE strength definitions redefined to include the reserved bit10
16 * 3. Override MFP_CFG() and MFP_CFG_DRV()
17 * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
18 */
19
20#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
21#define MFP_DRIVE_SLOW (0x2 << 13)
22#define MFP_DRIVE_MEDIUM (0x4 << 13)
23#define MFP_DRIVE_FAST (0x8 << 13)
24
25#undef MFP_CFG
26#undef MFP_CFG_DRV
27#undef MFP_CFG_LPM
28#undef MFP_CFG_X
29#undef MFP_CFG_DEFAULT
30
31#define MFP_CFG(pin, af) \
32 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
33
34#define MFP_CFG_DRV(pin, af, drv) \
35 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
36
37#endif /* __ASM_MACH_MFP_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
new file mode 100644
index 000000000000..ef0a8a2076e9
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_PXA168_H
2#define __ASM_MACH_PXA168_H
3
4#include <mach/devices.h>
5
6extern struct pxa_device_desc pxa168_device_uart1;
7extern struct pxa_device_desc pxa168_device_uart2;
8
9static inline int pxa168_add_uart(int id)
10{
11 struct pxa_device_desc *d = NULL;
12
13 switch (id) {
14 case 1: d = &pxa168_device_uart1; break;
15 case 2: d = &pxa168_device_uart2; break;
16 }
17
18 if (d == NULL)
19 return -EINVAL;
20
21 return pxa_register_device(d, NULL, 0);
22}
23#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
new file mode 100644
index 000000000000..b7aeaf574c36
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_PXA910_H
2#define __ASM_MACH_PXA910_H
3
4#include <mach/devices.h>
5
6extern struct pxa_device_desc pxa910_device_uart1;
7extern struct pxa_device_desc pxa910_device_uart2;
8
9static inline int pxa910_add_uart(int id)
10{
11 struct pxa_device_desc *d = NULL;
12
13 switch (id) {
14 case 1: d = &pxa910_device_uart1; break;
15 case 2: d = &pxa910_device_uart2; break;
16 }
17
18 if (d == NULL)
19 return -EINVAL;
20
21 return pxa_register_device(d, NULL, 0);
22}
23#endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
new file mode 100644
index 000000000000..c6b8c9dc2026
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -0,0 +1,78 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
3 *
4 * Application Peripheral Bus Clock Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_APBC_H
12#define __ASM_MACH_REGS_APBC_H
13
14#include <mach/addr-map.h>
15
16#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000)
17#define APBC_REG(x) (APBC_VIRT_BASE + (x))
18
19/*
20 * APB clock register offsets for PXA168
21 */
22#define APBC_PXA168_UART1 APBC_REG(0x000)
23#define APBC_PXA168_UART2 APBC_REG(0x004)
24#define APBC_PXA168_GPIO APBC_REG(0x008)
25#define APBC_PXA168_PWM0 APBC_REG(0x00c)
26#define APBC_PXA168_PWM1 APBC_REG(0x010)
27#define APBC_PXA168_SSP1 APBC_REG(0x01c)
28#define APBC_PXA168_SSP2 APBC_REG(0x020)
29#define APBC_PXA168_RTC APBC_REG(0x028)
30#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
31#define APBC_PXA168_KPC APBC_REG(0x030)
32#define APBC_PXA168_TIMERS APBC_REG(0x034)
33#define APBC_PXA168_AIB APBC_REG(0x03c)
34#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
35#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
36#define APBC_PXA168_SSP3 APBC_REG(0x04c)
37#define APBC_PXA168_ASFAR APBC_REG(0x050)
38#define APBC_PXA168_ASSAR APBC_REG(0x054)
39#define APBC_PXA168_SSP4 APBC_REG(0x058)
40#define APBC_PXA168_SSP5 APBC_REG(0x05c)
41#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
42#define APBC_PXA168_UART3 APBC_REG(0x070)
43#define APBC_PXA168_AC97 APBC_REG(0x084)
44
45/*
46 * APB Clock register offsets for PXA910
47 */
48#define APBC_PXA910_UART0 APBC_REG(0x000)
49#define APBC_PXA910_UART1 APBC_REG(0x004)
50#define APBC_PXA910_GPIO APBC_REG(0x008)
51#define APBC_PXA910_PWM0 APBC_REG(0x00c)
52#define APBC_PXA910_PWM1 APBC_REG(0x010)
53#define APBC_PXA910_PWM2 APBC_REG(0x014)
54#define APBC_PXA910_PWM3 APBC_REG(0x018)
55#define APBC_PXA910_SSP1 APBC_REG(0x01c)
56#define APBC_PXA910_SSP2 APBC_REG(0x020)
57#define APBC_PXA910_IPC APBC_REG(0x024)
58#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
59#define APBC_PXA910_KPC APBC_REG(0x030)
60#define APBC_PXA910_TIMERS APBC_REG(0x034)
61#define APBC_PXA910_TBROT APBC_REG(0x038)
62#define APBC_PXA910_AIB APBC_REG(0x03c)
63#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
64#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
65#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
66#define APBC_PXA910_SSP3 APBC_REG(0x04c)
67#define APBC_PXA910_ASFAR APBC_REG(0x050)
68#define APBC_PXA910_ASSAR APBC_REG(0x054)
69
70/* Common APB clock register bit definitions */
71#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
72#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
73#define APBC_RST (1 << 2) /* Reset Generation */
74
75/* Functional Clock Selection Mask */
76#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
77
78#endif /* __ASM_MACH_REGS_APBC_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
new file mode 100644
index 000000000000..919030514120
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -0,0 +1,36 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h
3 *
4 * Application Subsystem Power Management Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_APMU_H
12#define __ASM_MACH_REGS_APMU_H
13
14#include <mach/addr-map.h>
15
16#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800)
17#define APMU_REG(x) (APMU_VIRT_BASE + (x))
18
19/* Clock Reset Control */
20#define APMU_IRE APMU_REG(0x048)
21#define APMU_LCD APMU_REG(0x04c)
22#define APMU_CCIC APMU_REG(0x050)
23#define APMU_SDH0 APMU_REG(0x054)
24#define APMU_SDH1 APMU_REG(0x058)
25#define APMU_USB APMU_REG(0x05c)
26#define APMU_NAND APMU_REG(0x060)
27#define APMU_DMA APMU_REG(0x064)
28#define APMU_GEU APMU_REG(0x068)
29#define APMU_BUS APMU_REG(0x06c)
30
31#define APMU_FNCLK_EN (1 << 4)
32#define APMU_AXICLK_EN (1 << 3)
33#define APMU_FNRST_DIS (1 << 1)
34#define APMU_AXIRST_DIS (1 << 0)
35
36#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h
new file mode 100644
index 000000000000..e5f08723e0cc
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-icu.h
@@ -0,0 +1,31 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-icu.h
3 *
4 * Interrupt Control Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ICU_H
12#define __ASM_MACH_ICU_H
13
14#include <mach/addr-map.h>
15
16#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
17#define ICU_REG(x) (ICU_VIRT_BASE + (x))
18
19#define ICU_INT_CONF(n) ICU_REG((n) << 2)
20#define ICU_INT_CONF_AP_INT (1 << 6)
21#define ICU_INT_CONF_CP_INT (1 << 5)
22#define ICU_INT_CONF_IRQ (1 << 4)
23#define ICU_INT_CONF_MASK (0xf)
24
25#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
30
31#endif /* __ASM_MACH_ICU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h
new file mode 100644
index 000000000000..45589fec9fc7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-timers.h
@@ -0,0 +1,44 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-timers.h
3 *
4 * Timers Module
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_REGS_TIMERS_H
12#define __ASM_MACH_REGS_TIMERS_H
13
14#include <mach/addr-map.h>
15
16#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
17#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
18
19#define TMR_CCR (0x0000)
20#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
21#define TMR_CR(n) (0x0028 + ((n) << 2))
22#define TMR_SR(n) (0x0034 + ((n) << 2))
23#define TMR_IER(n) (0x0040 + ((n) << 2))
24#define TMR_PLVR(n) (0x004c + ((n) << 2))
25#define TMR_PLCR(n) (0x0058 + ((n) << 2))
26#define TMR_WMER (0x0064)
27#define TMR_WMR (0x0068)
28#define TMR_WVR (0x006c)
29#define TMR_WSR (0x0070)
30#define TMR_ICR(n) (0x0074 + ((n) << 2))
31#define TMR_WICR (0x0080)
32#define TMR_CER (0x0084)
33#define TMR_CMR (0x0088)
34#define TMR_ILR(n) (0x008c + ((n) << 2))
35#define TMR_WCR (0x0098)
36#define TMR_WFAR (0x009c)
37#define TMR_WSAR (0x00A0)
38#define TMR_CVWR(n) (0x00A4 + ((n) << 2))
39
40#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0)
41#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2)
42#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5)
43
44#endif /* __ASM_MACH_REGS_TIMERS_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
new file mode 100644
index 000000000000..001edfefec19
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -0,0 +1,21 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/system.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_SYSTEM_H
10#define __ASM_MACH_SYSTEM_H
11
12static inline void arch_idle(void)
13{
14 cpu_do_idle();
15}
16
17static inline void arch_reset(char mode)
18{
19 cpu_reset(0);
20}
21#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h
new file mode 100644
index 000000000000..6cebbd0ca8f4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/timex.h
@@ -0,0 +1,9 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/timex.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#define CLOCK_TICK_RATE 3250000
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
new file mode 100644
index 000000000000..c93d5fa5865c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/mach-mmp/include/mach/uncompress.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/serial_reg.h>
10#include <mach/addr-map.h>
11
12#define UART1_BASE (APB_PHYS_BASE + 0x36000)
13#define UART2_BASE (APB_PHYS_BASE + 0x17000)
14#define UART3_BASE (APB_PHYS_BASE + 0x18000)
15
16static inline void putc(char c)
17{
18 volatile unsigned long *UART = (unsigned long *)UART2_BASE;
19
20 /* UART enabled? */
21 if (!(UART[UART_IER] & UART_IER_UUE))
22 return;
23
24 while (!(UART[UART_LSR] & UART_LSR_THRE))
25 barrier();
26
27 UART[UART_TX] = c;
28}
29
30/*
31 * This does not append a newline
32 */
33static inline void flush(void)
34{
35}
36
37/*
38 * nothing to do
39 */
40#define arch_decomp_setup()
41#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b60ccaf9fee7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 000000000000..52ff2f065eba
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,55 @@
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Bin Yang <bin.yang@marvell.com>
7 * Created: Sep 30, 2008
8 * Copyright: Marvell International Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18
19#include <mach/regs-icu.h>
20
21#include "common.h"
22
23#define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
24
25#define PRIORITY_DEFAULT 0x1
26#define PRIORITY_NONE 0x0 /* means IRQ disabled */
27
28static void icu_mask_irq(unsigned int irq)
29{
30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
31}
32
33static void icu_unmask_irq(unsigned int irq)
34{
35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
36}
37
38static struct irq_chip icu_irq_chip = {
39 .name = "icu_irq",
40 .ack = icu_mask_irq,
41 .mask = icu_mask_irq,
42 .unmask = icu_unmask_irq,
43};
44
45void __init icu_init_irq(void)
46{
47 int irq;
48
49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq);
51 set_irq_chip(irq, &icu_irq_chip);
52 set_irq_handler(irq, handle_level_irq);
53 set_irq_flags(irq, IRQF_VALID);
54 }
55}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
new file mode 100644
index 000000000000..ae924468658c
--- /dev/null
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -0,0 +1,111 @@
1/*
2 * linux/arch/arm/mach-mmp/pxa168.c
3 *
4 * Code specific to PXA168
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/list.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17
18#include <asm/mach/time.h>
19#include <mach/addr-map.h>
20#include <mach/cputype.h>
21#include <mach/regs-apbc.h>
22#include <mach/irqs.h>
23#include <mach/gpio.h>
24#include <mach/dma.h>
25#include <mach/devices.h>
26#include <mach/mfp.h>
27
28#include "common.h"
29#include "clock.h"
30
31#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
32
33static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
34{
35 MFP_ADDR_X(GPIO0, GPIO36, 0x04c),
36 MFP_ADDR_X(GPIO37, GPIO55, 0x000),
37 MFP_ADDR_X(GPIO56, GPIO123, 0x0e0),
38 MFP_ADDR_X(GPIO124, GPIO127, 0x0f4),
39
40 MFP_ADDR_END,
41};
42
43#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
44
45static void __init pxa168_init_gpio(void)
46{
47 int i;
48
49 /* enable GPIO clock */
50 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO);
51
52 /* unmask GPIO edge detection for all 4 banks - APMASKx */
53 for (i = 0; i < 4; i++)
54 __raw_writel(0xffffffff, APMASK(i));
55
56 pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL);
57}
58
59void __init pxa168_init_irq(void)
60{
61 icu_init_irq();
62 pxa168_init_gpio();
63}
64
65/* APB peripheral clocks */
66static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
67static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
68
69/* device and clock bindings */
70static struct clk_lookup pxa168_clkregs[] = {
71 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
72 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
73};
74
75static int __init pxa168_init(void)
76{
77 if (cpu_is_pxa168()) {
78 mfp_init_base(MFPR_VIRT_BASE);
79 mfp_init_addr(pxa168_mfp_addr_map);
80 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
81 clks_register(ARRAY_AND_SIZE(pxa168_clkregs));
82 }
83
84 return 0;
85}
86postcore_initcall(pxa168_init);
87
88/* system timer - clock enabled, 3.25MHz */
89#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
90
91static void __init pxa168_timer_init(void)
92{
93 /* this is early, we have to initialize the CCU registers by
94 * ourselves instead of using clk_* API. Clock rate is defined
95 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
96 */
97 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
98
99 /* 3.25MHz, bus/functional clock enabled, release reset */
100 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
101
102 timer_init(IRQ_PXA168_TIMER1);
103}
104
105struct sys_timer pxa168_timer = {
106 .init = pxa168_timer_init,
107};
108
109/* on-chip devices */
110PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
111PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
new file mode 100644
index 000000000000..453f8f7758bf
--- /dev/null
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -0,0 +1,158 @@
1/*
2 * linux/arch/arm/mach-mmp/pxa910.c
3 *
4 * Code specific to PXA910
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/list.h>
15#include <linux/io.h>
16
17#include <asm/mach/time.h>
18#include <mach/addr-map.h>
19#include <mach/regs-apbc.h>
20#include <mach/regs-apmu.h>
21#include <mach/cputype.h>
22#include <mach/irqs.h>
23#include <mach/gpio.h>
24#include <mach/dma.h>
25#include <mach/mfp.h>
26#include <mach/devices.h>
27
28#include "common.h"
29#include "clock.h"
30
31#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
32
33static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
34{
35 MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
36 MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
37 MFP_ADDR_X(GPIO100, GPIO109, 0x238),
38
39 MFP_ADDR(GPIO123, 0xcc),
40 MFP_ADDR(GPIO124, 0xd0),
41
42 MFP_ADDR(DF_IO0, 0x40),
43 MFP_ADDR(DF_IO1, 0x3c),
44 MFP_ADDR(DF_IO2, 0x38),
45 MFP_ADDR(DF_IO3, 0x34),
46 MFP_ADDR(DF_IO4, 0x30),
47 MFP_ADDR(DF_IO5, 0x2c),
48 MFP_ADDR(DF_IO6, 0x28),
49 MFP_ADDR(DF_IO7, 0x24),
50 MFP_ADDR(DF_IO8, 0x20),
51 MFP_ADDR(DF_IO9, 0x1c),
52 MFP_ADDR(DF_IO10, 0x18),
53 MFP_ADDR(DF_IO11, 0x14),
54 MFP_ADDR(DF_IO12, 0x10),
55 MFP_ADDR(DF_IO13, 0xc),
56 MFP_ADDR(DF_IO14, 0x8),
57 MFP_ADDR(DF_IO15, 0x4),
58
59 MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
60 MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
61 MFP_ADDR(SM_nCS0, 0x4c),
62 MFP_ADDR(SM_nCS1, 0x50),
63 MFP_ADDR(DF_WEn, 0x54),
64 MFP_ADDR(DF_REn, 0x58),
65 MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
66 MFP_ADDR(DF_ALE_SM_WEn, 0x60),
67 MFP_ADDR(SM_SCLK, 0x64),
68 MFP_ADDR(DF_RDY0, 0x68),
69 MFP_ADDR(SM_BE0, 0x6c),
70 MFP_ADDR(SM_BE1, 0x70),
71 MFP_ADDR(SM_ADV, 0x74),
72 MFP_ADDR(DF_RDY1, 0x78),
73 MFP_ADDR(SM_ADVMUX, 0x7c),
74 MFP_ADDR(SM_RDY, 0x80),
75
76 MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
77
78 MFP_ADDR_END,
79};
80
81#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
82
83static void __init pxa910_init_gpio(void)
84{
85 int i;
86
87 /* enable GPIO clock */
88 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
89
90 /* unmask GPIO edge detection for all 4 banks - APMASKx */
91 for (i = 0; i < 4; i++)
92 __raw_writel(0xffffffff, APMASK(i));
93
94 pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
95}
96
97void __init pxa910_init_irq(void)
98{
99 icu_init_irq();
100 pxa910_init_gpio();
101}
102
103/* APB peripheral clocks */
104static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
105static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
106
107/* device and clock bindings */
108static struct clk_lookup pxa910_clkregs[] = {
109 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
110 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
111};
112
113static int __init pxa910_init(void)
114{
115 if (cpu_is_pxa910()) {
116 mfp_init_base(MFPR_VIRT_BASE);
117 mfp_init_addr(pxa910_mfp_addr_map);
118 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
119 clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
120 }
121
122 return 0;
123}
124postcore_initcall(pxa910_init);
125
126/* system timer - clock enabled, 3.25MHz */
127#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
128
129static void __init pxa910_timer_init(void)
130{
131 /* reset and configure */
132 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
133 __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
134
135 timer_init(IRQ_PXA910_AP1_TIMER1);
136}
137
138struct sys_timer pxa910_timer = {
139 .init = pxa910_timer_init,
140};
141
142/* on-chip devices */
143
144/* NOTE: there are totally 3 UARTs on PXA910:
145 *
146 * UART1 - Slow UART (can be used both by AP and CP)
147 * UART2/3 - Fast UART
148 *
149 * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
150 * they are re-ordered as:
151 *
152 * pxa910_device_uart1 - UART2 as FFUART
153 * pxa910_device_uart2 - UART3 as BTUART
154 *
155 * UART1 is not used by AP for the moment.
156 */
157PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
158PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
new file mode 100644
index 000000000000..0e0c9220eaba
--- /dev/null
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -0,0 +1,109 @@
1/*
2 * linux/arch/arm/mach-mmp/tavorevb.c
3 *
4 * Support for the Marvell PXA910-based TavorEVB Development Platform.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/smc91x.h>
15
16#include <asm/mach-types.h>
17#include <asm/mach/arch.h>
18#include <mach/addr-map.h>
19#include <mach/mfp-pxa910.h>
20#include <mach/pxa910.h>
21#include <mach/gpio.h>
22
23#include "common.h"
24
25static unsigned long tavorevb_pin_config[] __initdata = {
26 /* UART2 */
27 GPIO47_UART2_RXD,
28 GPIO48_UART2_TXD,
29
30 /* SMC */
31 SM_nCS0_nCS0,
32 SM_ADV_SM_ADV,
33 SM_SCLK_SM_SCLK,
34 SM_SCLK_SM_SCLK,
35 SM_BE0_SM_BE0,
36 SM_BE1_SM_BE1,
37
38 /* DFI */
39 DF_IO0_ND_IO0,
40 DF_IO1_ND_IO1,
41 DF_IO2_ND_IO2,
42 DF_IO3_ND_IO3,
43 DF_IO4_ND_IO4,
44 DF_IO5_ND_IO5,
45 DF_IO6_ND_IO6,
46 DF_IO7_ND_IO7,
47 DF_IO8_ND_IO8,
48 DF_IO9_ND_IO9,
49 DF_IO10_ND_IO10,
50 DF_IO11_ND_IO11,
51 DF_IO12_ND_IO12,
52 DF_IO13_ND_IO13,
53 DF_IO14_ND_IO14,
54 DF_IO15_ND_IO15,
55 DF_nCS0_SM_nCS2_nCS0,
56 DF_ALE_SM_WEn_ND_ALE,
57 DF_CLE_SM_OEn_ND_CLE,
58 DF_WEn_DF_WEn,
59 DF_REn_DF_REn,
60 DF_RDY0_DF_RDY0,
61};
62
63static struct smc91x_platdata tavorevb_smc91x_info = {
64 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
65};
66
67static struct resource smc91x_resources[] = {
68 [0] = {
69 .start = SMC_CS1_PHYS_BASE + 0x300,
70 .end = SMC_CS1_PHYS_BASE + 0xfffff,
71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
74 .start = gpio_to_irq(80),
75 .end = gpio_to_irq(80),
76 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
77 }
78};
79
80static struct platform_device smc91x_device = {
81 .name = "smc91x",
82 .id = 0,
83 .dev = {
84 .platform_data = &tavorevb_smc91x_info,
85 },
86 .num_resources = ARRAY_SIZE(smc91x_resources),
87 .resource = smc91x_resources,
88};
89
90static void __init tavorevb_init(void)
91{
92 mfp_config(ARRAY_AND_SIZE(tavorevb_pin_config));
93
94 /* on-chip devices */
95 pxa910_add_uart(1);
96
97 /* off-chip devices */
98 platform_device_register(&smc91x_device);
99}
100
101MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
102 .phys_io = APB_PHYS_BASE,
103 .boot_params = 0x00000100,
104 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
105 .map_io = pxa_map_io,
106 .init_irq = pxa910_init_irq,
107 .timer = &pxa910_timer,
108 .init_machine = tavorevb_init,
109MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
new file mode 100644
index 000000000000..b03a6eda7419
--- /dev/null
+++ b/arch/arm/mach-mmp/time.c
@@ -0,0 +1,199 @@
1/*
2 * linux/arch/arm/mach-mmp/time.c
3 *
4 * Support for clocksource and clockevents
5 *
6 * Copyright (C) 2008 Marvell International Ltd.
7 * All rights reserved.
8 *
9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
10 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
11 *
12 * The timers module actually includes three timers, each timer with upto
13 * three match comparators. Timer #0 is used here in free-running mode as
14 * the clock source, and match comparator #1 used as clock event device.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/cnt32_to_63.h>
30
31#include <mach/addr-map.h>
32#include <mach/regs-timers.h>
33#include <mach/irqs.h>
34
35#include "clock.h"
36
37#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
38
39#define MAX_DELTA (0xfffffffe)
40#define MIN_DELTA (16)
41
42#define TCR2NS_SCALE_FACTOR 10
43
44static unsigned long tcr2ns_scale;
45
46static void __init set_tcr2ns_scale(unsigned long tcr_rate)
47{
48 unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR;
49 do_div(v, tcr_rate);
50 tcr2ns_scale = v;
51 /*
52 * We want an even value to automatically clear the top bit
53 * returned by cnt32_to_63() without an additional run time
54 * instruction. So if the LSB is 1 then round it up.
55 */
56 if (tcr2ns_scale & 1)
57 tcr2ns_scale++;
58}
59
60/*
61 * FIXME: the timer needs some delay to stablize the counter capture
62 */
63static inline uint32_t timer_read(void)
64{
65 int delay = 100;
66
67 __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0));
68
69 while (delay--)
70 cpu_relax();
71
72 return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
73}
74
75unsigned long long sched_clock(void)
76{
77 unsigned long long v = cnt32_to_63(timer_read());
78 return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR;
79}
80
81static irqreturn_t timer_interrupt(int irq, void *dev_id)
82{
83 struct clock_event_device *c = dev_id;
84
85 /* disable and clear pending interrupt status */
86 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
87 __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0));
88 c->event_handler(c);
89 return IRQ_HANDLED;
90}
91
92static int timer_set_next_event(unsigned long delta,
93 struct clock_event_device *dev)
94{
95 unsigned long flags, next;
96
97 local_irq_save(flags);
98
99 /* clear pending interrupt status and enable */
100 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
101 __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
102
103 next = timer_read() + delta;
104 __raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
105
106 local_irq_restore(flags);
107 return 0;
108}
109
110static void timer_set_mode(enum clock_event_mode mode,
111 struct clock_event_device *dev)
112{
113 unsigned long flags;
114
115 local_irq_save(flags);
116 switch (mode) {
117 case CLOCK_EVT_MODE_ONESHOT:
118 case CLOCK_EVT_MODE_UNUSED:
119 case CLOCK_EVT_MODE_SHUTDOWN:
120 /* disable the matching interrupt */
121 __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
122 break;
123 case CLOCK_EVT_MODE_RESUME:
124 case CLOCK_EVT_MODE_PERIODIC:
125 break;
126 }
127 local_irq_restore(flags);
128}
129
130static struct clock_event_device ckevt = {
131 .name = "clockevent",
132 .features = CLOCK_EVT_FEAT_ONESHOT,
133 .shift = 32,
134 .rating = 200,
135 .set_next_event = timer_set_next_event,
136 .set_mode = timer_set_mode,
137};
138
139static cycle_t clksrc_read(void)
140{
141 return timer_read();
142}
143
144static struct clocksource cksrc = {
145 .name = "clocksource",
146 .shift = 20,
147 .rating = 200,
148 .read = clksrc_read,
149 .mask = CLOCKSOURCE_MASK(32),
150 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
151};
152
153static void __init timer_config(void)
154{
155 uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
156 uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
157 uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
158
159 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
160
161 ccr &= TMR_CCR_CS_0(0x3);
162 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
163
164 /* free-running mode */
165 __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
166
167 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
168 __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
169 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
170
171 /* enable timer counter */
172 __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER);
173}
174
175static struct irqaction timer_irq = {
176 .name = "timer",
177 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
178 .handler = timer_interrupt,
179 .dev_id = &ckevt,
180};
181
182void __init timer_init(int irq)
183{
184 timer_config();
185
186 set_tcr2ns_scale(CLOCK_TICK_RATE);
187
188 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
189 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
190 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
191 ckevt.cpumask = cpumask_of(0);
192
193 cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
194
195 setup_irq(irq, &timer_irq);
196
197 clocksource_register(&cksrc);
198 clockevents_register_device(&ckevt);
199}
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
new file mode 100644
index 000000000000..08cfef6c92a2
--- /dev/null
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -0,0 +1,47 @@
1/*
2 * linux/arch/arm/mach-mmp/ttc_dkb.c
3 *
4 * Support for the Marvell PXA910-based TTC_DKB Development Platform.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/arch.h>
17#include <mach/addr-map.h>
18#include <mach/mfp-pxa910.h>
19#include <mach/pxa910.h>
20
21#include "common.h"
22
23#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
24
25static unsigned long ttc_dkb_pin_config[] __initdata = {
26 /* UART2 */
27 GPIO47_UART2_RXD,
28 GPIO48_UART2_TXD,
29};
30
31static void __init ttc_dkb_init(void)
32{
33 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
34
35 /* on-chip devices */
36 pxa910_add_uart(1);
37}
38
39MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
40 .phys_io = APB_PHYS_BASE,
41 .boot_params = 0x00000100,
42 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
43 .map_io = pxa_map_io,
44 .init_irq = pxa910_init_irq,
45 .timer = &pxa910_timer,
46 .init_machine = ttc_dkb_init,
47MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 19:57:18 -0500