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-rw-r--r--arch/arm/mach-mmp/irq.c445
1 files changed, 445 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 000000000000..3705470c9f1e
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,445 @@
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
6 *
7 * Author: Bin Yang <bin.yang@marvell.com>
8 * Haojian Zhuang <haojian.zhuang@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23
24#include <mach/irqs.h>
25
26#include "common.h"
27
28#define MAX_ICU_NR 16
29
30struct icu_chip_data {
31 int nr_irqs;
32 unsigned int virq_base;
33 unsigned int cascade_irq;
34 void __iomem *reg_status;
35 void __iomem *reg_mask;
36 unsigned int conf_enable;
37 unsigned int conf_disable;
38 unsigned int conf_mask;
39 unsigned int clr_mfp_irq_base;
40 unsigned int clr_mfp_hwirq;
41 struct irq_domain *domain;
42};
43
44struct mmp_intc_conf {
45 unsigned int conf_enable;
46 unsigned int conf_disable;
47 unsigned int conf_mask;
48};
49
50void __iomem *mmp_icu_base;
51static struct icu_chip_data icu_data[MAX_ICU_NR];
52static int max_icu_nr;
53
54extern void mmp2_clear_pmic_int(void);
55
56static void icu_mask_ack_irq(struct irq_data *d)
57{
58 struct irq_domain *domain = d->domain;
59 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
60 int hwirq;
61 u32 r;
62
63 hwirq = d->irq - data->virq_base;
64 if (data == &icu_data[0]) {
65 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
66 r &= ~data->conf_mask;
67 r |= data->conf_disable;
68 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
69 } else {
70#ifdef CONFIG_CPU_MMP2
71 if ((data->virq_base == data->clr_mfp_irq_base)
72 && (hwirq == data->clr_mfp_hwirq))
73 mmp2_clear_pmic_int();
74#endif
75 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
76 writel_relaxed(r, data->reg_mask);
77 }
78}
79
80static void icu_mask_irq(struct irq_data *d)
81{
82 struct irq_domain *domain = d->domain;
83 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
84 int hwirq;
85 u32 r;
86
87 hwirq = d->irq - data->virq_base;
88 if (data == &icu_data[0]) {
89 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
90 r &= ~data->conf_mask;
91 r |= data->conf_disable;
92 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
93 } else {
94 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
95 writel_relaxed(r, data->reg_mask);
96 }
97}
98
99static void icu_unmask_irq(struct irq_data *d)
100{
101 struct irq_domain *domain = d->domain;
102 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
103 int hwirq;
104 u32 r;
105
106 hwirq = d->irq - data->virq_base;
107 if (data == &icu_data[0]) {
108 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
109 r &= ~data->conf_mask;
110 r |= data->conf_enable;
111 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
112 } else {
113 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
114 writel_relaxed(r, data->reg_mask);
115 }
116}
117
118static struct irq_chip icu_irq_chip = {
119 .name = "icu_irq",
120 .irq_mask = icu_mask_irq,
121 .irq_mask_ack = icu_mask_ack_irq,
122 .irq_unmask = icu_unmask_irq,
123};
124
125static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
126{
127 struct irq_domain *domain;
128 struct icu_chip_data *data;
129 int i;
130 unsigned long mask, status, n;
131
132 for (i = 1; i < max_icu_nr; i++) {
133 if (irq == icu_data[i].cascade_irq) {
134 domain = icu_data[i].domain;
135 data = (struct icu_chip_data *)domain->host_data;
136 break;
137 }
138 }
139 if (i >= max_icu_nr) {
140 pr_err("Spurious irq %d in MMP INTC\n", irq);
141 return;
142 }
143
144 mask = readl_relaxed(data->reg_mask);
145 while (1) {
146 status = readl_relaxed(data->reg_status) & ~mask;
147 if (status == 0)
148 break;
149 n = find_first_bit(&status, BITS_PER_LONG);
150 while (n < BITS_PER_LONG) {
151 generic_handle_irq(icu_data[i].virq_base + n);
152 n = find_next_bit(&status, BITS_PER_LONG, n + 1);
153 }
154 }
155}
156
157static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
158 irq_hw_number_t hw)
159{
160 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
161 set_irq_flags(irq, IRQF_VALID);
162 return 0;
163}
164
165static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
166 const u32 *intspec, unsigned int intsize,
167 unsigned long *out_hwirq,
168 unsigned int *out_type)
169{
170 *out_hwirq = intspec[0];
171 return 0;
172}
173
174const struct irq_domain_ops mmp_irq_domain_ops = {
175 .map = mmp_irq_domain_map,
176 .xlate = mmp_irq_domain_xlate,
177};
178
179static struct mmp_intc_conf mmp_conf = {
180 .conf_enable = 0x51,
181 .conf_disable = 0x0,
182 .conf_mask = 0x7f,
183};
184
185static struct mmp_intc_conf mmp2_conf = {
186 .conf_enable = 0x20,
187 .conf_disable = 0x0,
188 .conf_mask = 0x7f,
189};
190
191/* MMP (ARMv5) */
192void __init icu_init_irq(void)
193{
194 int irq;
195
196 max_icu_nr = 1;
197 mmp_icu_base = ioremap(0xd4282000, 0x1000);
198 icu_data[0].conf_enable = mmp_conf.conf_enable;
199 icu_data[0].conf_disable = mmp_conf.conf_disable;
200 icu_data[0].conf_mask = mmp_conf.conf_mask;
201 icu_data[0].nr_irqs = 64;
202 icu_data[0].virq_base = 0;
203 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
204 &irq_domain_simple_ops,
205 &icu_data[0]);
206 for (irq = 0; irq < 64; irq++) {
207 icu_mask_irq(irq_get_irq_data(irq));
208 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
209 set_irq_flags(irq, IRQF_VALID);
210 }
211 irq_set_default_host(icu_data[0].domain);
212}
213
214/* MMP2 (ARMv7) */
215void __init mmp2_init_icu(void)
216{
217 int irq;
218
219 max_icu_nr = 8;
220 mmp_icu_base = ioremap(0xd4282000, 0x1000);
221 icu_data[0].conf_enable = mmp2_conf.conf_enable;
222 icu_data[0].conf_disable = mmp2_conf.conf_disable;
223 icu_data[0].conf_mask = mmp2_conf.conf_mask;
224 icu_data[0].nr_irqs = 64;
225 icu_data[0].virq_base = 0;
226 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
227 &irq_domain_simple_ops,
228 &icu_data[0]);
229 icu_data[1].reg_status = mmp_icu_base + 0x150;
230 icu_data[1].reg_mask = mmp_icu_base + 0x168;
231 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
232 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
233 icu_data[1].nr_irqs = 2;
234 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
235 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
236 icu_data[1].virq_base, 0,
237 &irq_domain_simple_ops,
238 &icu_data[1]);
239 icu_data[2].reg_status = mmp_icu_base + 0x154;
240 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
241 icu_data[2].nr_irqs = 2;
242 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
243 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
244 icu_data[2].virq_base, 0,
245 &irq_domain_simple_ops,
246 &icu_data[2]);
247 icu_data[3].reg_status = mmp_icu_base + 0x180;
248 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
249 icu_data[3].nr_irqs = 3;
250 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
251 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
252 icu_data[3].virq_base, 0,
253 &irq_domain_simple_ops,
254 &icu_data[3]);
255 icu_data[4].reg_status = mmp_icu_base + 0x158;
256 icu_data[4].reg_mask = mmp_icu_base + 0x170;
257 icu_data[4].nr_irqs = 5;
258 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
259 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
260 icu_data[4].virq_base, 0,
261 &irq_domain_simple_ops,
262 &icu_data[4]);
263 icu_data[5].reg_status = mmp_icu_base + 0x15c;
264 icu_data[5].reg_mask = mmp_icu_base + 0x174;
265 icu_data[5].nr_irqs = 15;
266 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
267 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
268 icu_data[5].virq_base, 0,
269 &irq_domain_simple_ops,
270 &icu_data[5]);
271 icu_data[6].reg_status = mmp_icu_base + 0x160;
272 icu_data[6].reg_mask = mmp_icu_base + 0x178;
273 icu_data[6].nr_irqs = 2;
274 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
275 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
276 icu_data[6].virq_base, 0,
277 &irq_domain_simple_ops,
278 &icu_data[6]);
279 icu_data[7].reg_status = mmp_icu_base + 0x188;
280 icu_data[7].reg_mask = mmp_icu_base + 0x184;
281 icu_data[7].nr_irqs = 2;
282 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
283 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
284 icu_data[7].virq_base, 0,
285 &irq_domain_simple_ops,
286 &icu_data[7]);
287 for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
288 icu_mask_irq(irq_get_irq_data(irq));
289 switch (irq) {
290 case IRQ_MMP2_PMIC_MUX:
291 case IRQ_MMP2_RTC_MUX:
292 case IRQ_MMP2_KEYPAD_MUX:
293 case IRQ_MMP2_TWSI_MUX:
294 case IRQ_MMP2_MISC_MUX:
295 case IRQ_MMP2_MIPI_HSI1_MUX:
296 case IRQ_MMP2_MIPI_HSI0_MUX:
297 irq_set_chip(irq, &icu_irq_chip);
298 irq_set_chained_handler(irq, icu_mux_irq_demux);
299 break;
300 default:
301 irq_set_chip_and_handler(irq, &icu_irq_chip,
302 handle_level_irq);
303 break;
304 }
305 set_irq_flags(irq, IRQF_VALID);
306 }
307 irq_set_default_host(icu_data[0].domain);
308}
309
310#ifdef CONFIG_OF
311static const struct of_device_id intc_ids[] __initconst = {
312 { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
313 { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
314 {}
315};
316
317static const struct of_device_id mmp_mux_irq_match[] __initconst = {
318 { .compatible = "mrvl,mmp2-mux-intc" },
319 {}
320};
321
322int __init mmp2_mux_init(struct device_node *parent)
323{
324 struct device_node *node;
325 const struct of_device_id *of_id;
326 struct resource res;
327 int i, irq_base, ret, irq;
328 u32 nr_irqs, mfp_irq;
329
330 node = parent;
331 max_icu_nr = 1;
332 for (i = 1; i < MAX_ICU_NR; i++) {
333 node = of_find_matching_node(node, mmp_mux_irq_match);
334 if (!node)
335 break;
336 of_id = of_match_node(&mmp_mux_irq_match[0], node);
337 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
338 &nr_irqs);
339 if (ret) {
340 pr_err("Not found mrvl,intc-nr-irqs property\n");
341 ret = -EINVAL;
342 goto err;
343 }
344 ret = of_address_to_resource(node, 0, &res);
345 if (ret < 0) {
346 pr_err("Not found reg property\n");
347 ret = -EINVAL;
348 goto err;
349 }
350 icu_data[i].reg_status = mmp_icu_base + res.start;
351 ret = of_address_to_resource(node, 1, &res);
352 if (ret < 0) {
353 pr_err("Not found reg property\n");
354 ret = -EINVAL;
355 goto err;
356 }
357 icu_data[i].reg_mask = mmp_icu_base + res.start;
358 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
359 if (!icu_data[i].cascade_irq) {
360 ret = -EINVAL;
361 goto err;
362 }
363
364 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
365 if (irq_base < 0) {
366 pr_err("Failed to allocate IRQ numbers for mux intc\n");
367 ret = irq_base;
368 goto err;
369 }
370 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
371 &mfp_irq)) {
372 icu_data[i].clr_mfp_irq_base = irq_base;
373 icu_data[i].clr_mfp_hwirq = mfp_irq;
374 }
375 irq_set_chained_handler(icu_data[i].cascade_irq,
376 icu_mux_irq_demux);
377 icu_data[i].nr_irqs = nr_irqs;
378 icu_data[i].virq_base = irq_base;
379 icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
380 irq_base, 0,
381 &mmp_irq_domain_ops,
382 &icu_data[i]);
383 for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
384 icu_mask_irq(irq_get_irq_data(irq));
385 }
386 max_icu_nr = i;
387 return 0;
388err:
389 of_node_put(node);
390 max_icu_nr = i;
391 return ret;
392}
393
394void __init mmp_dt_irq_init(void)
395{
396 struct device_node *node;
397 const struct of_device_id *of_id;
398 struct mmp_intc_conf *conf;
399 int nr_irqs, irq_base, ret, irq;
400
401 node = of_find_matching_node(NULL, intc_ids);
402 if (!node) {
403 pr_err("Failed to find interrupt controller in arch-mmp\n");
404 return;
405 }
406 of_id = of_match_node(intc_ids, node);
407 conf = of_id->data;
408
409 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
410 if (ret) {
411 pr_err("Not found mrvl,intc-nr-irqs property\n");
412 return;
413 }
414
415 mmp_icu_base = of_iomap(node, 0);
416 if (!mmp_icu_base) {
417 pr_err("Failed to get interrupt controller register\n");
418 return;
419 }
420
421 irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
422 if (irq_base < 0) {
423 pr_err("Failed to allocate IRQ numbers\n");
424 goto err;
425 } else if (irq_base != NR_IRQS_LEGACY) {
426 pr_err("ICU's irqbase should be started from 0\n");
427 goto err;
428 }
429 icu_data[0].conf_enable = conf->conf_enable;
430 icu_data[0].conf_disable = conf->conf_disable;
431 icu_data[0].conf_mask = conf->conf_mask;
432 icu_data[0].nr_irqs = nr_irqs;
433 icu_data[0].virq_base = 0;
434 icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
435 &mmp_irq_domain_ops,
436 &icu_data[0]);
437 irq_set_default_host(icu_data[0].domain);
438 for (irq = 0; irq < nr_irqs; irq++)
439 icu_mask_irq(irq_get_irq_data(irq));
440 mmp2_mux_init(node);
441 return;
442err:
443 iounmap(mmp_icu_base);
444}
445#endif
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