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-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h10
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h10
3 files changed, 31 insertions, 10 deletions
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index 02701196ea03..b379cdec4d38 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -5,10 +5,10 @@
5 * Interrupt numbers for PXA168 5 * Interrupt numbers for PXA168
6 */ 6 */
7#define IRQ_PXA168_NONE (-1) 7#define IRQ_PXA168_NONE (-1)
8#define IRQ_PXA168_SSP3 0 8#define IRQ_PXA168_SSP4 0
9#define IRQ_PXA168_SSP2 1 9#define IRQ_PXA168_SSP3 1
10#define IRQ_PXA168_SSP1 2 10#define IRQ_PXA168_SSP2 2
11#define IRQ_PXA168_SSP0 3 11#define IRQ_PXA168_SSP1 3
12#define IRQ_PXA168_PMIC_INT 4 12#define IRQ_PXA168_PMIC_INT 4
13#define IRQ_PXA168_RTC_INT 5 13#define IRQ_PXA168_RTC_INT 5
14#define IRQ_PXA168_RTC_ALARM 6 14#define IRQ_PXA168_RTC_ALARM 6
@@ -20,7 +20,7 @@
20#define IRQ_PXA168_TIMER2 14 20#define IRQ_PXA168_TIMER2 14
21#define IRQ_PXA168_TIMER3 15 21#define IRQ_PXA168_TIMER3 15
22#define IRQ_PXA168_CMU 16 22#define IRQ_PXA168_CMU 16
23#define IRQ_PXA168_SSP4 17 23#define IRQ_PXA168_SSP5 17
24#define IRQ_PXA168_MSP_WAKEUP 19 24#define IRQ_PXA168_MSP_WAKEUP 19
25#define IRQ_PXA168_CF_WAKEUP 20 25#define IRQ_PXA168_CF_WAKEUP 20
26#define IRQ_PXA168_XD_WAKEUP 21 26#define IRQ_PXA168_XD_WAKEUP 21
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 3ad612cbdf09..3b2bd5d5eb05 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,6 +14,11 @@ extern struct pxa_device_desc pxa168_device_pwm1;
14extern struct pxa_device_desc pxa168_device_pwm2; 14extern struct pxa_device_desc pxa168_device_pwm2;
15extern struct pxa_device_desc pxa168_device_pwm3; 15extern struct pxa_device_desc pxa168_device_pwm3;
16extern struct pxa_device_desc pxa168_device_pwm4; 16extern struct pxa_device_desc pxa168_device_pwm4;
17extern struct pxa_device_desc pxa168_device_ssp1;
18extern struct pxa_device_desc pxa168_device_ssp2;
19extern struct pxa_device_desc pxa168_device_ssp3;
20extern struct pxa_device_desc pxa168_device_ssp4;
21extern struct pxa_device_desc pxa168_device_ssp5;
17extern struct pxa_device_desc pxa168_device_nand; 22extern struct pxa_device_desc pxa168_device_nand;
18 23
19static inline int pxa168_add_uart(int id) 24static inline int pxa168_add_uart(int id)
@@ -67,6 +72,22 @@ static inline int pxa168_add_pwm(int id)
67 return pxa_register_device(d, NULL, 0); 72 return pxa_register_device(d, NULL, 0);
68} 73}
69 74
75static inline int pxa168_add_ssp(int id)
76{
77 struct pxa_device_desc *d = NULL;
78
79 switch (id) {
80 case 1: d = &pxa168_device_ssp1; break;
81 case 2: d = &pxa168_device_ssp2; break;
82 case 3: d = &pxa168_device_ssp3; break;
83 case 4: d = &pxa168_device_ssp4; break;
84 case 5: d = &pxa168_device_ssp5; break;
85 default:
86 return -EINVAL;
87 }
88 return pxa_register_device(d, NULL, 0);
89}
90
70static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) 91static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
71{ 92{
72 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); 93 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 712af03fd1af..1a96585336ba 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -26,8 +26,6 @@
26#define APBC_PXA168_PWM2 APBC_REG(0x010) 26#define APBC_PXA168_PWM2 APBC_REG(0x010)
27#define APBC_PXA168_PWM3 APBC_REG(0x014) 27#define APBC_PXA168_PWM3 APBC_REG(0x014)
28#define APBC_PXA168_PWM4 APBC_REG(0x018) 28#define APBC_PXA168_PWM4 APBC_REG(0x018)
29#define APBC_PXA168_SSP1 APBC_REG(0x01c)
30#define APBC_PXA168_SSP2 APBC_REG(0x020)
31#define APBC_PXA168_RTC APBC_REG(0x028) 29#define APBC_PXA168_RTC APBC_REG(0x028)
32#define APBC_PXA168_TWSI0 APBC_REG(0x02c) 30#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
33#define APBC_PXA168_KPC APBC_REG(0x030) 31#define APBC_PXA168_KPC APBC_REG(0x030)
@@ -35,14 +33,16 @@
35#define APBC_PXA168_AIB APBC_REG(0x03c) 33#define APBC_PXA168_AIB APBC_REG(0x03c)
36#define APBC_PXA168_SW_JTAG APBC_REG(0x040) 34#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
37#define APBC_PXA168_ONEWIRE APBC_REG(0x048) 35#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
38#define APBC_PXA168_SSP3 APBC_REG(0x04c)
39#define APBC_PXA168_ASFAR APBC_REG(0x050) 36#define APBC_PXA168_ASFAR APBC_REG(0x050)
40#define APBC_PXA168_ASSAR APBC_REG(0x054) 37#define APBC_PXA168_ASSAR APBC_REG(0x054)
41#define APBC_PXA168_SSP4 APBC_REG(0x058)
42#define APBC_PXA168_SSP5 APBC_REG(0x05c)
43#define APBC_PXA168_TWSI1 APBC_REG(0x06c) 38#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
44#define APBC_PXA168_UART3 APBC_REG(0x070) 39#define APBC_PXA168_UART3 APBC_REG(0x070)
45#define APBC_PXA168_AC97 APBC_REG(0x084) 40#define APBC_PXA168_AC97 APBC_REG(0x084)
41#define APBC_PXA168_SSP1 APBC_REG(0x81c)
42#define APBC_PXA168_SSP2 APBC_REG(0x820)
43#define APBC_PXA168_SSP3 APBC_REG(0x84c)
44#define APBC_PXA168_SSP4 APBC_REG(0x858)
45#define APBC_PXA168_SSP5 APBC_REG(0x85c)
46 46
47/* 47/*
48 * APB Clock register offsets for PXA910 48 * APB Clock register offsets for PXA910