diff options
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/irqs.h')
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/irqs.h | 115 |
1 files changed, 112 insertions, 3 deletions
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d68871b0f28c..02701196ea03 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h | |||
| @@ -113,10 +113,119 @@ | |||
| 113 | #define IRQ_PXA910_AP_PMU 60 | 113 | #define IRQ_PXA910_AP_PMU 60 |
| 114 | #define IRQ_PXA910_SM_INT 63 /* from PinMux */ | 114 | #define IRQ_PXA910_SM_INT 63 /* from PinMux */ |
| 115 | 115 | ||
| 116 | #define IRQ_GPIO_START 64 | 116 | /* |
| 117 | #define IRQ_GPIO_NUM 128 | 117 | * Interrupt numbers for MMP2 |
| 118 | */ | ||
| 119 | #define IRQ_MMP2_NONE (-1) | ||
| 120 | #define IRQ_MMP2_SSP1 0 | ||
| 121 | #define IRQ_MMP2_SSP2 1 | ||
| 122 | #define IRQ_MMP2_SSPA1 2 | ||
| 123 | #define IRQ_MMP2_SSPA2 3 | ||
| 124 | #define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ | ||
| 125 | #define IRQ_MMP2_RTC_MUX 5 | ||
| 126 | #define IRQ_MMP2_TWSI1 7 | ||
| 127 | #define IRQ_MMP2_GPU 8 | ||
| 128 | #define IRQ_MMP2_KEYPAD 9 | ||
| 129 | #define IRQ_MMP2_ROTARY 10 | ||
| 130 | #define IRQ_MMP2_TRACKBALL 11 | ||
| 131 | #define IRQ_MMP2_ONEWIRE 12 | ||
| 132 | #define IRQ_MMP2_TIMER1 13 | ||
| 133 | #define IRQ_MMP2_TIMER2 14 | ||
| 134 | #define IRQ_MMP2_TIMER3 15 | ||
| 135 | #define IRQ_MMP2_RIPC 16 | ||
| 136 | #define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ | ||
| 137 | #define IRQ_MMP2_HDMI 19 | ||
| 138 | #define IRQ_MMP2_SSP3 20 | ||
| 139 | #define IRQ_MMP2_SSP4 21 | ||
| 140 | #define IRQ_MMP2_USB_HS1 22 | ||
| 141 | #define IRQ_MMP2_USB_HS2 23 | ||
| 142 | #define IRQ_MMP2_UART3 24 | ||
| 143 | #define IRQ_MMP2_UART1 27 | ||
| 144 | #define IRQ_MMP2_UART2 28 | ||
| 145 | #define IRQ_MMP2_MIPI_DSI 29 | ||
| 146 | #define IRQ_MMP2_CI2 30 | ||
| 147 | #define IRQ_MMP2_PMU_TIMER1 31 | ||
| 148 | #define IRQ_MMP2_PMU_TIMER2 32 | ||
| 149 | #define IRQ_MMP2_PMU_TIMER3 33 | ||
| 150 | #define IRQ_MMP2_USB_FS 34 | ||
| 151 | #define IRQ_MMP2_MISC_MUX 35 | ||
| 152 | #define IRQ_MMP2_WDT1 36 | ||
| 153 | #define IRQ_MMP2_NAND_DMA 37 | ||
| 154 | #define IRQ_MMP2_USIM 38 | ||
| 155 | #define IRQ_MMP2_MMC 39 | ||
| 156 | #define IRQ_MMP2_WTM 40 | ||
| 157 | #define IRQ_MMP2_LCD 41 | ||
| 158 | #define IRQ_MMP2_CI 42 | ||
| 159 | #define IRQ_MMP2_IRE 43 | ||
| 160 | #define IRQ_MMP2_USB_OTG 44 | ||
| 161 | #define IRQ_MMP2_NAND 45 | ||
| 162 | #define IRQ_MMP2_UART4 46 | ||
| 163 | #define IRQ_MMP2_DMA_FIQ 47 | ||
| 164 | #define IRQ_MMP2_DMA_RIQ 48 | ||
| 165 | #define IRQ_MMP2_GPIO 49 | ||
| 166 | #define IRQ_MMP2_SSP_MUX 51 | ||
| 167 | #define IRQ_MMP2_MMC2 52 | ||
| 168 | #define IRQ_MMP2_MMC3 53 | ||
| 169 | #define IRQ_MMP2_MMC4 54 | ||
| 170 | #define IRQ_MMP2_MIPI_HSI 55 | ||
| 171 | #define IRQ_MMP2_MSP 58 | ||
| 172 | #define IRQ_MMP2_MIPI_SLIM_DMA 59 | ||
| 173 | #define IRQ_MMP2_PJ4_FREQ_CHG 60 | ||
| 174 | #define IRQ_MMP2_MIPI_SLIM 62 | ||
| 175 | #define IRQ_MMP2_SM 63 | ||
| 176 | |||
| 177 | #define IRQ_MMP2_MUX_BASE 64 | ||
| 178 | |||
| 179 | /* secondary interrupt of INT #4 */ | ||
| 180 | #define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) | ||
| 181 | #define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) | ||
| 182 | #define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) | ||
| 183 | |||
| 184 | /* secondary interrupt of INT #5 */ | ||
| 185 | #define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) | ||
| 186 | #define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) | ||
| 187 | #define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) | ||
| 188 | |||
| 189 | /* secondary interrupt of INT #17 */ | ||
| 190 | #define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) | ||
| 191 | #define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) | ||
| 192 | #define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) | ||
| 193 | #define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) | ||
| 194 | #define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) | ||
| 195 | #define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) | ||
| 196 | |||
| 197 | /* secondary interrupt of INT #35 */ | ||
| 198 | #define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) | ||
| 199 | #define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) | ||
| 200 | #define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) | ||
| 201 | #define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) | ||
| 202 | #define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) | ||
| 203 | #define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) | ||
| 204 | #define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) | ||
| 205 | #define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) | ||
| 206 | #define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) | ||
| 207 | #define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) | ||
| 208 | #define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) | ||
| 209 | #define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) | ||
| 210 | #define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) | ||
| 211 | #define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) | ||
| 212 | #define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) | ||
| 213 | |||
| 214 | /* secondary interrupt of INT #51 */ | ||
| 215 | #define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) | ||
| 216 | #define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) | ||
| 217 | #define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) | ||
| 218 | |||
| 219 | #define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) | ||
| 220 | |||
| 221 | #define IRQ_GPIO_START 128 | ||
| 222 | #define IRQ_GPIO_NUM 192 | ||
| 118 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) | 223 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) |
| 119 | 224 | ||
| 120 | #define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) | 225 | /* Board IRQ - 64 by default, increase if not enough */ |
| 226 | #define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) | ||
| 227 | #define IRQ_BOARD_END (IRQ_BOARD_START + 64) | ||
| 228 | |||
| 229 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 121 | 230 | ||
| 122 | #endif /* __ASM_MACH_IRQS_H */ | 231 | #endif /* __ASM_MACH_IRQS_H */ |