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-rw-r--r--arch/arm/mach-lpc32xx/Kconfig26
-rw-r--r--arch/arm/mach-lpc32xx/clock.c77
-rw-r--r--arch/arm/mach-lpc32xx/common.c188
-rw-r--r--arch/arm/mach-lpc32xx/common.h14
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/i2c.h63
-rw-r--r--arch/arm/mach-lpc32xx/irq.c78
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c149
7 files changed, 158 insertions, 437 deletions
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 75946ac89ee9..e0b3eee83834 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,30 +29,4 @@ config ARCH_LPC32XX_UART6_SELECT
29 29
30endmenu 30endmenu
31 31
32menu "LPC32XX chip components"
33
34config ARCH_LPC32XX_IRAM_FOR_NET
35 bool "Use IRAM for network buffers"
36 default y
37 help
38 Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
39 network buffer. If the total combined required buffer sizes is
40 larger than the size of IRAM, then SDRAM will be used instead.
41
42 This can be enabled safely if the IRAM is not intended for other
43 uses.
44
45config ARCH_LPC32XX_MII_SUPPORT
46 bool "Check to enable MII support or leave disabled for RMII support"
47 help
48 Say Y here to enable MII support, or N for RMII support. Regardless of
49 which support is selected, the ethernet interface driver needs to be
50 selected in the device driver networking section.
51
52 The PHY3250 reference board uses RMII, so users of this board should
53 say N.
54
55endmenu
56
57endif 32endif
58
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 2fc24ca12054..f6a3ffec1f4b 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1095,49 +1095,42 @@ struct clk *clk_get_parent(struct clk *clk)
1095} 1095}
1096EXPORT_SYMBOL(clk_get_parent); 1096EXPORT_SYMBOL(clk_get_parent);
1097 1097
1098#define _REGISTER_CLOCK(d, n, c) \
1099 { \
1100 .dev_id = (d), \
1101 .con_id = (n), \
1102 .clk = &(c), \
1103 },
1104
1105static struct clk_lookup lookups[] = { 1098static struct clk_lookup lookups[] = {
1106 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz) 1099 CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
1107 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397) 1100 CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
1108 _REGISTER_CLOCK(NULL, "osc_main", osc_main) 1101 CLKDEV_INIT(NULL, "osc_main", &osc_main),
1109 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys) 1102 CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
1110 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll) 1103 CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
1111 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll) 1104 CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
1112 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk) 1105 CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
1113 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk) 1106 CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
1114 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0) 1107 CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
1115 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1) 1108 CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
1116 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2) 1109 CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
1117 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3) 1110 CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
1118 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9) 1111 CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
1119 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma) 1112 CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
1120 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt) 1113 CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
1121 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3) 1114 CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
1122 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4) 1115 CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
1123 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5) 1116 CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
1124 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6) 1117 CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
1125 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0) 1118 CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
1126 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1) 1119 CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
1127 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2) 1120 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
1128 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0) 1121 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1129 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) 1122 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
1130 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) 1123 CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
1131 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) 1124 CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
1132 _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc) 1125 CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
1133 _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0) 1126 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1134 _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1) 1127 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
1135 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) 1128 CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
1136 _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc) 1129 CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
1137 _REGISTER_CLOCK("lpc-eth.0", NULL, clk_net) 1130 CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
1138 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) 1131 CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
1139 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) 1132 CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
1140 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc) 1133 CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
1141}; 1134};
1142 1135
1143static int __init clk_init(void) 1136static int __init clk_init(void)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index bbbf063a74c2..5c96057b6d78 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -27,186 +27,11 @@
27 27
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29 29
30#include <mach/i2c.h>
31#include <mach/hardware.h> 30#include <mach/hardware.h>
32#include <mach/platform.h> 31#include <mach/platform.h>
33#include "common.h" 32#include "common.h"
34 33
35/* 34/*
36 * Watchdog timer
37 */
38static struct resource watchdog_resources[] = {
39 [0] = {
40 .start = LPC32XX_WDTIM_BASE,
41 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44};
45
46struct platform_device lpc32xx_watchdog_device = {
47 .name = "pnx4008-watchdog",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(watchdog_resources),
50 .resource = watchdog_resources,
51};
52
53/*
54 * I2C busses
55 */
56static struct i2c_pnx_data i2c0_data = {
57 .name = I2C_CHIP_NAME "1",
58 .base = LPC32XX_I2C1_BASE,
59 .irq = IRQ_LPC32XX_I2C_1,
60};
61
62static struct i2c_pnx_data i2c1_data = {
63 .name = I2C_CHIP_NAME "2",
64 .base = LPC32XX_I2C2_BASE,
65 .irq = IRQ_LPC32XX_I2C_2,
66};
67
68static struct i2c_pnx_data i2c2_data = {
69 .name = "USB-I2C",
70 .base = LPC32XX_OTG_I2C_BASE,
71 .irq = IRQ_LPC32XX_USB_I2C,
72};
73
74struct platform_device lpc32xx_i2c0_device = {
75 .name = "pnx-i2c",
76 .id = 0,
77 .dev = {
78 .platform_data = &i2c0_data,
79 },
80};
81
82struct platform_device lpc32xx_i2c1_device = {
83 .name = "pnx-i2c",
84 .id = 1,
85 .dev = {
86 .platform_data = &i2c1_data,
87 },
88};
89
90struct platform_device lpc32xx_i2c2_device = {
91 .name = "pnx-i2c",
92 .id = 2,
93 .dev = {
94 .platform_data = &i2c2_data,
95 },
96};
97
98/* TSC (Touch Screen Controller) */
99
100static struct resource lpc32xx_tsc_resources[] = {
101 {
102 .start = LPC32XX_ADC_BASE,
103 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
104 .flags = IORESOURCE_MEM,
105 }, {
106 .start = IRQ_LPC32XX_TS_IRQ,
107 .end = IRQ_LPC32XX_TS_IRQ,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112struct platform_device lpc32xx_tsc_device = {
113 .name = "ts-lpc32xx",
114 .id = -1,
115 .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
116 .resource = lpc32xx_tsc_resources,
117};
118
119/* RTC */
120
121static struct resource lpc32xx_rtc_resources[] = {
122 {
123 .start = LPC32XX_RTC_BASE,
124 .end = LPC32XX_RTC_BASE + SZ_4K - 1,
125 .flags = IORESOURCE_MEM,
126 },{
127 .start = IRQ_LPC32XX_RTC,
128 .end = IRQ_LPC32XX_RTC,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133struct platform_device lpc32xx_rtc_device = {
134 .name = "rtc-lpc32xx",
135 .id = -1,
136 .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
137 .resource = lpc32xx_rtc_resources,
138};
139
140/*
141 * ADC support
142 */
143static struct resource adc_resources[] = {
144 {
145 .start = LPC32XX_ADC_BASE,
146 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
147 .flags = IORESOURCE_MEM,
148 }, {
149 .start = IRQ_LPC32XX_TS_IRQ,
150 .end = IRQ_LPC32XX_TS_IRQ,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155struct platform_device lpc32xx_adc_device = {
156 .name = "lpc32xx-adc",
157 .id = -1,
158 .num_resources = ARRAY_SIZE(adc_resources),
159 .resource = adc_resources,
160};
161
162/*
163 * USB support
164 */
165/* The dmamask must be set for OHCI to work */
166static u64 ohci_dmamask = ~(u32) 0;
167static struct resource ohci_resources[] = {
168 {
169 .start = IO_ADDRESS(LPC32XX_USB_BASE),
170 .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_LPC32XX_USB_HOST,
174 .flags = IORESOURCE_IRQ,
175 },
176};
177struct platform_device lpc32xx_ohci_device = {
178 .name = "usb-ohci",
179 .id = -1,
180 .dev = {
181 .dma_mask = &ohci_dmamask,
182 .coherent_dma_mask = 0xFFFFFFFF,
183 },
184 .num_resources = ARRAY_SIZE(ohci_resources),
185 .resource = ohci_resources,
186};
187
188/*
189 * Network Support
190 */
191static struct resource net_resources[] = {
192 [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
193 [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
194 [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
195};
196
197static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
198struct platform_device lpc32xx_net_device = {
199 .name = "lpc-eth",
200 .id = 0,
201 .dev = {
202 .dma_mask = &lpc32xx_mac_dma_mask,
203 .coherent_dma_mask = 0xffffffffUL,
204 },
205 .num_resources = ARRAY_SIZE(net_resources),
206 .resource = net_resources,
207};
208
209/*
210 * Returns the unique ID for the device 35 * Returns the unique ID for the device
211 */ 36 */
212void lpc32xx_get_uid(u32 devid[4]) 37void lpc32xx_get_uid(u32 devid[4])
@@ -398,3 +223,16 @@ void lpc23xx_restart(char mode, const char *cmd)
398 while (1) 223 while (1)
399 ; 224 ;
400} 225}
226
227static int __init lpc32xx_display_uid(void)
228{
229 u32 uid[4];
230
231 lpc32xx_get_uid(uid);
232
233 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
234 uid[3], uid[2], uid[1], uid[0]);
235
236 return 1;
237}
238arch_initcall(lpc32xx_display_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 68e45e8c9486..afeac3b1fae6 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -23,26 +23,12 @@
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25/* 25/*
26 * Arch specific platform device structures
27 */
28extern struct platform_device lpc32xx_watchdog_device;
29extern struct platform_device lpc32xx_i2c0_device;
30extern struct platform_device lpc32xx_i2c1_device;
31extern struct platform_device lpc32xx_i2c2_device;
32extern struct platform_device lpc32xx_tsc_device;
33extern struct platform_device lpc32xx_adc_device;
34extern struct platform_device lpc32xx_rtc_device;
35extern struct platform_device lpc32xx_ohci_device;
36extern struct platform_device lpc32xx_net_device;
37
38/*
39 * Other arch specific structures and functions 26 * Other arch specific structures and functions
40 */ 27 */
41extern struct sys_timer lpc32xx_timer; 28extern struct sys_timer lpc32xx_timer;
42extern void __init lpc32xx_init_irq(void); 29extern void __init lpc32xx_init_irq(void);
43extern void __init lpc32xx_map_io(void); 30extern void __init lpc32xx_map_io(void);
44extern void __init lpc32xx_serial_init(void); 31extern void __init lpc32xx_serial_init(void);
45extern void __init lpc32xx_gpio_init(void);
46extern void lpc23xx_restart(char, const char *); 32extern void lpc23xx_restart(char, const char *);
47 33
48 34
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
deleted file mode 100644
index 034dc9286bcc..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/i2c.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * PNX4008-specific tweaks for I2C IP3204 block
3 *
4 * Author: Vitaly Wool <vwool@ru.mvista.com>
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifndef __ASM_ARCH_I2C_H
13#define __ASM_ARCH_I2C_H
14
15enum {
16 mstatus_tdi = 0x00000001,
17 mstatus_afi = 0x00000002,
18 mstatus_nai = 0x00000004,
19 mstatus_drmi = 0x00000008,
20 mstatus_active = 0x00000020,
21 mstatus_scl = 0x00000040,
22 mstatus_sda = 0x00000080,
23 mstatus_rff = 0x00000100,
24 mstatus_rfe = 0x00000200,
25 mstatus_tff = 0x00000400,
26 mstatus_tfe = 0x00000800,
27};
28
29enum {
30 mcntrl_tdie = 0x00000001,
31 mcntrl_afie = 0x00000002,
32 mcntrl_naie = 0x00000004,
33 mcntrl_drmie = 0x00000008,
34 mcntrl_daie = 0x00000020,
35 mcntrl_rffie = 0x00000040,
36 mcntrl_tffie = 0x00000080,
37 mcntrl_reset = 0x00000100,
38 mcntrl_cdbmode = 0x00000400,
39};
40
41enum {
42 rw_bit = 1 << 0,
43 start_bit = 1 << 8,
44 stop_bit = 1 << 9,
45};
46
47#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
48#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
49#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
50#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
51#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
52#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
53#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
54#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
55#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
56#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
57#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
58#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
59#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
60
61#define I2C_CHIP_NAME "PNX4008-I2C"
62
63#endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index d080cb1123dd..5b1cc35e6fba 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -22,6 +22,11 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/err.h> 23#include <linux/err.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/irqdomain.h>
29#include <linux/module.h>
25 30
26#include <mach/irqs.h> 31#include <mach/irqs.h>
27#include <mach/hardware.h> 32#include <mach/hardware.h>
@@ -44,6 +49,9 @@
44#define SIC1_ATR_DEFAULT 0x00026000 49#define SIC1_ATR_DEFAULT 0x00026000
45#define SIC2_ATR_DEFAULT 0x00000000 50#define SIC2_ATR_DEFAULT 0x00000000
46 51
52static struct irq_domain *lpc32xx_mic_domain;
53static struct device_node *lpc32xx_mic_np;
54
47struct lpc32xx_event_group_regs { 55struct lpc32xx_event_group_regs {
48 void __iomem *enab_reg; 56 void __iomem *enab_reg;
49 void __iomem *edge_reg; 57 void __iomem *edge_reg;
@@ -203,7 +211,7 @@ static void lpc32xx_mask_irq(struct irq_data *d)
203{ 211{
204 unsigned int reg, ctrl, mask; 212 unsigned int reg, ctrl, mask;
205 213
206 get_controller(d->irq, &ctrl, &mask); 214 get_controller(d->hwirq, &ctrl, &mask);
207 215
208 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; 216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
209 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -213,7 +221,7 @@ static void lpc32xx_unmask_irq(struct irq_data *d)
213{ 221{
214 unsigned int reg, ctrl, mask; 222 unsigned int reg, ctrl, mask;
215 223
216 get_controller(d->irq, &ctrl, &mask); 224 get_controller(d->hwirq, &ctrl, &mask);
217 225
218 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; 226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
219 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -223,14 +231,14 @@ static void lpc32xx_ack_irq(struct irq_data *d)
223{ 231{
224 unsigned int ctrl, mask; 232 unsigned int ctrl, mask;
225 233
226 get_controller(d->irq, &ctrl, &mask); 234 get_controller(d->hwirq, &ctrl, &mask);
227 235
228 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); 236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
229 237
230 /* Also need to clear pending wake event */ 238 /* Also need to clear pending wake event */
231 if (lpc32xx_events[d->irq].mask != 0) 239 if (lpc32xx_events[d->hwirq].mask != 0)
232 __raw_writel(lpc32xx_events[d->irq].mask, 240 __raw_writel(lpc32xx_events[d->hwirq].mask,
233 lpc32xx_events[d->irq].event_group->rawstat_reg); 241 lpc32xx_events[d->hwirq].event_group->rawstat_reg);
234} 242}
235 243
236static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, 244static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -274,22 +282,22 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
274 switch (type) { 282 switch (type) {
275 case IRQ_TYPE_EDGE_RISING: 283 case IRQ_TYPE_EDGE_RISING:
276 /* Rising edge sensitive */ 284 /* Rising edge sensitive */
277 __lpc32xx_set_irq_type(d->irq, 1, 1); 285 __lpc32xx_set_irq_type(d->hwirq, 1, 1);
278 break; 286 break;
279 287
280 case IRQ_TYPE_EDGE_FALLING: 288 case IRQ_TYPE_EDGE_FALLING:
281 /* Falling edge sensitive */ 289 /* Falling edge sensitive */
282 __lpc32xx_set_irq_type(d->irq, 0, 1); 290 __lpc32xx_set_irq_type(d->hwirq, 0, 1);
283 break; 291 break;
284 292
285 case IRQ_TYPE_LEVEL_LOW: 293 case IRQ_TYPE_LEVEL_LOW:
286 /* Low level sensitive */ 294 /* Low level sensitive */
287 __lpc32xx_set_irq_type(d->irq, 0, 0); 295 __lpc32xx_set_irq_type(d->hwirq, 0, 0);
288 break; 296 break;
289 297
290 case IRQ_TYPE_LEVEL_HIGH: 298 case IRQ_TYPE_LEVEL_HIGH:
291 /* High level sensitive */ 299 /* High level sensitive */
292 __lpc32xx_set_irq_type(d->irq, 1, 0); 300 __lpc32xx_set_irq_type(d->hwirq, 1, 0);
293 break; 301 break;
294 302
295 /* Other modes are not supported */ 303 /* Other modes are not supported */
@@ -298,7 +306,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
298 } 306 }
299 307
300 /* Ok to use the level handler for all types */ 308 /* Ok to use the level handler for all types */
301 irq_set_handler(d->irq, handle_level_irq); 309 irq_set_handler(d->hwirq, handle_level_irq);
302 310
303 return 0; 311 return 0;
304} 312}
@@ -307,33 +315,33 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
307{ 315{
308 unsigned long eventreg; 316 unsigned long eventreg;
309 317
310 if (lpc32xx_events[d->irq].mask != 0) { 318 if (lpc32xx_events[d->hwirq].mask != 0) {
311 eventreg = __raw_readl(lpc32xx_events[d->irq]. 319 eventreg = __raw_readl(lpc32xx_events[d->hwirq].
312 event_group->enab_reg); 320 event_group->enab_reg);
313 321
314 if (state) 322 if (state)
315 eventreg |= lpc32xx_events[d->irq].mask; 323 eventreg |= lpc32xx_events[d->hwirq].mask;
316 else { 324 else {
317 eventreg &= ~lpc32xx_events[d->irq].mask; 325 eventreg &= ~lpc32xx_events[d->hwirq].mask;
318 326
319 /* 327 /*
320 * When disabling the wakeup, clear the latched 328 * When disabling the wakeup, clear the latched
321 * event 329 * event
322 */ 330 */
323 __raw_writel(lpc32xx_events[d->irq].mask, 331 __raw_writel(lpc32xx_events[d->hwirq].mask,
324 lpc32xx_events[d->irq]. 332 lpc32xx_events[d->hwirq].
325 event_group->rawstat_reg); 333 event_group->rawstat_reg);
326 } 334 }
327 335
328 __raw_writel(eventreg, 336 __raw_writel(eventreg,
329 lpc32xx_events[d->irq].event_group->enab_reg); 337 lpc32xx_events[d->hwirq].event_group->enab_reg);
330 338
331 return 0; 339 return 0;
332 } 340 }
333 341
334 /* Clear event */ 342 /* Clear event */
335 __raw_writel(lpc32xx_events[d->irq].mask, 343 __raw_writel(lpc32xx_events[d->hwirq].mask,
336 lpc32xx_events[d->irq].event_group->rawstat_reg); 344 lpc32xx_events[d->hwirq].event_group->rawstat_reg);
337 345
338 return -ENODEV; 346 return -ENODEV;
339} 347}
@@ -353,6 +361,7 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
353} 361}
354 362
355static struct irq_chip lpc32xx_irq_chip = { 363static struct irq_chip lpc32xx_irq_chip = {
364 .name = "MIC",
356 .irq_ack = lpc32xx_ack_irq, 365 .irq_ack = lpc32xx_ack_irq,
357 .irq_mask = lpc32xx_mask_irq, 366 .irq_mask = lpc32xx_mask_irq,
358 .irq_unmask = lpc32xx_unmask_irq, 367 .irq_unmask = lpc32xx_unmask_irq,
@@ -386,9 +395,23 @@ static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
386 } 395 }
387} 396}
388 397
398static int __init __lpc32xx_mic_of_init(struct device_node *node,
399 struct device_node *parent)
400{
401 lpc32xx_mic_np = node;
402
403 return 0;
404}
405
406static const struct of_device_id mic_of_match[] __initconst = {
407 { .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init },
408 { }
409};
410
389void __init lpc32xx_init_irq(void) 411void __init lpc32xx_init_irq(void)
390{ 412{
391 unsigned int i; 413 unsigned int i;
414 int irq_base;
392 415
393 /* Setup MIC */ 416 /* Setup MIC */
394 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); 417 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -448,4 +471,19 @@ void __init lpc32xx_init_irq(void)
448 LPC32XX_CLKPWR_PIN_RS); 471 LPC32XX_CLKPWR_PIN_RS);
449 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), 472 __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
450 LPC32XX_CLKPWR_INT_RS); 473 LPC32XX_CLKPWR_INT_RS);
474
475 of_irq_init(mic_of_match);
476
477 irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
478 if (irq_base < 0) {
479 pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
480 irq_base = 0;
481 }
482
483 lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
484 irq_base, 0,
485 &irq_domain_simple_ops,
486 NULL);
487 if (!lpc32xx_mic_domain)
488 panic("Unable to add MIC irq domain\n");
451} 489}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7f7401ec7487..540106cdb9ec 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,8 +1,9 @@
1/* 1/*
2 * arch/arm/mach-lpc32xx/phy3250.c 2 * Platform support for LPC32xx SoC
3 * 3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com> 4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 * 5 *
6 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
6 * Copyright (C) 2010 NXP Semiconductors 7 * Copyright (C) 2010 NXP Semiconductors
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
@@ -25,11 +26,16 @@
25#include <linux/device.h> 26#include <linux/device.h>
26#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
27#include <linux/spi/eeprom.h> 28#include <linux/spi/eeprom.h>
28#include <linux/leds.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/of_platform.h>
37#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
33 39
34#include <asm/setup.h> 40#include <asm/setup.h>
35#include <asm/mach-types.h> 41#include <asm/mach-types.h>
@@ -47,7 +53,6 @@
47#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
48#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
49#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
50#define LED_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
51 56
52/* 57/*
53 * AMBA LCD controller 58 * AMBA LCD controller
@@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
150 .remove = lpc32xx_clcd_remove, 155 .remove = lpc32xx_clcd_remove,
151}; 156};
152 157
153static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
154 LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
155
156/* 158/*
157 * AMBA SSP (SPI) 159 * AMBA SSP (SPI)
158 */ 160 */
@@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
180 .enable_dma = 0, 182 .enable_dma = 0,
181}; 183};
182 184
183static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0, 185static struct pl022_ssp_controller lpc32xx_ssp1_data = {
184 LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data); 186 .bus_id = 1,
187 .num_chipselect = 1,
188 .enable_dma = 0,
189};
185 190
186/* AT25 driver registration */ 191/* AT25 driver registration */
187static int __init phy3250_spi_board_register(void) 192static int __init phy3250_spi_board_register(void)
@@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void)
221} 226}
222arch_initcall(phy3250_spi_board_register); 227arch_initcall(phy3250_spi_board_register);
223 228
224static struct i2c_board_info __initdata phy3250_i2c_board_info[] = { 229static struct pl08x_platform_data pl08x_pd = {
225 {
226 I2C_BOARD_INFO("pcf8563", 0x51),
227 },
228};
229
230static struct gpio_led phy_leds[] = {
231 {
232 .name = "led0",
233 .gpio = LED_GPIO,
234 .active_low = 1,
235 .default_trigger = "heartbeat",
236 },
237};
238
239static struct gpio_led_platform_data led_data = {
240 .leds = phy_leds,
241 .num_leds = ARRAY_SIZE(phy_leds),
242};
243
244static struct platform_device lpc32xx_gpio_led_device = {
245 .name = "leds-gpio",
246 .id = -1,
247 .dev.platform_data = &led_data,
248}; 230};
249 231
250static struct platform_device *phy3250_devs[] __initdata = { 232static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
251 &lpc32xx_rtc_device, 233 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
252 &lpc32xx_tsc_device, 234 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
253 &lpc32xx_i2c0_device, 235 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
254 &lpc32xx_i2c1_device, 236 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
255 &lpc32xx_i2c2_device, 237 { }
256 &lpc32xx_watchdog_device,
257 &lpc32xx_gpio_led_device,
258 &lpc32xx_adc_device,
259 &lpc32xx_ohci_device,
260 &lpc32xx_net_device,
261}; 238};
262 239
263static struct amba_device *amba_devs[] __initdata = { 240static void __init lpc3250_machine_init(void)
264 &lpc32xx_clcd_device,
265 &lpc32xx_ssp0_device,
266};
267
268/*
269 * Board specific functions
270 */
271static void __init phy3250_board_init(void)
272{ 241{
273 u32 tmp; 242 u32 tmp;
274 int i;
275
276 lpc32xx_gpio_init();
277
278 /* Register GPIOs used on this board */
279 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
280 printk(KERN_ERR "Error requesting gpio %u",
281 SPI0_CS_GPIO);
282 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
283 printk(KERN_ERR "Error setting gpio %u to output",
284 SPI0_CS_GPIO);
285
286 /* Setup network interface for RMII mode */
287 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
288 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
289 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
290 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
291 243
292 /* Setup SLC NAND controller muxing */ 244 /* Setup SLC NAND controller muxing */
293 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, 245 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
@@ -300,6 +252,12 @@ static void __init phy3250_board_init(void)
300 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; 252 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
301 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); 253 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
302 254
255 /* Set up USB power */
256 tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
257 tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
258 LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
259 __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
260
303 /* Set up I2C pull levels */ 261 /* Set up I2C pull levels */
304 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); 262 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
305 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | 263 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
@@ -321,54 +279,51 @@ static void __init phy3250_board_init(void)
321 /* 279 /*
322 * AMBA peripheral clocks need to be enabled prior to AMBA device 280 * AMBA peripheral clocks need to be enabled prior to AMBA device
323 * detection or a data fault will occur, so enable the clocks 281 * detection or a data fault will occur, so enable the clocks
324 * here. However, we don't want to enable them if the peripheral 282 * here.
325 * isn't included in the image
326 */ 283 */
327#ifdef CONFIG_FB_ARMCLCD
328 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); 284 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
329 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), 285 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
330 LPC32XX_CLKPWR_LCDCLK_CTRL); 286 LPC32XX_CLKPWR_LCDCLK_CTRL);
331#endif 287
332#ifdef CONFIG_SPI_PL022
333 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); 288 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
334 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), 289 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
335 LPC32XX_CLKPWR_SSP_CLK_CTRL); 290 LPC32XX_CLKPWR_SSP_CLK_CTRL);
336#endif
337 291
338 platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs)); 292 tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
339 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 293 __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
340 struct amba_device *d = amba_devs[i]; 294 LPC32XX_CLKPWR_DMA_CLK_CTRL);
341 amba_device_register(d, &iomem_resource);
342 }
343 295
344 /* Test clock needed for UDA1380 initial init */ 296 /* Test clock needed for UDA1380 initial init */
345 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 297 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
346 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, 298 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
347 LPC32XX_CLKPWR_TEST_CLK_SEL); 299 LPC32XX_CLKPWR_TEST_CLK_SEL);
348 300
349 i2c_register_board_info(0, phy3250_i2c_board_info, 301 of_platform_populate(NULL, of_default_bus_match_table,
350 ARRAY_SIZE(phy3250_i2c_board_info)); 302 lpc32xx_auxdata_lookup, NULL);
351}
352
353static int __init lpc32xx_display_uid(void)
354{
355 u32 uid[4];
356
357 lpc32xx_get_uid(uid);
358
359 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
360 uid[3], uid[2], uid[1], uid[0]);
361 303
362 return 1; 304 /* Register GPIOs used on this board */
305 if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
306 printk(KERN_ERR "Error requesting gpio %u",
307 SPI0_CS_GPIO);
308 else if (gpio_direction_output(SPI0_CS_GPIO, 1))
309 printk(KERN_ERR "Error setting gpio %u to output",
310 SPI0_CS_GPIO);
363} 311}
364arch_initcall(lpc32xx_display_uid);
365 312
366MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") 313static char const *lpc32xx_dt_compat[] __initdata = {
367 /* Maintainer: Kevin Wells, NXP Semiconductors */ 314 "nxp,lpc3220",
315 "nxp,lpc3230",
316 "nxp,lpc3240",
317 "nxp,lpc3250",
318 NULL
319};
320
321DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
368 .atag_offset = 0x100, 322 .atag_offset = 0x100,
369 .map_io = lpc32xx_map_io, 323 .map_io = lpc32xx_map_io,
370 .init_irq = lpc32xx_init_irq, 324 .init_irq = lpc32xx_init_irq,
371 .timer = &lpc32xx_timer, 325 .timer = &lpc32xx_timer,
372 .init_machine = phy3250_board_init, 326 .init_machine = lpc3250_machine_init,
327 .dt_compat = lpc32xx_dt_compat,
373 .restart = lpc23xx_restart, 328 .restart = lpc23xx_restart,
374MACHINE_END 329MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 12:13:26 -0500