diff options
Diffstat (limited to 'arch/arm/mach-lpc32xx/serial.c')
-rw-r--r-- | arch/arm/mach-lpc32xx/serial.c | 90 |
1 files changed, 6 insertions, 84 deletions
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index f2735281616a..05621a29fba2 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c | |||
@@ -31,59 +31,6 @@ | |||
31 | 31 | ||
32 | #define LPC32XX_SUART_FIFO_SIZE 64 | 32 | #define LPC32XX_SUART_FIFO_SIZE 64 |
33 | 33 | ||
34 | /* Standard 8250/16550 compatible serial ports */ | ||
35 | static struct plat_serial8250_port serial_std_platform_data[] = { | ||
36 | #ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT | ||
37 | { | ||
38 | .membase = io_p2v(LPC32XX_UART5_BASE), | ||
39 | .mapbase = LPC32XX_UART5_BASE, | ||
40 | .irq = IRQ_LPC32XX_UART_IIR5, | ||
41 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
42 | .regshift = 2, | ||
43 | .iotype = UPIO_MEM32, | ||
44 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
45 | UPF_SKIP_TEST, | ||
46 | }, | ||
47 | #endif | ||
48 | #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT | ||
49 | { | ||
50 | .membase = io_p2v(LPC32XX_UART3_BASE), | ||
51 | .mapbase = LPC32XX_UART3_BASE, | ||
52 | .irq = IRQ_LPC32XX_UART_IIR3, | ||
53 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
54 | .regshift = 2, | ||
55 | .iotype = UPIO_MEM32, | ||
56 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
57 | UPF_SKIP_TEST, | ||
58 | }, | ||
59 | #endif | ||
60 | #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT | ||
61 | { | ||
62 | .membase = io_p2v(LPC32XX_UART4_BASE), | ||
63 | .mapbase = LPC32XX_UART4_BASE, | ||
64 | .irq = IRQ_LPC32XX_UART_IIR4, | ||
65 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
66 | .regshift = 2, | ||
67 | .iotype = UPIO_MEM32, | ||
68 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
69 | UPF_SKIP_TEST, | ||
70 | }, | ||
71 | #endif | ||
72 | #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT | ||
73 | { | ||
74 | .membase = io_p2v(LPC32XX_UART6_BASE), | ||
75 | .mapbase = LPC32XX_UART6_BASE, | ||
76 | .irq = IRQ_LPC32XX_UART_IIR6, | ||
77 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
78 | .regshift = 2, | ||
79 | .iotype = UPIO_MEM32, | ||
80 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
81 | UPF_SKIP_TEST, | ||
82 | }, | ||
83 | #endif | ||
84 | { }, | ||
85 | }; | ||
86 | |||
87 | struct uartinit { | 34 | struct uartinit { |
88 | char *uart_ck_name; | 35 | char *uart_ck_name; |
89 | u32 ck_mode_mask; | 36 | u32 ck_mode_mask; |
@@ -92,7 +39,6 @@ struct uartinit { | |||
92 | }; | 39 | }; |
93 | 40 | ||
94 | static struct uartinit uartinit_data[] __initdata = { | 41 | static struct uartinit uartinit_data[] __initdata = { |
95 | #ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT | ||
96 | { | 42 | { |
97 | .uart_ck_name = "uart5_ck", | 43 | .uart_ck_name = "uart5_ck", |
98 | .ck_mode_mask = | 44 | .ck_mode_mask = |
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
100 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, | 46 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, |
101 | .mapbase = LPC32XX_UART5_BASE, | 47 | .mapbase = LPC32XX_UART5_BASE, |
102 | }, | 48 | }, |
103 | #endif | ||
104 | #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT | ||
105 | { | 49 | { |
106 | .uart_ck_name = "uart3_ck", | 50 | .uart_ck_name = "uart3_ck", |
107 | .ck_mode_mask = | 51 | .ck_mode_mask = |
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
109 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, | 53 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, |
110 | .mapbase = LPC32XX_UART3_BASE, | 54 | .mapbase = LPC32XX_UART3_BASE, |
111 | }, | 55 | }, |
112 | #endif | ||
113 | #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT | ||
114 | { | 56 | { |
115 | .uart_ck_name = "uart4_ck", | 57 | .uart_ck_name = "uart4_ck", |
116 | .ck_mode_mask = | 58 | .ck_mode_mask = |
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
118 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, | 60 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, |
119 | .mapbase = LPC32XX_UART4_BASE, | 61 | .mapbase = LPC32XX_UART4_BASE, |
120 | }, | 62 | }, |
121 | #endif | ||
122 | #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT | ||
123 | { | 63 | { |
124 | .uart_ck_name = "uart6_ck", | 64 | .uart_ck_name = "uart6_ck", |
125 | .ck_mode_mask = | 65 | .ck_mode_mask = |
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
127 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, | 67 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, |
128 | .mapbase = LPC32XX_UART6_BASE, | 68 | .mapbase = LPC32XX_UART6_BASE, |
129 | }, | 69 | }, |
130 | #endif | ||
131 | }; | ||
132 | |||
133 | static struct platform_device serial_std_platform_device = { | ||
134 | .name = "serial8250", | ||
135 | .id = 0, | ||
136 | .dev = { | ||
137 | .platform_data = serial_std_platform_data, | ||
138 | }, | ||
139 | }; | ||
140 | |||
141 | static struct platform_device *lpc32xx_serial_devs[] __initdata = { | ||
142 | &serial_std_platform_device, | ||
143 | }; | 70 | }; |
144 | 71 | ||
145 | void __init lpc32xx_serial_init(void) | 72 | void __init lpc32xx_serial_init(void) |
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void) | |||
156 | clk = clk_get(NULL, uartinit_data[i].uart_ck_name); | 83 | clk = clk_get(NULL, uartinit_data[i].uart_ck_name); |
157 | if (!IS_ERR(clk)) { | 84 | if (!IS_ERR(clk)) { |
158 | clk_enable(clk); | 85 | clk_enable(clk); |
159 | serial_std_platform_data[i].uartclk = | ||
160 | clk_get_rate(clk); | ||
161 | } | 86 | } |
162 | 87 | ||
163 | /* Fall back on main osc rate if clock rate return fails */ | ||
164 | if (serial_std_platform_data[i].uartclk == 0) | ||
165 | serial_std_platform_data[i].uartclk = | ||
166 | LPC32XX_MAIN_OSC_FREQ; | ||
167 | |||
168 | /* Setup UART clock modes for all UARTs, disable autoclock */ | 88 | /* Setup UART clock modes for all UARTs, disable autoclock */ |
169 | clkmodes |= uartinit_data[i].ck_mode_mask; | 89 | clkmodes |= uartinit_data[i].ck_mode_mask; |
170 | 90 | ||
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void) | |||
189 | __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); | 109 | __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); |
190 | for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { | 110 | for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { |
191 | /* Force a flush of the RX FIFOs to work around a HW bug */ | 111 | /* Force a flush of the RX FIFOs to work around a HW bug */ |
192 | puart = serial_std_platform_data[i].mapbase; | 112 | puart = uartinit_data[i].mapbase; |
193 | __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); | 113 | __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); |
194 | __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); | 114 | __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); |
195 | j = LPC32XX_SUART_FIFO_SIZE; | 115 | j = LPC32XX_SUART_FIFO_SIZE; |
@@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void) | |||
198 | __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); | 118 | __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); |
199 | } | 119 | } |
200 | 120 | ||
121 | /* Disable IrDA pulsing support on UART6 */ | ||
122 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); | ||
123 | tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; | ||
124 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); | ||
125 | |||
201 | /* Disable UART5->USB transparent mode or USB won't work */ | 126 | /* Disable UART5->USB transparent mode or USB won't work */ |
202 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); | 127 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); |
203 | tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; | 128 | tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; |
204 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); | 129 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); |
205 | |||
206 | platform_add_devices(lpc32xx_serial_devs, | ||
207 | ARRAY_SIZE(lpc32xx_serial_devs)); | ||
208 | } | 130 | } |