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-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c163
1 files changed, 57 insertions, 106 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 540106cdb9ec..b07dcc90829d 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/amba/pl08x.h>
34#include <linux/amba/mmci.h>
33#include <linux/of.h> 35#include <linux/of.h>
34#include <linux/of_address.h> 36#include <linux/of_address.h>
35#include <linux/of_irq.h> 37#include <linux/of_irq.h>
36#include <linux/of_platform.h> 38#include <linux/of_platform.h>
37#include <linux/clk.h> 39#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
39 40
40#include <asm/setup.h> 41#include <asm/setup.h>
41#include <asm/mach-types.h> 42#include <asm/mach-types.h>
@@ -50,9 +51,9 @@
50/* 51/*
51 * Mapped GPIOLIB GPIOs 52 * Mapped GPIOLIB GPIOs
52 */ 53 */
53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 56#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
56 57
57/* 58/*
58 * AMBA LCD controller 59 * AMBA LCD controller
@@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = {
158/* 159/*
159 * AMBA SSP (SPI) 160 * AMBA SSP (SPI)
160 */ 161 */
161static void phy3250_spi_cs_set(u32 control)
162{
163 gpio_set_value(SPI0_CS_GPIO, (int) control);
164}
165
166static struct pl022_config_chip spi0_chip_info = {
167 .com_mode = INTERRUPT_TRANSFER,
168 .iface = SSP_INTERFACE_MOTOROLA_SPI,
169 .hierarchy = SSP_MASTER,
170 .slave_tx_disable = 0,
171 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
172 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
173 .ctrl_len = SSP_BITS_8,
174 .wait_state = SSP_MWIRE_WAIT_ZERO,
175 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
176 .cs_control = phy3250_spi_cs_set,
177};
178
179static struct pl022_ssp_controller lpc32xx_ssp0_data = { 162static struct pl022_ssp_controller lpc32xx_ssp0_data = {
180 .bus_id = 0, 163 .bus_id = 0,
181 .num_chipselect = 1, 164 .num_chipselect = 1,
@@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
188 .enable_dma = 0, 171 .enable_dma = 0,
189}; 172};
190 173
191/* AT25 driver registration */ 174static struct pl08x_channel_data pl08x_slave_channels[] = {
192static int __init phy3250_spi_board_register(void) 175 {
176 .bus_id = "nand-slc",
177 .min_signal = 1, /* SLC NAND Flash */
178 .max_signal = 1,
179 .periph_buses = PL08X_AHB1,
180 },
181 {
182 .bus_id = "nand-mlc",
183 .min_signal = 12, /* MLC NAND Flash */
184 .max_signal = 12,
185 .periph_buses = PL08X_AHB1,
186 },
187};
188
189static int pl08x_get_signal(const struct pl08x_channel_data *cd)
190{
191 return cd->min_signal;
192}
193
194static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
193{ 195{
194#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
195 static struct spi_board_info info[] = {
196 {
197 .modalias = "spidev",
198 .max_speed_hz = 5000000,
199 .bus_num = 0,
200 .chip_select = 0,
201 .controller_data = &spi0_chip_info,
202 },
203 };
204
205#else
206 static struct spi_eeprom eeprom = {
207 .name = "at25256a",
208 .byte_len = 0x8000,
209 .page_size = 64,
210 .flags = EE_ADDR2,
211 };
212
213 static struct spi_board_info info[] = {
214 {
215 .modalias = "at25",
216 .max_speed_hz = 5000000,
217 .bus_num = 0,
218 .chip_select = 0,
219 .mode = SPI_MODE_0,
220 .platform_data = &eeprom,
221 .controller_data = &spi0_chip_info,
222 },
223 };
224#endif
225 return spi_register_board_info(info, ARRAY_SIZE(info));
226} 196}
227arch_initcall(phy3250_spi_board_register);
228 197
229static struct pl08x_platform_data pl08x_pd = { 198static struct pl08x_platform_data pl08x_pd = {
199 .slave_channels = &pl08x_slave_channels[0],
200 .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
201 .get_signal = pl08x_get_signal,
202 .put_signal = pl08x_put_signal,
203 .lli_buses = PL08X_AHB1,
204 .mem_buses = PL08X_AHB1,
205};
206
207static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
208{
209 /* Only on and off are supported */
210 if (ios->power_mode == MMC_POWER_OFF)
211 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
212 else
213 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
214 return 0;
215}
216
217static struct mmci_platform_data lpc32xx_mmci_data = {
218 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
219 MMC_VDD_32_33 | MMC_VDD_33_34,
220 .ios_handler = mmc_handle_ios,
221 .dma_filter = NULL,
222 /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
223 * gather, and the MMCI driver doesn't do it this way */
230}; 224};
231 225
232static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { 226static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
@@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
234 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), 228 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
235 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), 229 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
236 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), 230 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
231 OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
232 &lpc32xx_mmci_data),
237 { } 233 { }
238}; 234};
239 235
@@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void)
241{ 237{
242 u32 tmp; 238 u32 tmp;
243 239
244 /* Setup SLC NAND controller muxing */
245 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
246 LPC32XX_CLKPWR_NAND_CLK_CTRL);
247
248 /* Setup LCD muxing to RGB565 */ 240 /* Setup LCD muxing to RGB565 */
249 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & 241 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
250 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | 242 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
@@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void)
252 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; 244 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
253 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); 245 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
254 246
255 /* Set up USB power */
256 tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
257 tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
258 LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
259 __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
260
261 /* Set up I2C pull levels */
262 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
263 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
264 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
265 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
266
267 /* Disable IrDA pulsing support on UART6 */
268 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
269 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
270 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
271
272 /* Enable DMA for I2S1 channel */
273 tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
274 tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
275 __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
276
277 lpc32xx_serial_init(); 247 lpc32xx_serial_init();
278 248
279 /*
280 * AMBA peripheral clocks need to be enabled prior to AMBA device
281 * detection or a data fault will occur, so enable the clocks
282 * here.
283 */
284 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
285 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
286 LPC32XX_CLKPWR_LCDCLK_CTRL);
287
288 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
289 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
290 LPC32XX_CLKPWR_SSP_CLK_CTRL);
291
292 tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
293 __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
294 LPC32XX_CLKPWR_DMA_CLK_CTRL);
295
296 /* Test clock needed for UDA1380 initial init */ 249 /* Test clock needed for UDA1380 initial init */
297 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 250 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
298 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, 251 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
@@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void)
302 lpc32xx_auxdata_lookup, NULL); 255 lpc32xx_auxdata_lookup, NULL);
303 256
304 /* Register GPIOs used on this board */ 257 /* Register GPIOs used on this board */
305 if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) 258 if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
306 printk(KERN_ERR "Error requesting gpio %u", 259 pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
307 SPI0_CS_GPIO); 260 else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
308 else if (gpio_direction_output(SPI0_CS_GPIO, 1)) 261 pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
309 printk(KERN_ERR "Error setting gpio %u to output",
310 SPI0_CS_GPIO);
311} 262}
312 263
313static char const *lpc32xx_dt_compat[] __initdata = { 264static char const *lpc32xx_dt_compat[] __initdata = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 05:13:01 -0400