diff options
Diffstat (limited to 'arch/arm/mach-lh7a40x/Kconfig')
-rw-r--r-- | arch/arm/mach-lh7a40x/Kconfig | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig index 6f4c6a1798c1..9be7466e346c 100644 --- a/arch/arm/mach-lh7a40x/Kconfig +++ b/arch/arm/mach-lh7a40x/Kconfig | |||
@@ -40,23 +40,22 @@ config LPD7A40X_CPLD_SSP | |||
40 | bool | 40 | bool |
41 | 41 | ||
42 | config LH7A40X_CONTIGMEM | 42 | config LH7A40X_CONTIGMEM |
43 | bool "Disable NUMA Support" | 43 | bool "Disable NUMA/SparseMEM Support" |
44 | depends on ARCH_LH7A40X | ||
45 | help | 44 | help |
46 | Say Y here if your bootloader sets the SROMLL bit(s) in | 45 | Say Y here if your bootloader sets the SROMLL bit(s) in |
47 | the SDRAM controller, organizing memory as a contiguous | 46 | the SDRAM controller, organizing memory as a contiguous |
48 | array. This option will disable CONFIG_DISCONTIGMEM and | 47 | array. This option will disable sparse memory support |
49 | force the kernel to manage all memory in one node. | 48 | and force the kernel to manage all memory in one node. |
50 | 49 | ||
51 | Setting this option incorrectly may prevent the kernel from | 50 | Setting this option incorrectly may prevent the kernel |
52 | booting. It is OK to leave it N. | 51 | from booting. It is OK to leave it N. |
53 | 52 | ||
54 | For more information, consult | 53 | For more information, consult |
55 | <file:Documentation/arm/Sharp-LH/SDRAM>. | 54 | <file:Documentation/arm/Sharp-LH/SDRAM>. |
56 | 55 | ||
57 | config LH7A40X_ONE_BANK_PER_NODE | 56 | config LH7A40X_ONE_BANK_PER_NODE |
58 | bool "Optimize NUMA Node Tables for Size" | 57 | bool "Optimize NUMA Node Tables for Size" |
59 | depends on ARCH_LH7A40X && !LH7A40X_CONTIGMEM | 58 | depends on !LH7A40X_CONTIGMEM |
60 | help | 59 | help |
61 | Say Y here to produce compact memory node tables. By | 60 | Say Y here to produce compact memory node tables. By |
62 | default pairs of adjacent physical RAM banks are managed | 61 | default pairs of adjacent physical RAM banks are managed |