diff options
Diffstat (limited to 'arch/arm/mach-l7200/include/mach/sib.h')
-rw-r--r-- | arch/arm/mach-l7200/include/mach/sib.h | 119 |
1 files changed, 0 insertions, 119 deletions
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h deleted file mode 100644 index 965728712cf3..000000000000 --- a/arch/arm/mach-l7200/include/mach/sib.h +++ /dev/null | |||
@@ -1,119 +0,0 @@ | |||
1 | /****************************************************************************/ | ||
2 | /* | ||
3 | * arch/arm/mach-l7200/include/mach/sib.h | ||
4 | * | ||
5 | * Registers and helper functions for the Serial Interface Bus. | ||
6 | * | ||
7 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file COPYING in the main directory of this archive for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | /****************************************************************************/ | ||
15 | |||
16 | #define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */ | ||
17 | |||
18 | /* IO_START and IO_BASE are defined in hardware.h */ | ||
19 | |||
20 | #define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */ | ||
21 | #define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */ | ||
22 | |||
23 | /* Offsets from the start of the SIB for all the registers. */ | ||
24 | |||
25 | /* Define the SIB registers for use by device drivers and the kernel. */ | ||
26 | |||
27 | typedef struct | ||
28 | { | ||
29 | unsigned int MCCR; /* SIB Control Register Offset: 0x00 */ | ||
30 | unsigned int RES1; /* Reserved Offset: 0x04 */ | ||
31 | unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */ | ||
32 | unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */ | ||
33 | unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */ | ||
34 | unsigned int RES2; /* Reserved Offset: 0x14 */ | ||
35 | unsigned int MCSR; /* SIB Status Register Offset: 0x18 */ | ||
36 | } SIB_Interface; | ||
37 | |||
38 | #define SIB ((volatile SIB_Interface *) (SIB_BASE)) | ||
39 | |||
40 | /* MCCR */ | ||
41 | |||
42 | #define INTERNAL_FREQ 9216000 /* Hertz */ | ||
43 | #define AUDIO_FREQ 5000 /* Hertz */ | ||
44 | #define TELECOM_FREQ 5000 /* Hertz */ | ||
45 | |||
46 | #define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ)) | ||
47 | #define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ)) | ||
48 | |||
49 | #define MCCR_ASD57 AUDIO_DIVIDE | ||
50 | #define MCCR_TSD57 (TELECOM_DIVIDE << 8) | ||
51 | #define MCCR_MCE (1 << 16) /* SIB enable */ | ||
52 | #define MCCR_ECS (1 << 17) /* External Clock Select */ | ||
53 | #define MCCR_ADM (1 << 18) /* A/D Data Sampling */ | ||
54 | #define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */ | ||
55 | |||
56 | |||
57 | #define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */ | ||
58 | #define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */ | ||
59 | #define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */ | ||
60 | #define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */ | ||
61 | #define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */ | ||
62 | #define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ | ||
63 | #define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */ | ||
64 | #define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ | ||
65 | #define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */ | ||
66 | #define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */ | ||
67 | #define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */ | ||
68 | #define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */ | ||
69 | #define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */ | ||
70 | #define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */ | ||
71 | |||
72 | /* MCDR0 */ | ||
73 | |||
74 | #define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff) | ||
75 | #define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4)) | ||
76 | |||
77 | /* MCDR1 */ | ||
78 | |||
79 | #define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff) | ||
80 | #define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2)) | ||
81 | |||
82 | |||
83 | /* MCSR */ | ||
84 | |||
85 | #define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */ | ||
86 | #define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */ | ||
87 | #define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */ | ||
88 | #define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */ | ||
89 | |||
90 | #define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO) | ||
91 | |||
92 | |||
93 | #define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/ | ||
94 | #define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/ | ||
95 | #define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */ | ||
96 | #define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */ | ||
97 | #define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */ | ||
98 | #define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */ | ||
99 | #define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */ | ||
100 | #define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */ | ||
101 | #define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */ | ||
102 | #define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */ | ||
103 | #define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */ | ||
104 | #define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */ | ||
105 | #define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */ | ||
106 | #define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */ | ||
107 | #define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */ | ||
108 | #define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */ | ||
109 | |||
110 | /* MCDR2 */ | ||
111 | |||
112 | #define MCDR2_rW (1 << 16) | ||
113 | |||
114 | #define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff))) | ||
115 | #define MCDR2_WRITE_COMPLETE GET_CWC | ||
116 | |||
117 | #define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17)) | ||
118 | #define MCDR2_READ_COMPLETE GET_CRC | ||
119 | #define MCDR2_READ (SIB->MCDR2 & 0xffff) | ||