diff options
Diffstat (limited to 'arch/arm/mach-kirkwood')
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 20 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/kirkwood.h | 110 |
2 files changed, 65 insertions, 65 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index a115142f8690..5c82b7dce4e2 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |||
| @@ -13,37 +13,37 @@ | |||
| 13 | 13 | ||
| 14 | #include <mach/kirkwood.h> | 14 | #include <mach/kirkwood.h> |
| 15 | 15 | ||
| 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) | 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) |
| 17 | #define CPU_CONFIG_ERROR_PROP 0x00000004 | 17 | #define CPU_CONFIG_ERROR_PROP 0x00000004 |
| 18 | 18 | ||
| 19 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | 19 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
| 20 | #define CPU_RESET 0x00000002 | 20 | #define CPU_RESET 0x00000002 |
| 21 | 21 | ||
| 22 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | 22 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
| 23 | #define WDT_RESET_OUT_EN 0x00000002 | 23 | #define WDT_RESET_OUT_EN 0x00000002 |
| 24 | #define SOFT_RESET_OUT_EN 0x00000004 | 24 | #define SOFT_RESET_OUT_EN 0x00000004 |
| 25 | 25 | ||
| 26 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | 26 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
| 27 | #define SOFT_RESET 0x00000001 | 27 | #define SOFT_RESET 0x00000001 |
| 28 | 28 | ||
| 29 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | 29 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) |
| 30 | #define WDT_INT_REQ 0x0008 | 30 | #define WDT_INT_REQ 0x0008 |
| 31 | 31 | ||
| 32 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | 32 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
| 33 | 33 | ||
| 34 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | 34 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
| 35 | #define IRQ_CAUSE_LOW_OFF 0x0000 | 35 | #define IRQ_CAUSE_LOW_OFF 0x0000 |
| 36 | #define IRQ_MASK_LOW_OFF 0x0004 | 36 | #define IRQ_MASK_LOW_OFF 0x0004 |
| 37 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | 37 | #define IRQ_CAUSE_HIGH_OFF 0x0010 |
| 38 | #define IRQ_MASK_HIGH_OFF 0x0014 | 38 | #define IRQ_MASK_HIGH_OFF 0x0014 |
| 39 | 39 | ||
| 40 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 40 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
| 41 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) | 41 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
| 42 | 42 | ||
| 43 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) | 43 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) |
| 44 | #define L2_WRITETHROUGH 0x00000010 | 44 | #define L2_WRITETHROUGH 0x00000010 |
| 45 | 45 | ||
| 46 | #define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) | 46 | #define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) |
| 47 | #define CGC_BIT_GE0 (0) | 47 | #define CGC_BIT_GE0 (0) |
| 48 | #define CGC_BIT_PEX0 (2) | 48 | #define CGC_BIT_PEX0 (2) |
| 49 | #define CGC_BIT_USB0 (3) | 49 | #define CGC_BIT_USB0 (3) |
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776b..9695592d332b 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h | |||
| @@ -61,61 +61,61 @@ | |||
| 61 | /* | 61 | /* |
| 62 | * Register Map | 62 | * Register Map |
| 63 | */ | 63 | */ |
| 64 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) | 64 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) |
| 65 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) | 65 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) |
| 66 | #define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) | 66 | #define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418) |
| 67 | 67 | ||
| 68 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) | 68 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) |
| 69 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) | 69 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) |
| 70 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) | 70 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030) |
| 71 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | 71 | #define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034) |
| 72 | #define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) | 72 | #define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) |
| 73 | #define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140) | 73 | #define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140) |
| 74 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | 74 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300) |
| 75 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | 75 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600) |
| 76 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | 76 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) |
| 77 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 77 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) |
| 78 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 78 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) |
| 79 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 79 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) |
| 80 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | 80 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) |
| 81 | 81 | ||
| 82 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) | 82 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) |
| 83 | #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000) | 83 | #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) |
| 84 | 84 | ||
| 85 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) | 85 | #define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) |
| 86 | 86 | ||
| 87 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) | 87 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000) |
| 88 | #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) | 88 | #define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70) |
| 89 | #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) | 89 | #define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04) |
| 90 | #define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) | 90 | #define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000) |
| 91 | #define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) | 91 | #define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70) |
| 92 | #define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) | 92 | #define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04) |
| 93 | 93 | ||
| 94 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) | 94 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000) |
| 95 | 95 | ||
| 96 | #define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) | 96 | #define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800) |
| 97 | #define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) | 97 | #define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800) |
| 98 | #define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) | 98 | #define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900) |
| 99 | #define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) | 99 | #define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900) |
| 100 | #define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) | 100 | #define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00) |
| 101 | #define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) | 101 | #define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00) |
| 102 | #define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) | 102 | #define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00) |
| 103 | #define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) | 103 | #define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00) |
| 104 | 104 | ||
| 105 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) | 105 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000) |
| 106 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) | 106 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000) |
| 107 | 107 | ||
| 108 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | 108 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000) |
| 109 | #define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) | 109 | #define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000) |
| 110 | #define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) | 110 | #define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050) |
| 111 | #define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) | 111 | #define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330) |
| 112 | #define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) | 112 | #define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050) |
| 113 | #define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) | 113 | #define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330) |
| 114 | 114 | ||
| 115 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) | 115 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000) |
| 116 | 116 | ||
| 117 | #define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) | 117 | #define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000) |
| 118 | #define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) | 118 | #define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000) |
| 119 | 119 | ||
| 120 | /* | 120 | /* |
| 121 | * Supported devices and revisions. | 121 | * Supported devices and revisions. |