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-rw-r--r--arch/arm/mach-kirkwood/pcie.c44
1 files changed, 13 insertions, 31 deletions
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2efa3c35..532d8acb38f9 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -56,7 +56,7 @@ struct pcie_port {
56 void __iomem *base; 56 void __iomem *base;
57 spinlock_t conf_lock; 57 spinlock_t conf_lock;
58 int irq; 58 int irq;
59 struct resource res[2]; 59 struct resource res;
60}; 60};
61 61
62static int pcie_port_map[2]; 62static int pcie_port_map[2];
@@ -137,20 +137,12 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
137 pp->irq = IRQ_KIRKWOOD_PCIE; 137 pp->irq = IRQ_KIRKWOOD_PCIE;
138 138
139 /* 139 /*
140 * IORESOURCE_IO
141 */
142 pp->res[0].name = "PCIe 0 I/O Space";
143 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
144 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
145 pp->res[0].flags = IORESOURCE_IO;
146
147 /*
148 * IORESOURCE_MEM 140 * IORESOURCE_MEM
149 */ 141 */
150 pp->res[1].name = "PCIe 0 MEM"; 142 pp->res.name = "PCIe 0 MEM";
151 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; 143 pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
152 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 144 pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
153 pp->res[1].flags = IORESOURCE_MEM; 145 pp->res.flags = IORESOURCE_MEM;
154} 146}
155 147
156static void __init pcie1_ioresources_init(struct pcie_port *pp) 148static void __init pcie1_ioresources_init(struct pcie_port *pp)
@@ -159,20 +151,12 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
159 pp->irq = IRQ_KIRKWOOD_PCIE1; 151 pp->irq = IRQ_KIRKWOOD_PCIE1;
160 152
161 /* 153 /*
162 * IORESOURCE_IO
163 */
164 pp->res[0].name = "PCIe 1 I/O Space";
165 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
166 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
167 pp->res[0].flags = IORESOURCE_IO;
168
169 /*
170 * IORESOURCE_MEM 154 * IORESOURCE_MEM
171 */ 155 */
172 pp->res[1].name = "PCIe 1 MEM"; 156 pp->res.name = "PCIe 1 MEM";
173 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; 157 pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
174 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; 158 pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
175 pp->res[1].flags = IORESOURCE_MEM; 159 pp->res.flags = IORESOURCE_MEM;
176} 160}
177 161
178static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) 162static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
197 case 0: 181 case 0:
198 kirkwood_enable_pcie_clk("0"); 182 kirkwood_enable_pcie_clk("0");
199 pcie0_ioresources_init(pp); 183 pcie0_ioresources_init(pp);
184 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
200 break; 185 break;
201 case 1: 186 case 1:
202 kirkwood_enable_pcie_clk("1"); 187 kirkwood_enable_pcie_clk("1");
203 pcie1_ioresources_init(pp); 188 pcie1_ioresources_init(pp);
189 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
204 break; 190 break;
205 default: 191 default:
206 panic("PCIe setup: invalid controller %d", index); 192 panic("PCIe setup: invalid controller %d", index);
207 } 193 }
208 194
209 if (request_resource(&ioport_resource, &pp->res[0])) 195 if (request_resource(&iomem_resource, &pp->res))
210 panic("Request PCIe%d IO resource failed\n", index);
211 if (request_resource(&iomem_resource, &pp->res[1]))
212 panic("Request PCIe%d Memory resource failed\n", index); 196 panic("Request PCIe%d Memory resource failed\n", index);
213 197
214 sys->io_offset = 0; 198 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
215 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
216 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
217 199
218 /* 200 /*
219 * Generic PCIe unit setup. 201 * Generic PCIe unit setup.