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Diffstat (limited to 'arch/arm/mach-kirkwood/include/mach/bridge-regs.h')
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 4f7029f521cc..9e80d9232c83 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,12 +17,15 @@
17#define CPU_RESET 0x00000002 17#define CPU_RESET 0x00000002
18 18
19#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 19#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
20#define WDT_RESET_OUT_EN 0x00000002
20#define SOFT_RESET_OUT_EN 0x00000004 21#define SOFT_RESET_OUT_EN 0x00000004
21 22
22#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 23#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
23#define SOFT_RESET 0x00000001 24#define SOFT_RESET 0x00000001
24 25
25#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) 26#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
27#define WDT_INT_REQ 0x0008
28
26#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) 29#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
27#define BRIDGE_INT_TIMER0 0x0002 30#define BRIDGE_INT_TIMER0 0x0002
28#define BRIDGE_INT_TIMER1 0x0004 31#define BRIDGE_INT_TIMER1 0x0004
@@ -39,4 +42,22 @@
39#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) 42#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
40#define L2_WRITETHROUGH 0x00000010 43#define L2_WRITETHROUGH 0x00000010
41 44
45#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
46#define CGC_GE0 (1 << 0)
47#define CGC_PEX0 (1 << 2)
48#define CGC_USB0 (1 << 3)
49#define CGC_SDIO (1 << 4)
50#define CGC_TSU (1 << 5)
51#define CGC_DUNIT (1 << 6)
52#define CGC_RUNIT (1 << 7)
53#define CGC_XOR0 (1 << 8)
54#define CGC_AUDIO (1 << 9)
55#define CGC_SATA0 (1 << 14)
56#define CGC_SATA1 (1 << 15)
57#define CGC_XOR1 (1 << 16)
58#define CGC_CRYPTO (1 << 17)
59#define CGC_GE1 (1 << 19)
60#define CGC_TDM (1 << 20)
61#define CGC_RESERVED ((1 << 18) | (0x6 << 21))
62
42#endif 63#endif