aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-kirkwood/board-dt.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-kirkwood/board-dt.c')
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c25
1 files changed, 18 insertions, 7 deletions
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 2e73e9d53f70..d367aa6b47bb 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -41,16 +41,12 @@ static void __init kirkwood_legacy_clk_init(void)
41 41
42 struct device_node *np = of_find_compatible_node( 42 struct device_node *np = of_find_compatible_node(
43 NULL, NULL, "marvell,kirkwood-gating-clock"); 43 NULL, NULL, "marvell,kirkwood-gating-clock");
44
45 struct of_phandle_args clkspec; 44 struct of_phandle_args clkspec;
45 struct clk *clk;
46 46
47 clkspec.np = np; 47 clkspec.np = np;
48 clkspec.args_count = 1; 48 clkspec.args_count = 1;
49 49
50 clkspec.args[0] = CGC_BIT_GE0;
51 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
52 of_clk_get_from_provider(&clkspec));
53
54 clkspec.args[0] = CGC_BIT_PEX0; 50 clkspec.args[0] = CGC_BIT_PEX0;
55 orion_clkdev_add("0", "pcie", 51 orion_clkdev_add("0", "pcie",
56 of_clk_get_from_provider(&clkspec)); 52 of_clk_get_from_provider(&clkspec));
@@ -59,9 +55,24 @@ static void __init kirkwood_legacy_clk_init(void)
59 orion_clkdev_add("1", "pcie", 55 orion_clkdev_add("1", "pcie",
60 of_clk_get_from_provider(&clkspec)); 56 of_clk_get_from_provider(&clkspec));
61 57
62 clkspec.args[0] = CGC_BIT_GE1; 58 clkspec.args[0] = CGC_BIT_SDIO;
63 orion_clkdev_add(NULL, "mv643xx_eth_port.1", 59 orion_clkdev_add(NULL, "mvsdio",
64 of_clk_get_from_provider(&clkspec)); 60 of_clk_get_from_provider(&clkspec));
61
62 /*
63 * The ethernet interfaces forget the MAC address assigned by
64 * u-boot if the clocks are turned off. Until proper DT support
65 * is available we always enable them for now.
66 */
67 clkspec.args[0] = CGC_BIT_GE0;
68 clk = of_clk_get_from_provider(&clkspec);
69 orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
70 clk_prepare_enable(clk);
71
72 clkspec.args[0] = CGC_BIT_GE1;
73 clk = of_clk_get_from_provider(&clkspec);
74 orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
75 clk_prepare_enable(clk);
65} 76}
66 77
67static void __init kirkwood_of_clk_init(void) 78static void __init kirkwood_of_clk_init(void)