diff options
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r-- | arch/arm/mach-ixp4xx/common.c | 155 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/coyote-pci.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/coyote-setup.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/gtwx5715-pci.c | 28 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/gtwx5715-setup.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixdp425-pci.c | 12 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixdp425-setup.c | 13 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixdpg425-pci.c | 4 |
8 files changed, 91 insertions, 145 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 04490a9f8f6e..0422e906cc9a 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -38,90 +38,6 @@ | |||
38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
39 | #include <asm/mach/time.h> | 39 | #include <asm/mach/time.h> |
40 | 40 | ||
41 | enum ixp4xx_irq_type { | ||
42 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | ||
43 | }; | ||
44 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); | ||
45 | |||
46 | /************************************************************************* | ||
47 | * GPIO acces functions | ||
48 | *************************************************************************/ | ||
49 | |||
50 | /* | ||
51 | * Configure GPIO line for input, interrupt, or output operation | ||
52 | * | ||
53 | * TODO: Enable/disable the irq_desc based on interrupt or output mode. | ||
54 | * TODO: Should these be named ixp4xx_gpio_? | ||
55 | */ | ||
56 | void gpio_line_config(u8 line, u32 style) | ||
57 | { | ||
58 | static const int gpio2irq[] = { | ||
59 | 6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 | ||
60 | }; | ||
61 | u32 enable; | ||
62 | volatile u32 *int_reg; | ||
63 | u32 int_style; | ||
64 | enum ixp4xx_irq_type irq_type; | ||
65 | |||
66 | enable = *IXP4XX_GPIO_GPOER; | ||
67 | |||
68 | if (style & IXP4XX_GPIO_OUT) { | ||
69 | enable &= ~((1) << line); | ||
70 | } else if (style & IXP4XX_GPIO_IN) { | ||
71 | enable |= ((1) << line); | ||
72 | |||
73 | switch (style & IXP4XX_GPIO_INTSTYLE_MASK) | ||
74 | { | ||
75 | case (IXP4XX_GPIO_ACTIVE_HIGH): | ||
76 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; | ||
77 | irq_type = IXP4XX_IRQ_LEVEL; | ||
78 | break; | ||
79 | case (IXP4XX_GPIO_ACTIVE_LOW): | ||
80 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; | ||
81 | irq_type = IXP4XX_IRQ_LEVEL; | ||
82 | break; | ||
83 | case (IXP4XX_GPIO_RISING_EDGE): | ||
84 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; | ||
85 | irq_type = IXP4XX_IRQ_EDGE; | ||
86 | break; | ||
87 | case (IXP4XX_GPIO_FALLING_EDGE): | ||
88 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; | ||
89 | irq_type = IXP4XX_IRQ_EDGE; | ||
90 | break; | ||
91 | case (IXP4XX_GPIO_TRANSITIONAL): | ||
92 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; | ||
93 | irq_type = IXP4XX_IRQ_EDGE; | ||
94 | break; | ||
95 | default: | ||
96 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; | ||
97 | irq_type = IXP4XX_IRQ_LEVEL; | ||
98 | break; | ||
99 | } | ||
100 | |||
101 | if (style & IXP4XX_GPIO_INTSTYLE_MASK) | ||
102 | ixp4xx_config_irq(gpio2irq[line], irq_type); | ||
103 | |||
104 | if (line >= 8) { /* pins 8-15 */ | ||
105 | line -= 8; | ||
106 | int_reg = IXP4XX_GPIO_GPIT2R; | ||
107 | } | ||
108 | else { /* pins 0-7 */ | ||
109 | int_reg = IXP4XX_GPIO_GPIT1R; | ||
110 | } | ||
111 | |||
112 | /* Clear the style for the appropriate pin */ | ||
113 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << | ||
114 | (line * IXP4XX_GPIO_STYLE_SIZE)); | ||
115 | |||
116 | /* Set the new style */ | ||
117 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); | ||
118 | } | ||
119 | |||
120 | *IXP4XX_GPIO_GPOER = enable; | ||
121 | } | ||
122 | |||
123 | EXPORT_SYMBOL(gpio_line_config); | ||
124 | |||
125 | /************************************************************************* | 41 | /************************************************************************* |
126 | * IXP4xx chipset I/O mapping | 42 | * IXP4xx chipset I/O mapping |
127 | *************************************************************************/ | 43 | *************************************************************************/ |
@@ -165,6 +81,69 @@ void __init ixp4xx_map_io(void) | |||
165 | * (be it PCI or something else) configures that GPIO line | 81 | * (be it PCI or something else) configures that GPIO line |
166 | * as an IRQ. | 82 | * as an IRQ. |
167 | **************************************************************************/ | 83 | **************************************************************************/ |
84 | enum ixp4xx_irq_type { | ||
85 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | ||
86 | }; | ||
87 | |||
88 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); | ||
89 | |||
90 | /* | ||
91 | * IRQ -> GPIO mapping table | ||
92 | */ | ||
93 | static int irq2gpio[32] = { | ||
94 | -1, -1, -1, -1, -1, -1, 0, 1, | ||
95 | -1, -1, -1, -1, -1, -1, -1, -1, | ||
96 | -1, -1, -1, 2, 3, 4, 5, 6, | ||
97 | 7, 8, 9, 10, 11, 12, -1, -1, | ||
98 | }; | ||
99 | |||
100 | static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) | ||
101 | { | ||
102 | int line = irq2gpio[irq]; | ||
103 | u32 int_style; | ||
104 | enum ixp4xx_irq_type irq_type; | ||
105 | volatile u32 *int_reg; | ||
106 | |||
107 | /* | ||
108 | * Only for GPIO IRQs | ||
109 | */ | ||
110 | if (line < 0) | ||
111 | return -EINVAL; | ||
112 | |||
113 | if (type & IRQT_BOTHEDGE) { | ||
114 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; | ||
115 | irq_type = IXP4XX_IRQ_EDGE; | ||
116 | } else if (type & IRQT_RISING) { | ||
117 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; | ||
118 | irq_type = IXP4XX_IRQ_EDGE; | ||
119 | } else if (type & IRQT_FALLING) { | ||
120 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; | ||
121 | irq_type = IXP4XX_IRQ_EDGE; | ||
122 | } else if (type & IRQT_HIGH) { | ||
123 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; | ||
124 | irq_type = IXP4XX_IRQ_LEVEL; | ||
125 | } else if (type & IRQT_LOW) { | ||
126 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; | ||
127 | irq_type = IXP4XX_IRQ_LEVEL; | ||
128 | } | ||
129 | |||
130 | ixp4xx_config_irq(irq, irq_type); | ||
131 | |||
132 | if (line >= 8) { /* pins 8-15 */ | ||
133 | line -= 8; | ||
134 | int_reg = IXP4XX_GPIO_GPIT2R; | ||
135 | } else { /* pins 0-7 */ | ||
136 | int_reg = IXP4XX_GPIO_GPIT1R; | ||
137 | } | ||
138 | |||
139 | /* Clear the style for the appropriate pin */ | ||
140 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << | ||
141 | (line * IXP4XX_GPIO_STYLE_SIZE)); | ||
142 | |||
143 | /* Set the new style */ | ||
144 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); | ||
145 | } | ||
146 | |||
168 | static void ixp4xx_irq_mask(unsigned int irq) | 147 | static void ixp4xx_irq_mask(unsigned int irq) |
169 | { | 148 | { |
170 | if (cpu_is_ixp46x() && irq >= 32) | 149 | if (cpu_is_ixp46x() && irq >= 32) |
@@ -183,12 +162,6 @@ static void ixp4xx_irq_unmask(unsigned int irq) | |||
183 | 162 | ||
184 | static void ixp4xx_irq_ack(unsigned int irq) | 163 | static void ixp4xx_irq_ack(unsigned int irq) |
185 | { | 164 | { |
186 | static int irq2gpio[32] = { | ||
187 | -1, -1, -1, -1, -1, -1, 0, 1, | ||
188 | -1, -1, -1, -1, -1, -1, -1, -1, | ||
189 | -1, -1, -1, 2, 3, 4, 5, 6, | ||
190 | 7, 8, 9, 10, 11, 12, -1, -1, | ||
191 | }; | ||
192 | int line = (irq < 32) ? irq2gpio[irq] : -1; | 165 | int line = (irq < 32) ? irq2gpio[irq] : -1; |
193 | 166 | ||
194 | if (line >= 0) | 167 | if (line >= 0) |
@@ -209,12 +182,14 @@ static struct irqchip ixp4xx_irq_level_chip = { | |||
209 | .ack = ixp4xx_irq_mask, | 182 | .ack = ixp4xx_irq_mask, |
210 | .mask = ixp4xx_irq_mask, | 183 | .mask = ixp4xx_irq_mask, |
211 | .unmask = ixp4xx_irq_level_unmask, | 184 | .unmask = ixp4xx_irq_level_unmask, |
185 | .type = ixp4xx_set_irq_type | ||
212 | }; | 186 | }; |
213 | 187 | ||
214 | static struct irqchip ixp4xx_irq_edge_chip = { | 188 | static struct irqchip ixp4xx_irq_edge_chip = { |
215 | .ack = ixp4xx_irq_ack, | 189 | .ack = ixp4xx_irq_ack, |
216 | .mask = ixp4xx_irq_mask, | 190 | .mask = ixp4xx_irq_mask, |
217 | .unmask = ixp4xx_irq_unmask, | 191 | .unmask = ixp4xx_irq_unmask, |
192 | .type = ixp4xx_set_irq_type | ||
218 | }; | 193 | }; |
219 | 194 | ||
220 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) | 195 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) |
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index afafb42ae129..60de8a94cff5 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -30,11 +30,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); | |||
30 | 30 | ||
31 | void __init coyote_pci_preinit(void) | 31 | void __init coyote_pci_preinit(void) |
32 | { | 32 | { |
33 | gpio_line_config(COYOTE_PCI_SLOT0_PIN, | 33 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); |
34 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | 34 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW); |
35 | |||
36 | gpio_line_config(COYOTE_PCI_SLOT1_PIN, | ||
37 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | ||
38 | 35 | ||
39 | gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); | 36 | gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); |
40 | gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); | 37 | gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); |
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index 411ea9996190..8b2f25322452 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c | |||
@@ -24,11 +24,6 @@ | |||
24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
25 | #include <asm/mach/flash.h> | 25 | #include <asm/mach/flash.h> |
26 | 26 | ||
27 | void __init coyote_map_io(void) | ||
28 | { | ||
29 | ixp4xx_map_io(); | ||
30 | } | ||
31 | |||
32 | static struct flash_platform_data coyote_flash_data = { | 27 | static struct flash_platform_data coyote_flash_data = { |
33 | .map_name = "cfi_probe", | 28 | .map_name = "cfi_probe", |
34 | .width = 2, | 29 | .width = 2, |
@@ -107,7 +102,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") | |||
107 | .phys_ram = PHYS_OFFSET, | 102 | .phys_ram = PHYS_OFFSET, |
108 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 103 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
109 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 104 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
110 | .map_io = coyote_map_io, | 105 | .map_io = ixp4xx_map_io, |
111 | .init_irq = ixp4xx_init_irq, | 106 | .init_irq = ixp4xx_init_irq, |
112 | .timer = &ixp4xx_timer, | 107 | .timer = &ixp4xx_timer, |
113 | .boot_params = 0x0100, | 108 | .boot_params = 0x0100, |
@@ -125,7 +120,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425") | |||
125 | .phys_ram = PHYS_OFFSET, | 120 | .phys_ram = PHYS_OFFSET, |
126 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 121 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
127 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 122 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
128 | .map_io = coyote_map_io, | 123 | .map_io = ixp4xx_map_io, |
129 | .init_irq = ixp4xx_init_irq, | 124 | .init_irq = ixp4xx_init_irq, |
130 | .timer = &ixp4xx_timer, | 125 | .timer = &ixp4xx_timer, |
131 | .boot_params = 0x0100, | 126 | .boot_params = 0x0100, |
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index b18035824e3e..a66484b63d36 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c | |||
@@ -35,26 +35,20 @@ extern void ixp4xx_pci_preinit(void); | |||
35 | extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); | 35 | extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); |
36 | extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); | 36 | extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); |
37 | 37 | ||
38 | /* | ||
39 | * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h | ||
40 | * Slot 0 isn't actually populated with a card connector but | ||
41 | * we initialize it anyway in case a future version has the | ||
42 | * slot populated or someone with good soldering skills has | ||
43 | * some free time. | ||
44 | */ | ||
45 | |||
46 | |||
47 | static void gtwx5715_init_gpio(u8 pin, u32 style) | ||
48 | { | ||
49 | gpio_line_config(pin, style | IXP4XX_GPIO_ACTIVE_LOW); | ||
50 | |||
51 | if (style & IXP4XX_GPIO_IN) gpio_line_isr_clear(pin); | ||
52 | } | ||
53 | 38 | ||
39 | /* | ||
40 | * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h | ||
41 | * Slot 0 isn't actually populated with a card connector but | ||
42 | * we initialize it anyway in case a future version has the | ||
43 | * slot populated or someone with good soldering skills has | ||
44 | * some free time. | ||
45 | */ | ||
54 | void __init gtwx5715_pci_preinit(void) | 46 | void __init gtwx5715_pci_preinit(void) |
55 | { | 47 | { |
56 | gtwx5715_init_gpio(GTWX5715_PCI_SLOT0_INTA_GPIO, IXP4XX_GPIO_IN); | 48 | set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW); |
57 | gtwx5715_init_gpio(GTWX5715_PCI_SLOT1_INTA_GPIO, IXP4XX_GPIO_IN); | 49 | set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW); |
50 | set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW); | ||
51 | set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW); | ||
58 | 52 | ||
59 | ixp4xx_pci_preinit(); | 53 | ixp4xx_pci_preinit(); |
60 | } | 54 | } |
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 333459d6aa46..3fd92c5cbaa8 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c | |||
@@ -101,12 +101,6 @@ static struct platform_device gtwx5715_uart_device = { | |||
101 | .resource = gtwx5715_uart_resources, | 101 | .resource = gtwx5715_uart_resources, |
102 | }; | 102 | }; |
103 | 103 | ||
104 | |||
105 | void __init gtwx5715_map_io(void) | ||
106 | { | ||
107 | ixp4xx_map_io(); | ||
108 | } | ||
109 | |||
110 | static struct flash_platform_data gtwx5715_flash_data = { | 104 | static struct flash_platform_data gtwx5715_flash_data = { |
111 | .map_name = "cfi_probe", | 105 | .map_name = "cfi_probe", |
112 | .width = 2, | 106 | .width = 2, |
@@ -144,7 +138,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") | |||
144 | .phys_ram = PHYS_OFFSET, | 138 | .phys_ram = PHYS_OFFSET, |
145 | .phys_io = IXP4XX_UART2_BASE_PHYS, | 139 | .phys_io = IXP4XX_UART2_BASE_PHYS, |
146 | .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc, | 140 | .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc, |
147 | .map_io = gtwx5715_map_io, | 141 | .map_io = ixp4xx_map_io, |
148 | .init_irq = ixp4xx_init_irq, | 142 | .init_irq = ixp4xx_init_irq, |
149 | .timer = &ixp4xx_timer, | 143 | .timer = &ixp4xx_timer, |
150 | .boot_params = 0x0100, | 144 | .boot_params = 0x0100, |
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index c2ab9ebb5980..f9a1d3e7d692 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -27,14 +27,10 @@ | |||
27 | 27 | ||
28 | void __init ixdp425_pci_preinit(void) | 28 | void __init ixdp425_pci_preinit(void) |
29 | { | 29 | { |
30 | gpio_line_config(IXDP425_PCI_INTA_PIN, | 30 | set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW); |
31 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | 31 | set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW); |
32 | gpio_line_config(IXDP425_PCI_INTB_PIN, | 32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW); |
33 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | 33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW); |
34 | gpio_line_config(IXDP425_PCI_INTC_PIN, | ||
35 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | ||
36 | gpio_line_config(IXDP425_PCI_INTD_PIN, | ||
37 | IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | ||
38 | 34 | ||
39 | gpio_line_isr_clear(IXDP425_PCI_INTA_PIN); | 35 | gpio_line_isr_clear(IXDP425_PCI_INTA_PIN); |
40 | gpio_line_isr_clear(IXDP425_PCI_INTB_PIN); | 36 | gpio_line_isr_clear(IXDP425_PCI_INTB_PIN); |
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index fa0646c8693b..6c14ff3c23a0 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c | |||
@@ -24,11 +24,6 @@ | |||
24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
25 | #include <asm/mach/flash.h> | 25 | #include <asm/mach/flash.h> |
26 | 26 | ||
27 | void __init ixdp425_map_io(void) | ||
28 | { | ||
29 | ixp4xx_map_io(); | ||
30 | } | ||
31 | |||
32 | static struct flash_platform_data ixdp425_flash_data = { | 27 | static struct flash_platform_data ixdp425_flash_data = { |
33 | .map_name = "cfi_probe", | 28 | .map_name = "cfi_probe", |
34 | .width = 2, | 29 | .width = 2, |
@@ -133,7 +128,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") | |||
133 | .phys_ram = PHYS_OFFSET, | 128 | .phys_ram = PHYS_OFFSET, |
134 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 129 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
135 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 130 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
136 | .map_io = ixdp425_map_io, | 131 | .map_io = ixp4xx_map_io, |
137 | .init_irq = ixp4xx_init_irq, | 132 | .init_irq = ixp4xx_init_irq, |
138 | .timer = &ixp4xx_timer, | 133 | .timer = &ixp4xx_timer, |
139 | .boot_params = 0x0100, | 134 | .boot_params = 0x0100, |
@@ -145,7 +140,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") | |||
145 | .phys_ram = PHYS_OFFSET, | 140 | .phys_ram = PHYS_OFFSET, |
146 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 141 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
147 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 142 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
148 | .map_io = ixdp425_map_io, | 143 | .map_io = ixp4xx_map_io, |
149 | .init_irq = ixp4xx_init_irq, | 144 | .init_irq = ixp4xx_init_irq, |
150 | .timer = &ixp4xx_timer, | 145 | .timer = &ixp4xx_timer, |
151 | .boot_params = 0x0100, | 146 | .boot_params = 0x0100, |
@@ -157,7 +152,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") | |||
157 | .phys_ram = PHYS_OFFSET, | 152 | .phys_ram = PHYS_OFFSET, |
158 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 153 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
159 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 154 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
160 | .map_io = ixdp425_map_io, | 155 | .map_io = ixp4xx_map_io, |
161 | .init_irq = ixp4xx_init_irq, | 156 | .init_irq = ixp4xx_init_irq, |
162 | .timer = &ixp4xx_timer, | 157 | .timer = &ixp4xx_timer, |
163 | .boot_params = 0x0100, | 158 | .boot_params = 0x0100, |
@@ -176,7 +171,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform") | |||
176 | .phys_ram = PHYS_OFFSET, | 171 | .phys_ram = PHYS_OFFSET, |
177 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | 172 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
178 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | 173 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, |
179 | .map_io = ixdp425_map_io, | 174 | .map_io = ixp4xx_map_io, |
180 | .init_irq = ixp4xx_init_irq, | 175 | .init_irq = ixp4xx_init_irq, |
181 | .timer = &ixp4xx_timer, | 176 | .timer = &ixp4xx_timer, |
182 | .boot_params = 0x0100, | 177 | .boot_params = 0x0100, |
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index ce4563f00676..fe5e7660de1d 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c | |||
@@ -29,8 +29,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); | |||
29 | 29 | ||
30 | void __init ixdpg425_pci_preinit(void) | 30 | void __init ixdpg425_pci_preinit(void) |
31 | { | 31 | { |
32 | gpio_line_config(6, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | 32 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); |
33 | gpio_line_config(7, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); | 33 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW); |
34 | 34 | ||
35 | gpio_line_isr_clear(6); | 35 | gpio_line_isr_clear(6); |
36 | gpio_line_isr_clear(7); | 36 | gpio_line_isr_clear(7); |