diff options
Diffstat (limited to 'arch/arm/mach-ixp4xx')
-rw-r--r-- | arch/arm/mach-ixp4xx/fsg-setup.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/dma.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/io.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/memory.h | 13 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/qmgr.h | 35 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | 44 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/nas100d-setup.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/nslu2-setup.c | 5 |
8 files changed, 76 insertions, 60 deletions
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index e7c6386782ed..5add22fc9899 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c | |||
@@ -177,7 +177,6 @@ static irqreturn_t fsg_reset_handler(int irq, void *dev_id) | |||
177 | 177 | ||
178 | static void __init fsg_init(void) | 178 | static void __init fsg_init(void) |
179 | { | 179 | { |
180 | DECLARE_MAC_BUF(mac_buf); | ||
181 | uint8_t __iomem *f; | 180 | uint8_t __iomem *f; |
182 | 181 | ||
183 | ixp4xx_sys_init(); | 182 | ixp4xx_sys_init(); |
@@ -256,10 +255,10 @@ static void __init fsg_init(void) | |||
256 | #endif | 255 | #endif |
257 | iounmap(f); | 256 | iounmap(f); |
258 | } | 257 | } |
259 | printk(KERN_INFO "FSG: Using MAC address %s for port 0\n", | 258 | printk(KERN_INFO "FSG: Using MAC address %pM for port 0\n", |
260 | print_mac(mac_buf, fsg_plat_eth[0].hwaddr)); | 259 | fsg_plat_eth[0].hwaddr); |
261 | printk(KERN_INFO "FSG: Using MAC address %s for port 1\n", | 260 | printk(KERN_INFO "FSG: Using MAC address %pM for port 1\n", |
262 | print_mac(mac_buf, fsg_plat_eth[1].hwaddr)); | 261 | fsg_plat_eth[1].hwaddr); |
263 | 262 | ||
264 | } | 263 | } |
265 | 264 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/dma.h b/arch/arm/mach-ixp4xx/include/mach/dma.h deleted file mode 100644 index 00c5070c0201..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/dma.h +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ixp4xx/include/mach/dma.h | ||
3 | * | ||
4 | * Copyright (C) 2001-2004 MontaVista Software, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_DMA_H | ||
12 | #define __ASM_ARCH_DMA_H | ||
13 | |||
14 | #include <linux/device.h> | ||
15 | #include <asm/page.h> | ||
16 | #include <asm/sizes.h> | ||
17 | #include <mach/hardware.h> | ||
18 | |||
19 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) | ||
20 | |||
21 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 319948e31bec..ce63048d45eb 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h | |||
@@ -49,8 +49,6 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |||
49 | 49 | ||
50 | #else | 50 | #else |
51 | 51 | ||
52 | #include <linux/mm.h> | ||
53 | |||
54 | /* | 52 | /* |
55 | * In the case of using indirect PCI, we simply return the actual PCI | 53 | * In the case of using indirect PCI, we simply return the actual PCI |
56 | * address and our read/write implementation use that to drive the | 54 | * address and our read/write implementation use that to drive the |
@@ -241,7 +239,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | |||
241 | 239 | ||
242 | #ifndef CONFIG_PCI | 240 | #ifndef CONFIG_PCI |
243 | 241 | ||
244 | #define __io(v) v | 242 | #define __io(v) __typesafe_io(v) |
245 | 243 | ||
246 | #else | 244 | #else |
247 | 245 | ||
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index c4d2830ac987..98f5e5e20980 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h | |||
@@ -22,19 +22,8 @@ void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); | |||
22 | ixp4xx_adjust_zones(node, size, holes) | 22 | ixp4xx_adjust_zones(node, size, holes) |
23 | 23 | ||
24 | #define ISA_DMA_THRESHOLD (SZ_64M - 1) | 24 | #define ISA_DMA_THRESHOLD (SZ_64M - 1) |
25 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) | ||
25 | 26 | ||
26 | #endif | 27 | #endif |
27 | 28 | ||
28 | /* | ||
29 | * Virtual view <-> DMA view memory address translations | ||
30 | * virt_to_bus: Used to translate the virtual address to an | ||
31 | * address suitable to be passed to set_dma_addr | ||
32 | * bus_to_virt: Used to convert an address for DMA operations | ||
33 | * to an address that the kernel can use. | ||
34 | * | ||
35 | * These are dummies for now. | ||
36 | */ | ||
37 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
38 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
39 | |||
40 | #endif | 29 | #endif |
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h index 1e52b95cede5..0cbe6ceb67c5 100644 --- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h +++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h | |||
@@ -12,6 +12,8 @@ | |||
12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | 14 | ||
15 | #define DEBUG_QMGR 0 | ||
16 | |||
15 | #define HALF_QUEUES 32 | 17 | #define HALF_QUEUES 32 |
16 | #define QUEUES 64 /* only 32 lower queues currently supported */ | 18 | #define QUEUES 64 /* only 32 lower queues currently supported */ |
17 | #define MAX_QUEUE_LENGTH 4 /* in dwords */ | 19 | #define MAX_QUEUE_LENGTH 4 /* in dwords */ |
@@ -61,22 +63,51 @@ void qmgr_enable_irq(unsigned int queue); | |||
61 | void qmgr_disable_irq(unsigned int queue); | 63 | void qmgr_disable_irq(unsigned int queue); |
62 | 64 | ||
63 | /* request_ and release_queue() must be called from non-IRQ context */ | 65 | /* request_ and release_queue() must be called from non-IRQ context */ |
66 | |||
67 | #if DEBUG_QMGR | ||
68 | extern char qmgr_queue_descs[QUEUES][32]; | ||
69 | |||
64 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | 70 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, |
65 | unsigned int nearly_empty_watermark, | 71 | unsigned int nearly_empty_watermark, |
66 | unsigned int nearly_full_watermark); | 72 | unsigned int nearly_full_watermark, |
73 | const char *desc_format, const char* name); | ||
74 | #else | ||
75 | int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | ||
76 | unsigned int nearly_empty_watermark, | ||
77 | unsigned int nearly_full_watermark); | ||
78 | #define qmgr_request_queue(queue, len, nearly_empty_watermark, \ | ||
79 | nearly_full_watermark, desc_format, name) \ | ||
80 | __qmgr_request_queue(queue, len, nearly_empty_watermark, \ | ||
81 | nearly_full_watermark) | ||
82 | #endif | ||
83 | |||
67 | void qmgr_release_queue(unsigned int queue); | 84 | void qmgr_release_queue(unsigned int queue); |
68 | 85 | ||
69 | 86 | ||
70 | static inline void qmgr_put_entry(unsigned int queue, u32 val) | 87 | static inline void qmgr_put_entry(unsigned int queue, u32 val) |
71 | { | 88 | { |
72 | extern struct qmgr_regs __iomem *qmgr_regs; | 89 | extern struct qmgr_regs __iomem *qmgr_regs; |
90 | #if DEBUG_QMGR | ||
91 | BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ | ||
92 | |||
93 | printk(KERN_DEBUG "Queue %s(%i) put %X\n", | ||
94 | qmgr_queue_descs[queue], queue, val); | ||
95 | #endif | ||
73 | __raw_writel(val, &qmgr_regs->acc[queue][0]); | 96 | __raw_writel(val, &qmgr_regs->acc[queue][0]); |
74 | } | 97 | } |
75 | 98 | ||
76 | static inline u32 qmgr_get_entry(unsigned int queue) | 99 | static inline u32 qmgr_get_entry(unsigned int queue) |
77 | { | 100 | { |
101 | u32 val; | ||
78 | extern struct qmgr_regs __iomem *qmgr_regs; | 102 | extern struct qmgr_regs __iomem *qmgr_regs; |
79 | return __raw_readl(&qmgr_regs->acc[queue][0]); | 103 | val = __raw_readl(&qmgr_regs->acc[queue][0]); |
104 | #if DEBUG_QMGR | ||
105 | BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ | ||
106 | |||
107 | printk(KERN_DEBUG "Queue %s(%i) get %X\n", | ||
108 | qmgr_queue_descs[queue], queue, val); | ||
109 | #endif | ||
110 | return val; | ||
80 | } | 111 | } |
81 | 112 | ||
82 | static inline int qmgr_get_stat1(unsigned int queue) | 113 | static inline int qmgr_get_stat1(unsigned int queue) |
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c index c6cb069a5a83..bfddc73d0a20 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | |||
@@ -14,8 +14,6 @@ | |||
14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
15 | #include <mach/qmgr.h> | 15 | #include <mach/qmgr.h> |
16 | 16 | ||
17 | #define DEBUG 0 | ||
18 | |||
19 | struct qmgr_regs __iomem *qmgr_regs; | 17 | struct qmgr_regs __iomem *qmgr_regs; |
20 | static struct resource *mem_res; | 18 | static struct resource *mem_res; |
21 | static spinlock_t qmgr_lock; | 19 | static spinlock_t qmgr_lock; |
@@ -23,6 +21,10 @@ static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ | |||
23 | static void (*irq_handlers[HALF_QUEUES])(void *pdev); | 21 | static void (*irq_handlers[HALF_QUEUES])(void *pdev); |
24 | static void *irq_pdevs[HALF_QUEUES]; | 22 | static void *irq_pdevs[HALF_QUEUES]; |
25 | 23 | ||
24 | #if DEBUG_QMGR | ||
25 | char qmgr_queue_descs[QUEUES][32]; | ||
26 | #endif | ||
27 | |||
26 | void qmgr_set_irq(unsigned int queue, int src, | 28 | void qmgr_set_irq(unsigned int queue, int src, |
27 | void (*handler)(void *pdev), void *pdev) | 29 | void (*handler)(void *pdev), void *pdev) |
28 | { | 30 | { |
@@ -70,6 +72,7 @@ void qmgr_disable_irq(unsigned int queue) | |||
70 | spin_lock_irqsave(&qmgr_lock, flags); | 72 | spin_lock_irqsave(&qmgr_lock, flags); |
71 | __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), | 73 | __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), |
72 | &qmgr_regs->irqen[0]); | 74 | &qmgr_regs->irqen[0]); |
75 | __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */ | ||
73 | spin_unlock_irqrestore(&qmgr_lock, flags); | 76 | spin_unlock_irqrestore(&qmgr_lock, flags); |
74 | } | 77 | } |
75 | 78 | ||
@@ -81,9 +84,16 @@ static inline void shift_mask(u32 *mask) | |||
81 | mask[0] <<= 1; | 84 | mask[0] <<= 1; |
82 | } | 85 | } |
83 | 86 | ||
87 | #if DEBUG_QMGR | ||
84 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | 88 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, |
85 | unsigned int nearly_empty_watermark, | 89 | unsigned int nearly_empty_watermark, |
86 | unsigned int nearly_full_watermark) | 90 | unsigned int nearly_full_watermark, |
91 | const char *desc_format, const char* name) | ||
92 | #else | ||
93 | int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | ||
94 | unsigned int nearly_empty_watermark, | ||
95 | unsigned int nearly_full_watermark) | ||
96 | #endif | ||
87 | { | 97 | { |
88 | u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ | 98 | u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ |
89 | int err; | 99 | int err; |
@@ -151,12 +161,13 @@ int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | |||
151 | used_sram_bitmap[2] |= mask[2]; | 161 | used_sram_bitmap[2] |= mask[2]; |
152 | used_sram_bitmap[3] |= mask[3]; | 162 | used_sram_bitmap[3] |= mask[3]; |
153 | __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); | 163 | __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); |
154 | spin_unlock_irq(&qmgr_lock); | 164 | #if DEBUG_QMGR |
155 | 165 | snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]), | |
156 | #if DEBUG | 166 | desc_format, name); |
157 | printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n", | 167 | printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n", |
158 | queue, addr); | 168 | qmgr_queue_descs[queue], queue, addr); |
159 | #endif | 169 | #endif |
170 | spin_unlock_irq(&qmgr_lock); | ||
160 | return 0; | 171 | return 0; |
161 | 172 | ||
162 | err: | 173 | err: |
@@ -189,6 +200,11 @@ void qmgr_release_queue(unsigned int queue) | |||
189 | while (addr--) | 200 | while (addr--) |
190 | shift_mask(mask); | 201 | shift_mask(mask); |
191 | 202 | ||
203 | #if DEBUG_QMGR | ||
204 | printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n", | ||
205 | qmgr_queue_descs[queue], queue); | ||
206 | qmgr_queue_descs[queue][0] = '\x0'; | ||
207 | #endif | ||
192 | __raw_writel(0, &qmgr_regs->sram[queue]); | 208 | __raw_writel(0, &qmgr_regs->sram[queue]); |
193 | 209 | ||
194 | used_sram_bitmap[0] &= ~mask[0]; | 210 | used_sram_bitmap[0] &= ~mask[0]; |
@@ -199,9 +215,10 @@ void qmgr_release_queue(unsigned int queue) | |||
199 | spin_unlock_irq(&qmgr_lock); | 215 | spin_unlock_irq(&qmgr_lock); |
200 | 216 | ||
201 | module_put(THIS_MODULE); | 217 | module_put(THIS_MODULE); |
202 | #if DEBUG | 218 | |
203 | printk(KERN_DEBUG "qmgr: released queue %i\n", queue); | 219 | while ((addr = qmgr_get_entry(queue))) |
204 | #endif | 220 | printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n", |
221 | queue, addr); | ||
205 | } | 222 | } |
206 | 223 | ||
207 | static int qmgr_init(void) | 224 | static int qmgr_init(void) |
@@ -272,5 +289,10 @@ EXPORT_SYMBOL(qmgr_regs); | |||
272 | EXPORT_SYMBOL(qmgr_set_irq); | 289 | EXPORT_SYMBOL(qmgr_set_irq); |
273 | EXPORT_SYMBOL(qmgr_enable_irq); | 290 | EXPORT_SYMBOL(qmgr_enable_irq); |
274 | EXPORT_SYMBOL(qmgr_disable_irq); | 291 | EXPORT_SYMBOL(qmgr_disable_irq); |
292 | #if DEBUG_QMGR | ||
293 | EXPORT_SYMBOL(qmgr_queue_descs); | ||
275 | EXPORT_SYMBOL(qmgr_request_queue); | 294 | EXPORT_SYMBOL(qmgr_request_queue); |
295 | #else | ||
296 | EXPORT_SYMBOL(__qmgr_request_queue); | ||
297 | #endif | ||
276 | EXPORT_SYMBOL(qmgr_release_queue); | 298 | EXPORT_SYMBOL(qmgr_release_queue); |
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 0acd95ecf27e..921c947b5b6b 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c | |||
@@ -231,7 +231,6 @@ static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) | |||
231 | 231 | ||
232 | static void __init nas100d_init(void) | 232 | static void __init nas100d_init(void) |
233 | { | 233 | { |
234 | DECLARE_MAC_BUF(mac_buf); | ||
235 | uint8_t __iomem *f; | 234 | uint8_t __iomem *f; |
236 | int i; | 235 | int i; |
237 | 236 | ||
@@ -294,8 +293,8 @@ static void __init nas100d_init(void) | |||
294 | #endif | 293 | #endif |
295 | iounmap(f); | 294 | iounmap(f); |
296 | } | 295 | } |
297 | printk(KERN_INFO "NAS100D: Using MAC address %s for port 0\n", | 296 | printk(KERN_INFO "NAS100D: Using MAC address %pM for port 0\n", |
298 | print_mac(mac_buf, nas100d_plat_eth[0].hwaddr)); | 297 | nas100d_plat_eth[0].hwaddr); |
299 | 298 | ||
300 | } | 299 | } |
301 | 300 | ||
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index bc9d920ae54f..ff6a08d02cc4 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c | |||
@@ -220,7 +220,6 @@ static struct sys_timer nslu2_timer = { | |||
220 | 220 | ||
221 | static void __init nslu2_init(void) | 221 | static void __init nslu2_init(void) |
222 | { | 222 | { |
223 | DECLARE_MAC_BUF(mac_buf); | ||
224 | uint8_t __iomem *f; | 223 | uint8_t __iomem *f; |
225 | int i; | 224 | int i; |
226 | 225 | ||
@@ -275,8 +274,8 @@ static void __init nslu2_init(void) | |||
275 | #endif | 274 | #endif |
276 | iounmap(f); | 275 | iounmap(f); |
277 | } | 276 | } |
278 | printk(KERN_INFO "NSLU2: Using MAC address %s for port 0\n", | 277 | printk(KERN_INFO "NSLU2: Using MAC address %pM for port 0\n", |
279 | print_mac(mac_buf, nslu2_plat_eth[0].hwaddr)); | 278 | nslu2_plat_eth[0].hwaddr); |
280 | 279 | ||
281 | } | 280 | } |
282 | 281 | ||