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-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c7
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/cpu.h9
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 192538a04575..f74a460d4a32 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -27,6 +27,7 @@
27#include <linux/device.h> 27#include <linux/device.h>
28#include <asm/dma-mapping.h> 28#include <asm/dma-mapping.h>
29 29
30#include <asm/cputype.h>
30#include <asm/io.h> 31#include <asm/io.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
32#include <asm/sizes.h> 33#include <asm/sizes.h>
@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
366 367
367void __init ixp4xx_pci_preinit(void) 368void __init ixp4xx_pci_preinit(void)
368{ 369{
369 unsigned long processor_id; 370 unsigned long cpuid = read_cpuid_id();
370
371 asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
372 371
373 /* 372 /*
374 * Determine which PCI read method to use. 373 * Determine which PCI read method to use.
375 * Rev 0 IXP425 requires workaround. 374 * Rev 0 IXP425 requires workaround.
376 */ 375 */
377 if (!(processor_id & 0xf) && cpu_is_ixp42x()) { 376 if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
378 printk("PCI: IXP42x A0 silicon detected - " 377 printk("PCI: IXP42x A0 silicon detected - "
379 "PCI Non-Prefetch Workaround Enabled\n"); 378 "PCI Non-Prefetch Workaround Enabled\n");
380 ixp4xx_pci_read = ixp4xx_pci_read_errata; 379 ixp4xx_pci_read = ixp4xx_pci_read_errata;
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index ff8aa2393bf9..51bd69c46d94 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,18 +14,19 @@
14#ifndef __ASM_ARCH_CPU_H__ 14#ifndef __ASM_ARCH_CPU_H__
15#define __ASM_ARCH_CPU_H__ 15#define __ASM_ARCH_CPU_H__
16 16
17extern unsigned int processor_id; 17#include <asm/cputype.h>
18
18/* Processor id value in CP15 Register 0 */ 19/* Processor id value in CP15 Register 0 */
19#define IXP425_PROCESSOR_ID_VALUE 0x690541c0 20#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
20#define IXP435_PROCESSOR_ID_VALUE 0x69054040 21#define IXP435_PROCESSOR_ID_VALUE 0x69054040
21#define IXP465_PROCESSOR_ID_VALUE 0x69054200 22#define IXP465_PROCESSOR_ID_VALUE 0x69054200
22#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 23#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
23 24
24#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ 25#define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
25 IXP425_PROCESSOR_ID_VALUE) 26 IXP425_PROCESSOR_ID_VALUE)
26#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ 27#define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
27 IXP435_PROCESSOR_ID_VALUE) 28 IXP435_PROCESSOR_ID_VALUE)
28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ 29#define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
29 IXP465_PROCESSOR_ID_VALUE) 30 IXP465_PROCESSOR_ID_VALUE)
30 31
31static inline u32 ixp4xx_read_feature_bits(void) 32static inline u32 ixp4xx_read_feature_bits(void)